Datasheet ML2726 Datasheet (RFMD)

ML2726

N

N

NEN

A

K

T

VSS

L

V

V
V

V

A

A

2.4GHz Low-IF 2.0Mbps FSK Transceiver
Preliminary Datasheet

GENERAL DESCRIPTION

The ML2726 is a fully integrated 2.0Mbps frequency
shift keyed (FSK) transceiver that operates in the
unlicensed 2.4GHz ISM frequency band. The device
has been optimized for digital cordless telephone
applications and includes all the frequency generation,
receive and transmit functions. Automatically adjusted
filters eliminate mechanical tuning. Closed loop
modulation eliminates frequency drift and permits
practically unlimited TX duration. The transmitter
generates a 3dBm FSK output signal.

The 2.0Mbps data rate permits data spreading, such as
Direct Sequence Spread Spectrum (DSSS) modulation,
which improves range. The dual conversion Low-IF
receiver has all of the sensitivity and selectivity
advantages of a traditional super-heterodyne without
requiring costly, bulky external filters, while providing
the integration advantages of direct conversion.

The phase locked loop (PLL) synthesizer is completely
integrated, including the voltage controlled oscillator
(VCO), tuning circuits, and VCO resonator. This allows
the ML2726 to be used in frequency hopped spread
spectrum (FHSS) applications.

FEATURES

 Complete 2.4GHz FSK Transceiver

- High data rate (2.048 Mbps)

- -80dBm sensitivity @ 0.1% BER (typ)

- 3dBm Output Power (differential, typ)

 Closed Loop TX Modulation

 Low IF Receiver: No external IF filters required.

 Fully Integrated frequency synthesizer:

- No external resonator required.

 Sigma-Delta Fractional-N two-port modulator

 Automatic Filter Alignment

- No manufacturing adjustments required.

 No external data slicer components required

 Control outputs correctly sequence and control PA

 3-wire control interface

 Analog RSSI output

The ML2726 contains internal voltage regulation. It
also contains PLL and transmitter configuration
registers. The device can be placed in a low power
standby mode for current sensitive applications. It is
packaged in a “Green” Pb-Free 32TQFP.

PIN CONFIGURATION

XCE
RXO
PAO

DAT

CL

AOU

RVDMD

DOUT

DIN

DD

31 30 29 28 27 26

32

1
2
3
4
5
6
7
8

9 10 11 12 13 14 15 16

FREF

RVPLL

QPO

GNDPL

RSSI

VREG

RVQMIF

RVVCO

GNDDMD

BG

25

24
23
22
21
20
19
18
17

GND

TUNE

VCCA
RVLO
TXOB
TXO
GNDRXMX2
GNDRXMX
GNDRF
RXI

ORDERING INFORMATION

PART # TEMP RANGE PACKAGE PACK (QTY)

ML2726DH -10oC to +60 oC 32TQFP 7x7x1mm Antistatic Tray (250)

ML2726DH-T -10oC to +60 oC 32TQFP 7x7x1mm Tape & Reel (2500)

APPLICATIONS

 2.4GHz FSK Data Transceivers

- Digital Cordless Telephones

- Wireless PC Peripherals

- Wireless Game Controllers

- Wireless Streaming Media

BLOCK DIAGRAM

RXI

2.4 GHz

Receive Input

TXO/TXOB

2.4 GHz
Output

Transmit

2

Mixer

Bandgap

Quadratu re

Downmixers

Filter

lignment

Divide

by 2

Quadrature

Divider

Modulator

1.6 GHz
VCO

PLL

Divider

VTUNE QPO

RSSI

Two-p ort

PLL Loop

Filter

P.D.

F
to
V

Test M ux

Mode

Control

Control

Registers

Ref.

Divider

OUT

DOUT

Receive Data

Out

RSSI

TPC
PAON
RXON
XCEN

DIN

Transmit Da ta In

DATA

Serial

CLK

Control Bus

EN

FREF
Frequency
Reference

Parallel

control lines

OCT 2007 EDS-105982 REV P01

ML2726

TABLE OF CONTENTS

GENERAL DESCRIPTION ........................................................................................................................................... 1

PIN CONFIGURATION................................................................................................................................................. 1

ORDERING INFORMATION ........................................................................................................................................ 1

FEATURES................................................................................................................................................................... 1

APPLICATIONS............................................................................................................................................................ 1

BLOCK DIAGRAM........................................................................................................................................................ 1

TABLE OF CONTENTS................................................................................................................................................ 2

SIMPLIFIED APPLICATIONS DIAGRAM..................................................................................................................... 3

ELECTRICAL CHARACTERISTICS............................................................................................................................. 4

PIN DESCRIPTIONS.................................................................................................................................................... 7

FUNCTIONAL DESCRIPTION ................................................................................................................................... 12

MODES OF OPERATION .......................................................................................................................................... 13

DATA INTERFACE..................................................................................................................................................... 15

CONTROL INTERFACES AND REGISTER DESCRIPTIONS .................................................................................. 17

DATA INTERFACES .................................................................................................................................................. 22

ADDITIONAL PERFORMANCE INFORMATION....................................................................................................... 24

PHYSICAL DIMENSIONS (INCHES/MILLIMETERS) ................................................................................................ 24

WARRANTY ............................................................................................................................................................... 25

PRELIMINARY DATASHEET OCT 2007 EDS-105982 REV P01

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ML2726

Ω

SIMPLIFIED APPLICATIONS DIAGRAM

ANTENNA

T/R

SWITCH

PA

LNA

PAON

RXI

TXOB

TXO

32

7

28

9

5

3

6
4

2
1

30

220nF

DOUT
AOUT

RSSI

FREF

CLK,

DATA

EN

XCEN,
RXON

2

DIN

VCCA

BASEBAND

IC

BATTERY

AND

PROTECTIO

CIRCUITS

DOUT

QPO

11

AOUT

RSSI

FREF

DATA

CLK

EN

RXON

XCEN

DIN

VBG

26

QPO

PAON

3

RXI

17

ML2726

22

21

TXOB

TXO

VTUNE

220

VTUNE

15

18nF

100nF

14

Figure 1: Typical ML2726 Application Diagram

(PLL Filter BW shown above: 22 KHz typical)

RVVCO

PRELIMINARY DATASHEET OCT 2007 EDS-105982 REV P01

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ML2726

ELECTRICAL CHARACTERISTICS

ABSOLUTE MAXIMUM RATINGS

Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute
maximum ratings are stress ratings only and functional device operation is not implied.

VCCA, VDD................................................................................................................................................................. 5.5V

Junction Temperature .............................................................................................................................................. 150°C

Storage Temperature Range...................................................................................................................... -65°C to 150°C

Lead Temperature (Soldering, 10s) ......................................................................................................................... 260°C

OPERATING CONDITIONS

Normal Temperature Range......................................................................................................................... -10°C to 60°C

VCCA Range...................................................................................................................................................2.7V to 4.5V

VDD Range .....................................................................................................................................................2.7V to 3.3V

Thermal Resistance (θ

JA)....................................................................................................................................... 70°C/W

Unless otherwise specified, VCCA=VDD=3.3V, T

=25°C, f

A

=12.288MHz, Data Rate=2.048Mbps, 22kHz Loop Filter

REF

as shown in Figure 1.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
POWER CONSUMPTION

VCCA Analog supply (VCCA) 2.7 3.3 4.5 V

VDD Digital Supply voltage

VBG Bandgap Voltage

I

Supply current, STANDBY mode DC supply connected, XCEN low 10 120

STBY

IRX Supply current, RECEIVE mode RX chain active, data being received 55 76 mA

ITX Supply current, TRANSMIT mode P

SYNTHESIZER

fC Carrier frequency range 2.4 2.485 GHz

δf

IP Charge Pump sink/source current +/-5.5 mA

ΦN

tFH Lock time for channel switch From EN asserted to RX valid

t

TX2RX

t

RX2TX

t

WAKE

Channel Spacing 3072 kHz

Phase noise at TXO

1.2MHz
3MHz

>7MHz

Lock time for TX/RX RXON High to Valid RX data 70 120

Lock time for RX/TX RXON Low to PAON high 63 75

Lock up time from standby XCEN high to Valid RX data, XCEN 240 325

VDD pin (VCCA ≥ VDD always)

VBG pin 26, IO=0μA

=3dBm 50 76 mA

OUT

Closed loop, loop filter bandwidth
13KHz

data(RX), or PAON high (TX)

1 Channel

5 Channels

Full Range

2.7 3.3 V

1.23 V

μA

-95

-115

-125

110

185

250

dBc/Hz

125

220

300

μs

μs

μs

μs

μs

μs

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ML2726

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

low period >120 seconds

f

Reference signal frequency RD0=0, RD1=0

FREF

V

Reference signal input level sine wave, AC coupled 2.0 VCCA VPP

FREF

RECEIVER

RD0=0, RD1=1

RD0=1, RD1=0

RD0=1, RD1=1

9.216

12.288

18.432

24.576

MHz

MHz

MHz

MHz

ZIN Receiver input impedance fc=2445MHz

Ω

NF Receiver noise figure fc=2445MHz 16.5 dB

DRRX Data Rate FSK modulation, f

S Input Sensitivity <12.5% CER at 2.048Mchip/s

<0.1% BER at 2.048Mbps

=+/-768kHz 2.048 Mbps

dev

-89

-80

dBm

dBm

BWRX Bandwidth 3dB Bandwidth 1155 kHz

P

Maximum RX RF input <12.5% CER at 2.048Mchip/s

IMAX

<0.1% BER at 2.048Mb/s

I

Receiver Input IP3 Test tones 2 and 4 channels away -15 dBm

IP3

+5

-4

dBm

dBm

LO leakage at RXI -60 dBm

IRR Mixer Image Rejection Ratio Measured at 3.5MHz offset 35 dB

Adjacent channel rejection -80dBm wanted signal <10-3 BER

Single 2GFSK modulated interferer
with a 2.0MHz –20dBc bandwidth

1 channel away
2 channels away
3 or more channels away

6

31

36

dB
dB
dB

IF FILTERS

f

IF filter center frequency After Automatic Filter Alignment 1.536 MHz

IFC

BWIF IF filter 3dB bandwidth After Automatic Filter Alignment 2108 kHz

LIMITER, AGC, AND FM DEMODULATOR

t

Recovery from overload From +15dBm at input 5 12

OVLD

μs

Eb/No For 0.1% BER 10.5 dB

Co-Channel rejection, 0.1% BER

V

Quiescent voltage @ AOUT 1.1 V

ODC

V

Output voltage swing AOUT 0.55 1.1 VPP

OPK

VOL AOUT open-drain voltage

-80 dBm, modulated with 2.048Mbps
GFSK, BT=0.5, PRBS data

IO=100μA, TPC Mode

10.5 dB

0.4 V

RSSI PERFORMANCE

t

RSSI rise time No Signal to

RRSSI

20pF load, 20% to 80% 4.5

μs

-15dBm into the IF mixer

t

RSSI fall time, < -15dBm to

FRSSI

20pF load, 20% to 80% 3.0

μs

No Signal into the IF mixer

G

RSSI sensitivity (V

RSMID

V

RSSI maximum voltage See Figure 3 1.8 2.3 V

RSMX

-40dBm

– V

)/20dB 28 36 42 mV/dB

-60dBm

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ML2726

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

V

RSSI midrange voltage -40dBm into RXI 1.4 1.7 2.0 V

RSMD

V

RSSI minimum voltage No signal into RXI 75 mV

RSMN

V

RSSI maximum voltage (clipped) -10dBm into RXI 1.6 1.95 V

RSMXC

TRANSMIT RF MIXER

P

Output power, single ended TRXO or TRXOB, fC=2.445GHz -3 1 5 dBm

OSE

P

Output power, differential P

ODIF

Z

Output impedance TRXO or TRXOB, fC=2.445GHz 12+j0

OUT

(TRXO,TRXOB)

TRANSMIT MODULATION

f

Modulation Deviation, @2.4GHz 200us of consecutive ‘1’s or ‘0’s 750 768 786 kHz

DEV

fOS

Modulation center frequency offset

50us after RXON low -75 +75 kHz

TRANSMIT DATA FILTER

BWTX Transmit Data Filter Bandwidth 3dB Bandwidth 2.1 MHz

TX spurious

-25

Image

, fC=2.445GHz -1 3 6 dBm

Ω

dBc

-20

dBc

INTERFACE LOGIC LEVELS

INPUTS (DIN, XCEN, RXON, DATA, CLK, EN)

VIH Input high voltage (never exceed VDD)

0.75*VDD

VIL Input low voltage 0

IB Input bias current -5 0 5

VDD V

0.25*VDD

V

μA

CIN Input capacitance (measured at 1MHz) 4 pF

OUTPUTS (DOUT, PAON)

VOH DOUT high voltage Io=0.1mA VDD-0.4 V

VOL DOUT low voltage Io=-0.1mA 0.4 V

Io DOUT sink/source current 0.1 mA

VOH PAON output high voltage Sourcing 0.5mA VDD-0.4 V

VOL PAON output low voltage Sinking 0.5mA 0.4 V

Io PAON source/sink current 0.5 mA

3 WIRE SERIAL BUS TIMING

tr CLK input rise time 15 ns

See Figure 4

tf CLK input fall time 15 ns

tck CLK period 50 ns

tew CLK pulse width 100 ns

tl Delay from last CLK falling edge 15 ns

tse EN setup time to ignore next

15 ns

rising CLK

ts DATA-to-CLK setup time 15 ns

th DATA-to-CLK hold time

15 ns

PRELIMINARY DATASHEET OCT 2007 EDS-105982 REV P01

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ML2726

PIN DESCRIPTIONS

PIN

SIGNAL

I/O FUNCTION DIAGRAM

NAME

POWER & GROUND

8 VSS GND Digital Ground. Ground for digital I/O

circuits and control logic.

10 RVPLL PWR PLL Supply. DC power supply

decoupling point for the PLL dividers,
phase detector, and charge pump. This
pin is connected to the output of the
regulator and to the PLL supplies. There
must be a 220nF capacitor to ground
from this pin to decouple (bypass) noise
and to stabilize the regulator.

12 GNDPLL GND Ground for the PLL dividers, phase

detector, and charge pump.

13 VVREG PWR DC Power Supply Input to the VCO

voltage regulator. Must be connected to
RVQMIF (pin 27) or RVDMD (pin 29) via
decoupling network.

14 RVVCO PWR DC power supply decoupling point for the

VCO. Connected to the output of the
VCO regulator. A 220nF capacitor must
be tied between this pin and ground to
decouple (bypass) noise and to stabilize
the regulator.

16 GND GND DC ground for VCO and LO circuits.

18 GNDRF GND Ground return for the Receive RF input

and Transmit RF output.

N/A

See Pin 11 below.

N/A

N/A

N/A

N/A

VCCA

24

0.7V

VSS

VCCA

(PIN 8)

(PIN 24)

4k

19 GNDRXMX GND Signal ground for the Receive mixers.

20 GNDRXMX2 GND Signal ground for the Receive mixers.

N/A
N/A

RXI

GNDRF

18

17

8

VSS

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ML2726

PIN

SIGNAL

I/O FUNCTION DIAGRAM

NAME

23 RVLO PWR DC power supply decoupling point for the

LO Chain. Connected to the output of a
regulator. A 220nF capacitor must be tied
between this pin and ground to decouple
(bypass) noise and to stabilize the
regulator.

24 VCCA PWR DC power supply Input to Voltage

Regulators and unregulated loads: 2.7 to

3.8V. VCCA is the main (or master)
analog VCC pin. There must be
capacitors to ground from this pin to
decouple (bypass) supply noise.

25 GNDDMD GND DC ground to IF, Demodulator, and Data

Slicer circuits.

27 RVQMIF PWR DC power supply decoupling point for

Quadrature Mixer and IF filter circuits. A
220nF capacitor must be tied between
this pin and ground to decouple (bypass)
noise and to stabilize the regulator.

29 RVDMD PWR DC power supply decoupling point for IF,

Demodulator, and Data Slicer circuits. A
220nF capacitor must be tied between
this pin and ground to decouple (bypass)
noise and to stabilize the regulator.

31 VDD PWR DC power supply input to the interface

logic and control registers. This supply is
not connected internally to any other
supply pin, but its voltage must be less
than or equal to the VCCA supply and
greater than 2.7V. A capacitor must be
tied between this pin and ground to
decouple (bypass) noise.

N/A

N/A

N/A

N/A

N/A

N/A

TRANSMIT/RECEIVE

17 RXI I (Analog) Receive RF Input. Nominal impedance at

2445MHz is 2.6-j2.6 with a simple
matching network required for optimum

VCCA

24

0.7V

noise figure. This input connects to the
base of an NPN transistor and should be
AC coupled.

RXI

GNDRF

17

18

8

VSS

VSS

VCCA

4k

(PIN 8)

(PIN 24)

PRELIMINARY DATASHEET OCT 2007 EDS-105982 REV P01

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ML2726

TXOB

TXO

A

A

21 TXO O (Analog) TX RF open-collector output. This output

requires a DC path to VCCA.

22 TXOB O (Analog) Complementary TX RF open-collector

output. This output requires a DC path to
VCCA. For single-ended output
applications, this pin should be
connected to a dummy load that includes
a DC path to VCCA.

DATA

21 22

18

GNDRF

7 AOUT A (Analog) Multi-function Output. In Analog output

mode this is output drives an off chip
data slicer. In Transmit power control
mode this is an open drain output, which
is pulled low when the TPC bit is serial
register #1, is clear. Transitions on TPC
are synchronized to the falling edge of
RXON. In analog test modes this pin and
the RSSI output become test access
points controlled by the serial control
bus.

30 DIN I (CMOS) Transmit Data Input. Drives the transmit

pulse shaping circuits. Serial digital data
on this pin becomes FSK modulation on
the Transmit RF output. The logic timing
on this pin controls data timing. Internal
circuits determine the modulation
deviation. This is a standard CMOS input
referenced to VDD and VSS.

32 DOUT O (CMOS) Serial digital output after demodulation,

chip rate filtering and center data slicing.
A CMOS level output (VSS to VDD) with
controlled slew rates. A low drive output
designed to drive a PCB trace and a
CMOS logic input while generating
minimal RFI. In digital test modes this pin
becomes a test access port controlled by
the serial control bus.

TPQ

MUX

TPC

8

VSS

See Pin 1 below.

MUX

MUX

TPC

OUT

250

VDD

31

OUT

100

Ω

7

8

VSS

VDD

31

Ω

32

DOUT

VSS

8

PRELIMINARY DATASHEET OCT 2007 EDS-105982 REV P01

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ML2726

VDD

MODE CONTROL AND INTERFACE LINES

1 XCEN I (CMOS) Enables the bandgap reference and

voltage regulators when high. Consumes
only leakage current in STANDBY mode
when low. This is a CMOS input, and the
thresholds are referenced to VDD and
VSS.

2 RXON I (CMOS) TX/RX Control Input. Switches the

transceiver between TRANSMIT and
RECEIVE modes. Circuits are powered
up and signal paths reconfigured
according to the operating mode. This is
a CMOS input, and the thresholds are
referenced to VDD and VSS.

3 PAON O (CMOS) PA Control Output. Enables the off-chip

PA at the correct times in a Transmit slot.
Goes high when transmit RF is present
at TXO; goes low 5μs before transmit RF
is removed from TXO. Has interlock logic
to shut down the PA if the PLL does not
lock.

XCEN

RXON

DIN

31

1

2

30

8

VSS

VDD

31

3

PAON

9 FREF I Input for the 9.216MHz, 12.288MHz,

18.432MHz or 25.576MHz reference
frequency. This input is used as the
reference frequency for the PLL and as a
calibration frequency for the on-chip
filters. An AC-coupled sine or square
wave source drives this self-biased input.

11 QPO O Charge Pump Output of the phase

detector. This is connected to the
external PLL loop filter.

9

FREF

RVP LL

10

VSS

VCCA

24

8

VSS

8

40k

40k

11 QPO

8

VSS

PRELIMINARY DATASHEET OCT 2007 EDS-105982 REV P01

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ML2726

VCCA

15 VTUNE I VCO Tuning Voltage input from the PLL

loop filter. This pin is very sensitive to
noise coupling and leakage currents.

26 VBG O Bandgap Decouple Voltage. Decoupled

to ground with a 220nF capacitor.

28 RSSI O Buffered Analog RSSI output with a

nominal sensitivity of 35mV/dB. In analog
test modes, this pin and the AOUT output
become test access points controlled by
the serial control bus.

N/A

VTUNE

15

TPI

MUX

24

8

VSS

1.25V

3.7k

VCCA

24

SERIAL BUS SIGNALS

4 EN I (CMOS) Control Bus Enable. Enable pin for the

three-wire serial control bus that sets the
operating frequency and programmable
options. The control registers are loaded
on a low-to-high transition of the signal.
Serial control bus data is ignored when
this signal is high. This is a CMOS input,
and the thresholds are referenced to
VDD and VSS.

5 DATA I (CMOS) Serial Control Bus Data. 16-bit words,

which include programming data and the
two-bit address of a control, register. This
is a CMOS input, and the thresholds are
referenced to VDD and VSS.

6 CLK I (CMOS) Serial control bus data is clocked in on

the rising edge when EN is low. This is a
CMOS input; the thresholds are
referenced to VDD and VSS.

RSSI

RSSI

OP
AMP

4EN

5DATA

6CLK

MUX

VDD

31

VSS

100 Ω

8

VSS

5.5k

1.7p

8

RSSI

28

PRELIMINARY DATASHEET OCT 2007 EDS-105982 REV P01

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ML2726

FUNCTIONAL DESCRIPTION

The ML2726 is a fully integrated 2.0Mbps frequency shift keyed (FSK) transceiver that operates in the unlicensed

2.4GHz ISM frequency band. The device has been optimized for digital cordless telephone applications and includes all
the frequency generation, receive and transmit functions for a raw data rate of 2.0Mbps. This high data rate allows for
data spreading, such as Direct Sequence Spread Spectrum (DSSS) modulation, which improves range. The ML2726
receiver architecture is a dual conversion Low IF, which has all of the sensitivity and selectivity advantages of a
traditional super-heterodyne receiver without requiring costly, bulky external filters.

The RF mixer down-converts the 2.4GHz RF input signal to the first intermediate frequency (IF), where it is filtered to
remove adjacent channel signals. An active image reject mixer converts this signal down to a Low IF frequency, where
the data is limited, filtered, and demodulated. This architecture provides all the benefits of direct conversion to
baseband while maintaining the stability and robustness of a traditional super-heterodyne.

A single synthesizer is used for both the receiver and the FSK transmitter. The phase locked loop (PLL) is completely
integrated, including the voltage controlled oscillator (VCO), tuning circuits, and VCO resonator.

RECEIVE MODE, the ML2726 is a dual conversion Low IF receiver. No external SAW filters are required. The

In
integrated image reject mixer gives sufficient rejection in this channel. All channel filtering and demodulation is
performed using active filters, which are automatically aligned. A matched bit rate filter and a data slicer follow the
demodulator. The sliced data is provided at the DOUT pin, and the analog data is available at AOUT.

TRANSMIT MODE, the ML2726 generates a 2.4GHz output using the transmit mixer. An auto-aligned transmit data

In
filter and modulation compensation circuit results in an adjustment-free transmitter. The VCO is modulated by the
transmit data, which is put through a sigma-delta fractional-N PLL ensuring modulation accuracy. This modulation
occurs while the phase locked loop is closed, thus allowing practically infinite transmit or receive times with excellent
frequency accuracy and stability. A 3dBm FSK-modulated differential signal is output at the TXO/TXOB pins at the

2.4GHz carrier frequency.

The integrated PLL frequency synthesizer includes a fully integrated VCO, prescaler, phase detector and charge pump.
The reference frequency is generated from the incoming signal at the FREF pin, which can be 9.216MHz, 12.288MHz,

18.432MHz, or 24.576MHz. The loop filter is external to allow customers to optimize their loop bandwidth to their
system’s lock time and in-band phase noise requirements. This frequency-agile synthesizer allows the ML2726 to be
used in frequency hopped spread spectrum (FHSS) applications with nominal channel spacing of 3.072MHz. Carrier
frequency is programmed via the configuration registers and 3-wire serial interface. The VCO tank circuit (inductor and
varactor) is fully integrated.

RSSI

Two-port

Modulator

P.D.

F
to
V

Test Mux

Mode

Control

Control

Registers

Ref.

Divider

RXI

2.4 GHz

Receive Input

Transmit

2

Mixer

TXO/TXOB

2.4 GHz
Output

Bandgap

Quadrature

Downmixers

Divide

by 2

Quadrature

Divider

1.6 GHz

Filter

Alignment

VCO

PLL

Divider

AOUT

DOUT

Receive Data

Out

RSSI

TPC

PAON

control lines

RXON
XCEN

DIN

Transmit Data In

DATA

Serial

CLK

Control Bus

EN

FREF

Frequency

Reference

Parallel

VTUNE QPO

PLL Loop

Filter

PRELIMINARY DATASHEET OCT 2007 EDS-105982 REV P01

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ML2726

Figure 2: ML2726 Internal Block Diagram

MODES OF OPERATION

There are three key modes of operation:

 STANDBY: All circuits powered down, except the control interface (Static CMOS)
 RECEIVE: Receiver circuits active
 TRANSMIT: Modulated RF output from IC

The two operational modes are RECEIVE and TRANSMIT, controlled by RXON. XCEN is the chip enable/disable
control pin, which sets the part in operational or STANDBY modes. The relationship between the parallel control lines
and the mode of operation of the IC is given in

XCEN RXON MODE FUNCTION

0 X STANDBY Control interfaces active, all other circuits powered down

1 1 RECEIVE Receiver time slot

1 0 TRANSMIT Transmit time slot

MODE CONTROL

Table 1.

Table 1: Modes of Operation

The ML2726 is intended for use in TDD and TDMA radios in battery-powered equipment. To minimize power
consumption it is designed to switch rapidly from a low power mode (STANDBY) to an active mode. The ML2726 can
also make a quick transition from receive to transmit for TDD operation. Prior to transmitting or receiving, time should
be allowed for the PLL to lock and for the filters to align. When the ML2726 is operated in single-carrier TDD mode, the
LO is automatically shifted by the second (low) IF frequency when the device is switched between RECEIVE and
TRANSMIT modes.

ML2726 carrier frequency can be changed (hopped) at any time, but is usually changed between transmissions. Carrier
frequency (channel) is modified in the ML2726 by writing a corresponding new value to the PLL frequency register
(Register 1)

RECEIVE

The ML2726 uses a double-conversion super-heterodyne receiver with a nominal second IF of 1.536MHz. The signal
flow in RECEIVE mode is from the RF input, through an RF down-conversion mixer and integrated IF filter, image reject
quadrature mixer, integrated Low IF filter, hard limiter, frequency to voltage converter, and data filter to the AOUT pin
and data slicer where the digital NRZ data is available at the DOUT pin. A 20dB step AGC extends the dynamic range
of the receiver. The ML2726 receive chain is a Low IF receiver using advanced integrated radio techniques to eliminate
external IF filters and minimize external RF filter requirements. The precision filtering and demodulation circuits give
improved performance over conventional radio designs using external filters while providing integration comparable to
advanced direct conversion radio designs.

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ML2726

Receive Signal Strength Indication (RSSI)

RSSI is an indication of field strength. It can be used to control transmit power to conserve battery life or it may be used
to determine if a given channel is occupied. See Figure 3.

Figure 3: RSSI Voltage vs. Input Signal Level

Automatic Filter Alignment

When the ML2726 is placed in RECEIVE mode, it automatically tunes all the internal filters using the reference
frequency from the FREF pin. When the chip is powered up (VDD first applied), the tuning information is reset to mid­range. This self-calibration sets:

 Discriminator center frequency

 IF filter center frequency and bandwidth

 Receiver data low-pass filter bandwidth

 Transmit data low-pass filter bandwidth

TRANSMIT MODE

In TRANSMIT mode, the PLL is closed to eliminate frequency drift. A two-port modulator modulates both the VCO and
the fractional-N PLL. The VCO is directly modulated with filtered FSK transmit data. The PLL is driven by a sigma-delta
modulator, which ensures that the PLL follows the mean frequency of the modulated VCO.

The transmit modulation filter is automatically tuned during every RECEIVE time, alleviating the need for production
alignment. Asserting RXON enables the ML2726. The rising edge of XCEN triggers a complete calibration of all the on­chip filters, which takes up to 256
emissions.

μs, which ensures the modulation filters are aligned to prevent unwanted spurious

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ML2726

PLL PROGRAMMING & CHANNEL SELECTION

The ML2726 PLL is programmed via control register 2 to the set RF center frequency of operation of the radio. The PLL
does not need to be (though it can be) reprogrammed between RECEIVE and TRANSMIT modes. Nominal channel
separation is 3.076MHz, allowing for over 40 non-overlapping channels in any given location. With careful planning,
channels can be programmed in 1536kHz steps as long as care is exercised to insure that two radio links will not share
spectrum at any one time. The equation to determine channel center frequency from the ML2726 control register word
is:

fC = CHQ<0:11>*1.536MHz

STANDBY MODE

In STANDBY mode, the ML2726 transceiver is powered down. The only circuits active are the control interfaces, which
are digital CMOS to minimize power consumption. The serial control interface and control registers remain powered up
and will accept and retain programming data as long as the digital supply is present. When exiting STANDBY mode, the
device must be kept in RECEIVE mode for 256

TEST MODE

The RF to digital functionality of the ML2726 requires special test mode circuitry for IC production test and radio
debugging. A test register, accessible via the 3-wire serial interface, controls the test multiplexers. (See

μs to allow for filter self-calibration.

Table ).

DATA INTERFACE

There are two control interfaces: CONTROL and SERIAL.

CONTROL INTERFACE

The control interface provides immediate control and monitoring of the ML2726. Input signals include:

 XCEN: Transceiver enable. Places the ML2726 in Standby or Active (when asserted) modes.
 RXON: Receive On. Places an Active ML2726 in Receive mode when asserted.
 FREF: Reference frequency input

Output signals include:

 RSSI: Received Signal Strength Indicator: indicates the power of the received signal
 PAON: External Power Amplifier Control Pin

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ML2726

SERIAL INTERFACE

A 3-wire serial interface (EN, DATA, CLK) is used for programming the ML2726 configuration registers, which control
device mode, pin functions, PLL and reference dividers, internal test modes, and filter alignment. Data words are
entered beginning with the MSB (“big-endian”). The word is divided into a leading 14-bit data field followed by a 2-bit
address field. When the address field has been decoded the destination register is loaded on the rising edge of EN.

Providing less than 16 bits of data will result in unpredictable behavior when EN goes high.

Data and clock signals are ignored when EN is high. When EN is low, data on the DATA pin is clocked into a shift
register on the rising edge of the CLK pin. This information is loaded into the target control register when EN goes high.
This serial interface bus is similar to that commonly found on PLL devices. It can be efficiently programmed by either
byte or 16-bit word oriented serial bus hardware. The data latches are implemented in CMOS and use minimal power
when the bus is inactive. Refer to Figure 4 and Table 2: 3-Wire Bus Timing Characteristics for timing and register
programming illustrations.

SYMBOL PARAMETER MIN TYP MAX UNIT

BUS CLOCK (CLK)

tr CLK input rise time 15 ns

tf CLK input fall time 15 ns

tck CLK period 50 ns

ENABLE (EN)

tew Minimum pulse width 100 ns

tl Delay from last CLK rising edge 15 ns

tse Set up time to ignore next rising CLK 15 ns

BUS DATA (DATA)

ts data to clock set up time 15 Ns

th data to clock hold time 15 Ns

Table 2: 3-Wire Bus Timing Characteristics

t

t

R

DATA

F

LSB

t

L

t

EW

t

CK

ADDRESS

t

CLK

DATA

EN

S

MSB

t

H

Figure 4: Serial Bus Timing for Address and Data Programming

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ML2726

CONTROL INTERFACES AND REGISTER DESCRIPTIONS

REGISTER INFORMATION

A 3-wire serial data input bus sets the ML2726’s transceiver parameters and programs the PLL circuits. Entering 16-bit
words into the ML2726 serial interface performs programming. Three 16-bit registers are partitioned such that 14 bits
are dedicated for data to program the operation and two bits identify the register address. The contents of these
registers cannot be read back via this bus.

The three registers are:

 Register 0: PLL Configuration
 Register 1: Channel Frequency Data
 Register 2: Internal Test Access

Figure 5 shows a register map. Table 3 through Table 5 provide detailed diagrams of the register organization: Table 3
and Table 4 outline the PLL configuration and channel frequency registers, and Table 5 displays the filter tuning and
test mode register.

MSB

B12

DB9

DB8

B11

DB7B9DB6B8DB5B7DB4B6DB3B5DB2B4DB1

B10

B3

DB0

ADR1B1ADR0

B2

B0

DB13

Res.

DB12

B15

DB11

Res. Res. Res. RCLP LVLO Res. TXM TPC TXCW RD1 AOUT RD0 QPP 0 0

B14

DB10

B13

MSB

DB13

Res.

MSB

DB13

Res.

B12

B12

DB9

DB9

DB8

DB7B9DB6B8DB5B7DB4B6DB3B5DB2B4DB1

B11

B11

B10

DB8

DB7B9DB6B8DB5B7DB4B6DB3B5DB2B4DB1

B10

B3

B3

DB0

B2

DB0

B2

DB12

B15

DB12

B15

DB11

DB11

DB10

B13

DB10

B13

Res. CHQ11 CHQ10 CHQ9 CHQ8 CHQ7 CHQ6 CHQ5 CHQ4 CHQ3 CHQ2 CHQ1 CHQ0 0 1

B14

Res. Res. Res. Res. Res. Res. Res. DTM2 DTM1 DTM0 ATM2 ATM1 ATM0 1 0

B14

Figure 5: Configuration Register Map

ADR1B1ADR0

B0

ADR1B1ADR0

B0

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ML2726

NAME DESCRIPTION DEFINITION

Reserved Reserved

Reserved Reserved

Reserved Reserved

Reserved Reserved

RCLP RSSI Clip Disable 0: RSSI clipped to 1.9V at –15dBm

1: RSSI not clipped

LVLO Low Voltage Lockout 0: PAON Undisturbed

1: PAON De-asserted for VCCA<2.65V. Reset on RXON high

Reserved Reserved Set to 0

TXM TX RF Output Mode 0: TX RF Output always on in TX mode

1: TX RF Output follows PAON signal

TPC Transmit Power Control 0: AOUT pin pulled to ground

1: AOUT pin high impedance

TXCW Transmit Test Mode 0: FSK modulation in Transmit mode

1: CW (no modulation in Transmit mode)

RD1 Reserved (See Table 7)

AOUT Analog Output 0: AOUT pin is Transmit Power Control

1: AOUT pin is Analog Data Out

RD0 Reference Frequency Select (See Table 7)

QPP PLL Charge Pump Polarity 0: For fc < fref, charge pump sources current

1: For fc < fref, charge pump sinks current

ADR1 MSB Address Bit ADR1=0

ADR0 LSB Address Bit ADR0=0

Set all bits to 0 (zero)

Table 3: Register 0 -- PLL Configuration Register

NAME DESCRIPTION DEFINITION

Reserved

Reserved

CHQ11

CHQ10

CHQ9

CHQ8

CHQ7

CHQ6

CHQ5

CHQ4

CHQ3

CHQ2

CHQ1

CHQ0

ADR1 MSB Address Bit ADR1=0

ADR0 LSB Address Bit ADR0=1

Channel Frequency select bits

Set all bits to 0 (zero)

Divide ratio=f

/1.536

c

Table 4: Register 1 – Channel Frequency Register

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ML2726

NAME DESCRIPTION DEFINITION

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

DTM2

DTM1

DTM0

ATM2

ATM 1

ATM 0

ADR1 MSB Address Bit ADR1=0

ADR0 LSB Address Bit ADR0=1

Reserved Set all bits to 0 (zero)

Digital Test Control Bits See Table

Analog Test Control Bits See Table

Table 5: Register 2 – Test Mode Register

Power-On State

On Power up, all register bits are cleared to the default value of 0 (zero). Power up is defined as occurring when

>2.0V. The register default values are valid upon power up.

VDD

CONTROL REGISTER BIT DESCRIPTIONS

ADR<1:0>, All Registers, Bits 0-1

Address Bits: The ADR<1:0> bits are the least-significant bits of each register. Each register is divided into a data

field and an address field. The data field is the leading field, while the last two bits clocked into the register are always
the address field. When EN goes high, the address field is decoded and the addressed destination register is loaded.
The last 16 bits clocked into the serial bus are loaded into the register. Clocking in less than 16 bits results in a
potentially incorrect entry into the register.

RES (Reserved), All Registers

Reserved Bits: These bits are reserved. These bits must be cleared to 0s (zeros) for normal operation. When power is

reset, all of the registers’ data fields are cleared to 0s (zeros).

QPP - Register 0, Bit 2

Charge Pump Polarity: This bit sets the charge pump polarity to sink or source current. For a majority of applications,

this bit is cleared (QPP=0). For applications where an external inverting amplifier is used in the loop filter, this bit is set
to change the charge pump polarity (see Table 6).

QPP PLL CHARGE PUMP POLARITY

0 fc > f

1 fc > f

Table 6: PLL Charge Pump Polarity

ͯ Charge pump sinks current.

ref

ͯ Charge pump sources current.

ref

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ML2726

RD0 - Register 0, Bit 3 RD1 - Register 0, Bit 5

Reference Divide: These 2 bits set the reference divider from the FREF pin to the reference input of the PLL

phase/frequency detector (see Table 7).

RD0 RD1 REFERENCE

DIVISION

0 0 9 9.216MHz 1.024MHz 1.536MHz

0 1 12 12.288MHz 1.024MHz 1.536MHz

1 0 18 18.432MHz 1.024MHz 1.536MHz

1 1 24 24.576MHz 1.024MHz 1.536MHz

FREF XTAL

FREQ

PLL REF

FREQ

CHANNEL

SPACING

Table 7: Reference Frequency Select

AOUT - Register 0, Bit 4

Analog Output Mode: This bit changes the function of the AOUT pin between an analog data output to transmit power

control (see Table 8).

AOUT AOUT PIN FUNCTION

0 Transmit Power Control

1 Data Filter Analog Output

Table 8: AOUT Function Select

TXCW - Register 0, Bit 6

Transmit Continuous Wave: This bit produces a continuous wave (CW) transmitter output for product test when

RXON is low (see Table 99).

TXCW TRANSMIT MODULATION

0 FSK Modulation

1 CW – No Modulation

Table 9: Transmit Modulation Mode

TPC - Register 0, Bit 7

Transmit Power Control: When the AOUT bit is low, this bit controls the state of the open-drain output pin. Although

this bit can be changed at any time, the AOUT pin only changes state at the falling edge of RXON (see Table 10).

TPC TPC PIN STATE

0 High Impedance

1 Pulled to Ground

Table 10: TPC Pin State

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ML2726

TXM - Register 0, Bit 8

Transmit Mode: This bit controls the TX RF buffer state timing mode. It must be reset to 0 for normal operation (see

Table 1).

TXM TXRF BUFFER BEHAVIOR

0 RF Output Always On in TX Mode

1 RF Output Follows PAON

Table 11: TXM Mode

LVLO - Register 0, Bit 10

Low Voltage Lock Out: The LVLO bit enables a transmit low voltage lockout latch, which shuts off the transmitter by

de-asserting the PAON output. This latch is set if the supply voltage drops below 2.65V and is reset when the RXON
control input goes high (see Table 2).

LVLO PAON BEHAVIOR

0 PAON Undisturbed

1 PAON de-asserted when VCCA<2.65V,

Reset by RXON high.

Table 12: LVLO Operation

RCLP - Register 0, Bit 11

RSSI Clip Enable: The RCLP bit disables the RSSI clipping circuitry. With RCLP low, the RSSI output voltage is

clipped to a maximum of about 2.0V at –10dBm. With RCLP high, the RSSI is not clipped. (see Table 3).

RCLP RSSI BEHAVIOR

0 RSSI output clipped to a maximum of ~1.9V at –15dBm

1 RSSI output not clipped

Table 13: RCLP Operation

CHQ <11:0> - Register 1, Bits 2-13

Channel Frequency Selection: These bits set the RF carrier frequency for the transceiver (see Table 4). The channel

frequency value is calculated by multiplying the CHQ value by 1.536. The recommended operating range value of the
CHQ is from 1,589 to 1,616. These bits must be programmed to a valid channel frequency before XCEN is asserted.

B15 B14 B13 TO B2 B1 B0

0 0 CHQ - PLL Divide Ratio 0 1

Table 14: Main Divider

The divide ratio is calculated as f

/1.536 where f

C

is the channel frequency in MHz.

C

f

=1.536 * CHQ

C

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ML2726

ATM<2:0> - Register 2, Bits 2-4

Analog Test Mode: The test mode selected is described in Table 5. The performance of the ML2726 is not specified in

these test modes. Although primarily intended for IC test and debug, they also can help in debugging the radio system.
The default (power-up) state of these bits is ATM<2:0>=<0,0,0>. When a non-zero value is written to the field, the RSSI
and AOUT pins become analog test access ports, giving access to the outputs of key signal processing stages in the
transceiver. During normal operation, ATM<2:0> must be set to all zeros.

ATM2 ATM1 ATM0 RSSI AOUT

0 0 0 RSSI Set by AOUT bit

0 0 1 No Connect No Connect

0 1 0 I IF Filter Output Q IF Filter Output

0 1 1 Q IF Filter – ve Output Q IF Filter + ve Output

1 0 0 I IF Filter – ve Output I IF Filter + ve Output

1 0 1 Data Filter + ve Output Data Filter – ve Output

1 1 0 I IF Limiter Outputs Q IF Limiter Outputs

1 1 1 1.67V Voltage Reference VCO Modulation Port Input

Table 15: Analog Test Control Bits

DTM <2:0> - Register 2, Bits 5-7

Digital Test Mode: The DTM<2:0> bit functions are described in Table 6. The performance of the ML2726 is not

specified in these test modes. Although primarily intended for IC test and debug, they also can help in debugging the
radio system. The default (power up) state of these bits is DTM<2:0>=<0,0,0>. When a non-zero value is written to
these fields, the DOUT and PAON pins become a digital test access port for key digital signals in the transceiver.
During normal operation, DTM<2:0> must be set to all zeros.

DTM2 DTM1 DTM0 PAON DOUT

0 0 0 PA Control Data Out

0 0 1 PA Control AGC Switch State

0 1 0 PA Control PLL Main Divider Output

0 1 1 PA Control PLL Reference Divider Output

1 0 0 S – D Modulation LSB Sigma – Delta Modulation MSB

Table 16: Digital Test Control Bits

DATA INTERFACES

BASEBAND INTERFACE: DIN & DOUT

The DIN and DOUT pins are digital CMOS signals that correspond to FSK modulation of the carrier frequency. The
ML2726 is designed to operate as an FSK transceiver in the 2.4GHz ISM band. The frequency deviation and transmit
filtering is determined in the transceiver.

Data on the DIN pin is filtered and presented to the transmit two-port modulator. There is no re-timing of the bits, so the
transmitted FSK data takes its timing from the input data. In the receive chain, FSK demodulation, data filtering, and
data slicing take place in the ML2726, and the digital data is output on the DOUT pin. Bit and word rate timing recovery
are performed off chip. The data filter output is available on the AOUT pin for use with an optional external data slicer.

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ML2726

RSSI & FREF

FREF (pin 9) is the master reference frequency for the transceiver. It supplies the frequency reference for the RF
channel frequency and the filter tuning. The FREF pin is a CMOS input with internal biasing resistors. It can be AC
coupled to sine or square wave source. The FREF input can also be driven by a CMOS logic output. The frequency of
the FREF input is limited to one of: 9.216MHz, 12,288MHz, 18,432MHz, or 24.576MHz.

The Received Signal Strength Indicator (RSSI) pin supplies a voltage proportional to the logarithm of the received
power level. It is normally connected to the input of a low speed ADC and is used during channel scanning to detect
clear channels on which the radio may transmit. It can also be used to set transmit power to optimize power
consumption while maintaining an acceptable bit error rate (BER).

PA CONTROL OUTPUTS (PAON & AOUT)

The PAON (PA control) is a CMOS output that controls an optional off-chip RF PA. It outputs a logic high when the PA
should be enabled and a logic low at all other times. This output is inhibited when the PLL fails to lock.

AOUT (pin 7) normally supplies the analog (not data-sliced) data output, but it can also be configured as an open-drain
output for transmit power control. This mode is controlled by the TPC bit in Register 0. This bit can be changed at any
time, but the AOUT pin will not change mode until the beginning of the next transmit slot, triggered by a falling edge on

(see Figure 6 and Table 17 for details).

RXON

In analog test modes the RSSI and AOUT pins become analog test access ports that allow the user to observe internal
signals in the ML2726.

RXON

PAON

Output from

TRFO

SYMBOL PARAMETER

T1 RXON falling edge to PAON rising edge 62.5

t4

t1

Figure 6: Power Amplifier Interface Table 17: Power Amplifier Timing

t2

t3

T2 RXON rising edge to PLL frequency

shift

T3 RXON rising edge to RECEIVE mode 70

T4 RXON rising edge to PAON falling edge < 0.1

TIME/μS

6.5

RF INTERFACE: RXI & TXO/TXOB

The RXI receive input (pin 17) and the TXO/TXOB differential transmit outputs (pins 21 and 22) are the only RF I/O
pins. The RXI pin requires a simple impedance matching network for optimum input noise figure. The TXO/TXOB pins
require a matching network for maximum power output into the RF power amp. If a single ended output is preferred, the
signal from the TXO pin can be matched to the power amp and the TXOB output can be shunted to a power supply
through a dummy load. The RF input and output ground (pin 18) must have a direct connection to the RF ground plane,
and the RF power supply pins must be decoupled to the same ground plane as close to the device as possible.

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ML2726

8

5

2

8

5

2

ADDITIONAL PERFORMANCE INFORMATION

1. 800

1. 600

1. 400

1. 200

1. 000

0. 800

0. 600

0. 400

0. 200

0. 000

Figure 7: Typical VCO Tuning Voltage vs. Frequency

1570 1577 1584 1591 1597 1604 1611 161

162

163

163

164

165

16591666 1673 16791686 1693 1700

PHYSICAL DIMENSIONS (INCHES/MILLIMETERS)

PIN 1 ID

25

0.012 - 0.018
(0.29 - 0.45)

0.276 BSC
(7.00 BSC)

17

0.354 BSC
(9.00 BSC)

0.048 MAX

(1.20 MAX)

0.037 - 0.041
(0.95 - 1.05)

0.354 BSC
(9.00 BSC)

0.276 BSC
(7.00 BSC)

1

9

0.032 BSC
(0.8 BSC)

0º - 8º

0.003 - 0.008
(0.09 - 0.20)

0.018 - 0.030
(0.45 - 0.75)

SEATING PLANE

Note: This package meets “Green” Pb-Free requirements and is compliant with the European Union directives WEEE
(Waste Electrical and Electronic Equipment) and RoHS (Restriction of the use of certain Hazardous Substances in
electrical and electronic equipment). The package pins are finished with 100% matte tin.

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ML2726

WARRANTY

Sirenza Microdevices makes no representations or warranties with respect to the accuracy, utility, or completeness of
the contents of this publication and reserves the right to make changes to specifications and product descriptions at any
time without notice. No license, express or implied, by estoppel or otherwise, to any patents or other intellectual
property rights is granted by this document. The circuits contained in this document are offered as possible applications
only. Particular uses or applications may invalidate some of the specifications and/or product descriptions contained
herein. The customer is urged to perform its own engineering review before deciding on a particular application. Sirenza
Microdevices assumes no liability whatsoever, and disclaims any express or implied warranty, relating to sale and/or
use of Sirenza Microdevices products including liability or warranties relating to merchantability, fitness for a particular
purpose, or infringement of any intellectual property right. Sirenza Microdevices products are not designed for use in
medical, life saving, or life sustaining applications.

If this document is “Advanced”, its contents describe a Sirenza Microdevices product that is currently under
development. All detailed specifications including pinouts and electrical specifications may be changed without notice. If
this document is “Preliminary”, its contents are based on early silicon measurements. Typical data is representative of
the product but is subject to change without notice. Pin out and mechanical dimensions are final. Preliminary
documents supersede all Advanced documents and all previous Preliminary versions. If this document is “Final”, its
contents are based on a characterized product, and it is believed to be accurate at the time of publication. This
document is Preliminary.

© 2007 Sirenza Microdevices Corporation. All rights reserved. All other trademarks are the property of their respective
owners. Products described herein may be covered by one or more of the following U.S. patents: 4,897,611; 4,964,026;
5,027,116; 5,281,862; 5,283,483; 5,418,502; 5,508,570; 5,510,727; 5,523,940; 5,546,017; 5,559,470; 5,565,761;
5,592,128; 5,594,376; 5,652,479; 5,661,427; 5,663,874; 5,672,959; 5,689,167; 5,714,897; 5,717,798; 5,742,151;
5,747,977; 5,754,012; 5,757,174; 5,767,653; 5,777,514; 5,793,168; 5,798,635; 5,804,950; 5,808,455; 5,811,999;
5,818,207; 5,818,669; 5,825,165; 5,825,223; 5,838,723; 5.844,378; 5,844,941. Japan: 2,598,946; 2,619,299;
2,704,176; 2,821,714. Other patents are pending.

Sirenza Microdevices, Inc., 303 S. Technology Court , Broomfield, CO 80021, USA

North America 1- 303-327-3030

www.sirenza.com z [e-mail] z [e-mail]

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z China [phone] z India [phone]

25