Datasheet MJW16212 Datasheet (Motorola)

Page 1
3–1
Motorola Bipolar Power Transistor Device Data

NPN Bipolar Power Deflection Transistor For High and Very High Resolution Monitors
The MJW16212 is a state–of–the–art SWITCHMODE bipolar power transistor. It is specifically designed for use in horizontal deflection circuits for 20 mm diameter neck, high and very high resolution, full page, monochrome monitors.
1500 Volt Collector–Emitter Breakdown Capability
Typical Dynamic Desaturation Specified (New Turn–Off Characteristic)
Application Specific State–of–the–Art Die Design
Fast Switching:
200 ns Inductive Fall Time (Typ) 2000 ns Inductive Storage Time (Typ)
Low Saturation Voltage:
0.15 Volts at 5.5 Amps Collector Current and 2.5 A Base Drive
Low Collector–Emitter Leakage Current — 250 µA Max at 1500 Volts — V
CES
High Emitter–Base Breakdown Capability For High Voltage Off Drive Circuits —
8.0 Volts (Min)
MAXIMUM RATINGS
Rating
Symbol
Value
Unit
Collector–Emitter Breakdown Voltage
V
CES
1500
Vdc
Collector–Emitter Sustaining Voltage
V
CEO(sus)
650
Vdc
Emitter–Base Voltage
V
EBO
8.0
Vdc
RMS Isolation Voltage (2) (for 1 sec, TA = 25_C, Per Fig. 14 Rel. Humidity < 30%) Per Fig. 15
V
ISOL
— —
V
Collector Current — Continuous
Collector Current — Pulsed (1)
I
C
I
CM
10 15
Adc
Base Current — Continuous
Base Current — Pulsed (1)
I
B
I
BM
5.0 10
Adc
Maximum Repetitive Emitter–Base
Avalanche Energy
W (BER)
0.2
mJ
Total Power Dissipation @ TC = 25_C
Total Power Dissipation @ TC = 100_C
Derated above TC = 25_C
P
D
150
39
1.49
Watts
W/_C
Operating and Storage Temperature Range
TJ, T
stg
–55 to 125
_
C
THERMAL CHARACTERISTICS
Characteristic
Symbol
Max
Unit
Thermal Resistance — Junction to Case
R
θJC
0.67
_
C/W
Lead Temperature for Soldering Purposes
1/8 from the case for 5 seconds
T
L
275
_
C
(1) Pulse Test: Pulse Width = 5.0 ms, Duty Cycle v 10%. (2) Proper strike and creepage distance must be provided.
Preferred devices are Motorola recommended choices for future use and best overall value.
SCANSWITCH and SWITCHMODE are trademarks of Motorola Inc.

SEMICONDUCTOR TECHNICAL DATA
Order this document
by MJW16212/D
           
Motorola, Inc. 1995

POWER TRANSISTOR
10 AMPERES
1500 VOLTS – V
CES
50 AND 150 WATTS
*Motorola Preferred Device
CASE 340F–03
TO–247AE
REV 1
Page 2
MJW16212
3–2
Motorola Bipolar Power Transistor Device Data
ELECTRICAL CHARACTERISTICS (T
C
= 25_C unless otherwise noted)
Characteristic
Symbol
Min
Typ
Max
ÎÎÎ
ÎÎÎ
ÎÎÎ
Unit
OFF CHARACTERISTICS (2)
Collector Cutoff Current (VCE = 1500 V, VBE = 0 V)
Collector Cutoff Current (VCE = 1200 V, VBE = 0 V)
I
CES
— —
— —
250
25
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
µAdc
Emitter–Base Leakage (VEB = 8.0 Vdc, IC = 0)
I
EBO
25
ÎÎÎ
ÎÎÎ
ÎÎÎ
µAdc
Emitter–Base Breakdown Voltage (IE = 1.0 mA, IC = 0)
V
(BR)EBO
8.0
11
ÎÎÎ
ÎÎÎ
ÎÎÎ
Vdc
Collector–Emitter Sustaining Voltage (Table 1) (IC = 10 mAdc, IB = 0)
V
CEO(sus)
650
ÎÎÎ
ÎÎÎ
ÎÎÎ
Vdc
ON CHARACTERISTICS (2)
Collector–Emitter Saturation Voltage (IC = 5.5 Adc, IB = 2.2 Adc)
Collector–Emitter Saturation Voltage (IC = 3.0 Adc, IB = 400 mAdc)
V
CE(sat)
— —
0.15
0.14
1.0
1.0
ÎÎÎ
ÎÎÎ
ÎÎÎ
Vdc
Base–Emitter Saturation Voltage (IC = 5.5 Adc, IB = 2.2 Adc)
V
BE(sat)
0.9
1.5
ÎÎÎ
ÎÎÎ
ÎÎÎ
Vdc
DC Current Gain (IC = 1.0 A, VCE = 5.0 Vdc)
DC Current Gain (IC = 10 A, VCE = 5.0 Vdc)
h
FE
4.0
24
6.0
— 10
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
DYNAMIC CHARACTERISTICS
Dynamic Desaturation Interval (IC = 5.5 A, IB1 = 2.2 A, LB = 1.5 µH)
t
ds
350
ÎÎÎ
ÎÎÎ
ÎÎÎ
ns
Output Capacitance
(VCE = 10 Vdc, IE = 0, f
test
= 100 kHz)
C
ob
180
350
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
pF
Gain Bandwidth Product
(VCE = 10 Vdc, IC = 0.5 A, f
test
= 1.0 MHz)
f
T
2.75
ÎÎÎ
ÎÎÎ
ÎÎÎ
MHz
Emitter–Base Turn–Off Energy
(EB
(avalanche)
= 500 ns, RBE = 22 )
EB
(off)
35
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
µJ
Collector–Heatsink Capacitance — MJF16212 Isolated Package
(Mounted on a 1 x 2 x 1/16 Copper Heatsink, VCE = 0, f
test
= 100 kHz)
C
c–hs
5.0
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
pF
SWITCHING CHARACTERISTICS
Inductive Load (IC = 5.5 A, IB = 2.2 A), High Resolution Deflection
Simulator Circuit Table 2
Storage Fall Time
t
sv t
fi
— —
2000
200
4000
350
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ns
(2) Pulse Test: Pulse Width = 300 µs, Duty Cycle v 2.0%.
I
C
, COLLECTOR CURRENT (A)
VCE, COLLECTOR–EMITTER VOLTAGE (V)
Figure 1. Maximum Forward Bias
Safe Operating Area
50
1
10
1
0.02 70
BONDING WIRE LIMIT THERMAL LIMIT SECOND BREAKDOWN
I
C
, COLLECTOR–EMITTER CURRENT (A)
0.1
7 20 1K
20
0.2
DC
TJ = 25°C
5 ms
10 µs
2
5
0.5
50 300 1500
IC/IB = 5 TJ
100°C
0
VCE, COLLECTOR–EMITTER VOLTAGE (V)
900
Figure 2. Maximum Reverse Bias
Safe Operating Area
10
18
6
2
600 1200
100
0.05
0.01
1003 10 20030
MJH16212
14
2 300 5005 700
100
ns
II
SAFE OPERATING AREA
Page 3
MJW16212
3–3
Motorola Bipolar Power Transistor Device Data
SAFE OPERATING AREA (continued)
FORWARD BIAS
There are two limitations on the power handling ability of a transistor: average junction temperature and second break­down. Safe operating area curves indicate IC – VCE limits of the transistor that must be observed for reliable operation; i.e., the transistor must not be subjected to greater dissipa­tion than the curves indicate.
The data of Figure 1 is based on TC = 25_C; T
J(pk)
is variable depending on power level. Second breakdown pulse limits are valid for duty cycles to 10% but must be derated when TC 25_C. Second breakdown limitations do not der­ate the same as thermal limitations. Allowable current at the voltages shown on Figure 1 may be found at any case tem­perature by using the appropriate curve on Figure 3.
At high case temperatures, thermal limitations will reduce the power that can be handled to values less than the limita­tions imposed by second breakdown.
Figure 3. Power Derating
25
TC, CASE TEMPERATURE (
°
C)
0
45 85 125
0.6
POWER DERATING FACTOR
SECOND BREAKDOWN
DERATING
1
0.8
0.4
0.2
65
THERMAL
DERATING
105
REVERSE BIAS
For inductive loads, high voltage and high current must be sustained simultaneously during turn–off, in most cases, with the base–to–emitter junction reverse biased. Under these conditions the collector voltage must be held to a safe level at or below a specific value of collector current. This can be accomplished by several means such as active clamping,
RC snubbing, load line shaping, etc.
The safe level for these devices is specified as Reverse Biased Safe Operating Area and represents the voltage– current condition allowable during reverse biased turnoff. This rating is verified under clamped conditions so that the device is never subjected to an avalanche mode. Figure 2 gives the RBSOA characteristics.
H.P. 214
OR EQUIV.
P.G.
0
–35 V
50
500
1
µ
F
100
–V
2N5337
2N6191
+V
11 V
100
0.02
µ
F
20
10 µF
0.02
µ
F
+ –
R
B1
R
B2
A
A
50
T
1
+V
0 V
–V
*I
B
*I
C
T.U.T.
L
MR856
V
clamp
V
CC
I
C
V
CE
I
B
I
B1
I
B2
I
C(pk)
V
CE(pk)
T1[
L
coil(ICpk
)
V
CC
Note: Adjust –V to obtain desired V
BE(off)
at Point A.
T1 adjusted to obtain I
C(pk)
V
(BR)CEO
L = 10 mH RB2 = VCC = 20 Volts
RBSOA
L = 200 µH RB2 = 0 VCC = 20 Volts RB1 selected for desired I
B1
*Tektronix
*P–6042 or *Equivalent
+ –
Table 1. RBSOA/V
(BR)CEO(SUS)
Test Circuit
Page 4
MJW16212
3–4
Motorola Bipolar Power Transistor Device Data
C, CAPACITANCE (pF)
f , TRANSITION FREQUENCY
τ
V
BE
, BASE–EMITTER VOLTAGE (V)
V
CE
, COLLECTOR–EMITTER VOLTAGE (V) V
CE
, COLLECTOR–EMITTER VOLTAGE (V)
Figure 4. Typical Collector–Emitter
Saturation Region
IB, BASE CURRENT (A)
0.7
0.1
.03
0.3
0.3
10 A
.05 1 2
4 5.5IC = 2
0.03
0.1 0.2 0.5
0.02
5
10
Figure 5. Typical Emitter–Base
Saturation Voltage
0.30.2 0.5
5
0.7
0.1
0.70.1 1 10
10
2
TJ = 25°C
2 3 5 7
IC, COLLECTOR CURRENT (A)
IC/IB = 5 TJ = 100
°
C
0.3
0.5
0.07
0.2
0.05
0.01
3
7
2 1
3
7
1
0.2
3
0.5
IC, COLLECTOR CURRENT (A)
Figure 6. Typical Collector–Emitter
Saturation Voltage
0.5
3
0.2
5
10
1
0.1
7
0.3
2
0.7
0.5 32 50.7 1
0.1 0.2 0.3
7
IC, COLLECTOR CURRENT (A)
Figure 7. Typical Transition Frequency
VCE = 10 V f
(test)
= 1 MHz
TC = 25°C
0 1 2 3 4 65
5
2
0
4
3
1
Figure 8. Typical Capacitance
10000
VR, REVERSE VOLTAGE (V)
C
ib
1
500
20
1
7 50 300
1000
50
2
2000
100
5000
200
10
3 10 100
705 30 200 1000
5
2 20 500
f
test
= 1 MHz
8
.02
.01 5 7
10
= 25°C
IC/IB = 10 TJ = 100
°
C
= 25°C
IC/IB = 5 TJ = 100
°
C
= 25°C
IC/IB = 10 TJ = 100
°
C
= 25°C
10
C
ob
Page 5
MJW16212
3–5
Motorola Bipolar Power Transistor Device Data
DYNAMIC DESATURATIION
The SCANSWITCH series of bipolar power transistors are specifically designed to meet the unique requirements of hor­izontal deflection circuits in computer monitor applications. Historically, deflection transistor design was focused on mini­mizing collector current fall time. While fall time is a valid figure of merit, a more important indicator of circuit perfor­mance as scan rates are increased is a new characteristic, “dynamic desaturation.” In order to assure a linear collector current ramp, the output transistor must remain in hard satu­ration during storage time and exhibit a rapid turn–off transi­tion. A sluggish transition results in serious consequences. As the saturation voltage of the output transistor increases,
the voltage across the yoke drops. Roll off in the collector current ramp results in improper beam deflection and distor­tion of the image at the right edge of the screen. Design changes have been made in the structure of the SCANS­WITCH series of devices which minimize the dynamic desa­turation interval. Dynamic desaturation has been defined in terms of the time required for the VCE to rise from 1.0 to
5.0 volts (Figures 9 and 10) and typical performance at opti­mized drive conditions has been specified. Optimization of device structure results in a linear collector current ramp, ex­cellent turn–off switching performance, and significantly low­er overall power dissipation.
U2
MC7812
V
I
V
O
G N D
+
+
+
+
+24 V
C1
100
µ
F
C2
10
µ
F
C3
10
µ
F
R7
2.7 k
R8
9.1 k
R9
470
R10
47
C5
0.1
C4
0.005
R2
R510R3250
R6 1 k
R12 470 1 W
D1
MUR110
T1
LB
R4 22
Q4
DUT
V
CE
CY
LY
C6
100
µ
F
R5 1 k
(IC)
(IB)
Q5
MJ11016
Q2
MJ11016
Q3
MJE
15031
R11 470 1 W
100 V
D2
MUR460
U1
MC1391P
%
OSC V
CC
OUT
GND
7 6
8 1
2
(DC)
BS170
Q1
SYNC
Table 2. High Resolution Deflection Application Simulator
R1 1 k
6.2 V
T1:Ferroxcube Pot Core #1811 P3C8 LB = 1.5 µH
Primary/Sec. Turns Ratio = 18:6 CY = 0.01 µF Gapped for LP = 30 µH LY = 13 µH
V
CE
, COLLECTOR–EMITTER VOLTAGE (V)
I
B
, BASE CURRENT (A)
Figure 9. Deflection Simulator Circuit Base
Drive Waveform
TIME (2 µs/DIV)
IB1 = 1.3 A
Figure 10. Definition of Dynamic
Desaturation Measurement
TIME (ns)
t
ds
DYNAMIC DESATURATION TIME IS MEASURED FROM VCE = 1 V TO VCE = 5 V
1
4
5
0
3
2
0 6 84
2 10
IB2 = 4.9 A
Page 6
MJW16212
3–6
Motorola Bipolar Power Transistor Device Data
IC, COLLECTOR CURRENT (A)
Figure 11. Typical Resistive Storage Time
t
s
, RESISTIVE STORAGE TIME ( s)
15
5
2
3
7
1 2 753
IC, COLLECTOR CURRENT (A)
Figure 12. Typical Resistive Fall Time
t
f
, RESISTIVE FALL TIME ( s)
700
100
300
1500
2 3 5 71 10
200
500
β
f
= 5
TJ = 25
°
C
µ
µ
IB2 = I
B1
IB2 = 2 (IB1)
β
f
= 5
TJ = 25
°
C
IB2 = I
B1
IB2 = 2 (IB1)
10
1000
1
10 15 15
ts and t
f
+15
150
100
100 µF
MTP8P10
MPF930
MPF930
MUR105
MJE210
150
500 µF
V
off
50
+10 V
MTP12N10
MTP8P10
R
B1
R
B2
A
1
µ
F
1
µ
F
T.U.T.
*I
C
*I
B
A
R
L
V
CC
V
(off)
adjusted to give specified off drive
V
CC
250 V
R
L
28
I
C
5.5 A
I
B1
1.1 A
I
B2
Per Spec
R
B1
3.3
R
B2
Per Spec
Table 3. Resistive Load Switching
t, TIME (ms)
0.01 1 100.1
1
0.2
0.1
0.05
r(t), TRANSIENT THERMAL
R
θ
JC
(t) = r(t) R
θ
JC
R
θ
JC
= 0.7
°
C/W MAX D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t
1
T
J(pk)
– TC = P
(pk)
R
θ
JC
(t)
P
(pk)
t
1
t
2
DUTY CYCLE, D = t1/t
2
SINGLE PULSE
RESISTANCE (NORMALIZED)
Figure 13. Thermal Response
0.5
D = 0.5
100 1000 10000
0.2
0.1
Page 7
MJW16212
3–7
Motorola Bipolar Power Transistor Device Data
EMITTER–BASE TURN–OFF ENERGY, EB
(off)
Emitter–base turn–off energy is a n ew specification included o n the S CANSWITCH d ata s heets. Typical techniques for driving horizontal outputs rely on a pulse transformer to supply forward base current, and a turnoff net­work that includes a series base inductor to limit the rate of transition from forward to reverse. An alternate drive scheme has been used to characterize the SCANSWITCH series of devices (see Figure 2). This circuit ramps the base drive to eliminate the heavy overdrive at the beginning of the collec­tor current ramp and underdrive just prior to turn–off ob­served in typical drive topologies. This high performance
drive has two additional important advantages. First, the con­figuration of T1 allows Lb to be placed outside the path of for­ward base current making it unnecessary to expend energy to reverse the current flow as in a series based inductor. Se­cond, there is no base resistor to limit forward base current and hence no power loss associated with setting the value of the forward base current. The ramp generating process stores rather than dissipates energy. Tailoring the amount of energy stored in T1 to the amount of energy, EB
(off)
, that is required to turn the output transistor off results in essentially lossless operation. [Note: B+ and the primary inductance of T1 (LP) are chosen such that 1/2LPl
b
2
= EB
(off)
.]
Figure 14. Screw or Clip Mounting Position
for Isolation Test Number 1
*Measurement made between leads and heatsink with all leads shorted together
LEADS
HEATSINK
0.099” MIN
Figure 15. Screw or Clip Mounting Position
for Isolation Test Number 2
MOUNTED
FULLY ISOLATED
PACKAGE
LEADS
HEATSINK
MOUNTED
FULLY ISOLATED
PACKAGE
0.110” MIN
TEST CONDITIONS FOR ISOLATION TESTS* (MJF16212 ONLY)
4–40 SCREW
PLAIN WASHER
HEATSINK
COMPRESSION WASHER
NUT
CLIP
HEATSINK
Laboratory tests on a limited number of samples indicate, when using the screw and compression washer mounting technique, a screw torque of 6 to 8 in.lbs is sufficient to provide maximum power dissipation capability . The compression washer helps to maintain a con­stant pressure on the package over time and during large temperature excursions.
Destructive laboratory tests show that using a hex head 4-40 screw, without washers, and applying a torque in excess of 20 in.lbs will cause the plastic to crack around the mounting hole, resulting in a loss of isolation capability.
Additional tests on slotted 4-40 screws indicate that the screw slot fails between 15 to 20 in.lbs without adversely affecting the pack­age. However, in order to positively ensure the package integrity of the fully isolated device, Motorola does not recommend exceeding 10 in.lbs of mounting torque under any mounting conditions.
Figure 16. Typical Mounting Techniques*
Figure 16a. Screw–Mounted Figure 16b. Clip–Mounted
MOUNTING INFORMATION** (MJF16212 ONLY)
**For more information about mounting power semiconductors see Application Note AN1040.
Page 8
MJW16212
3–8
Motorola Bipolar Power Transistor Device Data
PACKAGE DIMENSIONS
CASE 340F–03
TO–247AE
ISSUE E
DIMAMIN MAX MIN MAX
INCHES
20.40 20.90 0.803 0.823
MILLIMETERS
B 15.44 15.95 0.608 0.628 C 4.70 5.21 0.185 0.205 D 1.09 1.30 0.043 0.051 E 1.50 1.63 0.059 0.064 F 1.80 2.18 0.071 0.086 G 5.45 BSC 0.215 BSC H 2.56 2.87 0.101 0.113 J 0.48 0.68 0.019 0.027 K 15.57 16.08 0.613 0.633 L 7.26 7.50 0.286 0.295 P 3.10 3.38 0.122 0.133 Q 3.50 3.70 0.138 0.145 R 3.30 3.80 0.130 0.150 U 5.30 BSC 0.209 BSC V 3.05 3.40 0.120 0.134
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
STYLE 3:
PIN 1. BASE
2. COLLECTOR
3. EMITTER
4. COLLECTOR
R
P
A
K
V
F
D
G
U
L
E
0.25 (0.010)MT B
M
0.25 (0.010)MY Q
S
J
H
C
4
1 2 3
–T–
–B–
–Y–
–Q–
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MJW16212/D
*MJW16212/D*
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