Datasheet MJE 13009 Datasheet (INCHANGE)

MJE13009

Preferred Device

SWITCHMODEt Series NPN Silicon Power Transistors

The MJE13009 is designed for high−voltage, high−speed power switching inductive circuits where fall time is critical. They are particularly suited for 115 and 220 V SWITCHMODE applications such as Switching Regulators, Inverters, Motor Controls, Solenoid/Relay drivers and Deflection circuits.

Features

• V

CEO(sus)

• Reverse Bias SOA with Inductive Loads @ T

• Inductive Switching Matrix 3 to 12 Amp, 25 and 100_C t

100_C is 120 ns (Typ)

• 700 V Blocking Capability

• SOA and Switching Applications Information

• Pb−Free Package is Available*

400 V and 300 V

= 100_C

C

@ 8 A,

c

http://onsemi.com

12 AMPERE

NPN SILICON

POWER TRANSISTOR

400 VOLTS − 100 WATTS

MAXIMUM RATINGS

Rating Symbol Value Unit

Collector−Emitter Voltage V Collector−Emitter Voltage V Emitter−Base Voltage V Collector Current − Continuous

Base Current − Continuous

Emitter Current − Continuous

Total Device Dissipation @ TC = 25_C Derate above 25°C

Operating and Storage Junction Temperature Range

− Peak (Note 1)

TJ, T

CEO(sus)

CEV EBO

I

C

I

CM

I

B

I

BM

I

E

I

EM

P

D

P

D

stg

400 Vdc 700 Vdc

9 Vdc

12 24

6

12 18

36

2

16

100 800

−65 to +150

W/_C

Adc

W

_C

THERMAL CHARACTERISTICS

Characteristics Symbol Max Unit

Thermal Resistance, Junction−to−Ambient Thermal Resistance, Junction−to−Case Maximum Lead Temperature for Soldering

Purposes 1/8″ from Case for 5 Seconds

Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected.

1. Pulse Test: Pulse Width = 5 ms, Duty Cycle ≤ 10%.

*For additional information on our Pb−Free strategy and soldering details, please

download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.

R

q

JA

R

q

JC

T

L

62.5

1.25

275

_C/W _C/W

_C

TO−220AB

CASE 221A−09

2

3

STYLE 11

MARKING DIAGRAM

MJE13009G

AY WW

A = Assembly Location Y = Year WW = Work Week G = Pb−Free Package

ORDERING INFORMATION

Device Package Shipping

MJE13009 TO−220 50 Units / Rail MJE13009G TO−220

Preferred devices are recommended choices for future use and best overall value.

(Pb−Free)

50 Units / Rail

February, 2006 − Rev. 7

1 Publication Order Number:

MJE13009/D

MJE13009

Î

ELECTRICAL CHARACTERISTICS (T

= 25_C unless otherwise noted)

C

Characteristic

OFF CHARACTERISTICS (Note 2)

Collector−Emitter Sustaining Voltage

(IC = 10 mA, IB = 0)

Collector Cutoff Current

ОООООООООООООООООО

(V

= Rated Value, V

CEV

(V

= Rated Value, V

CEV

ОООООООООООООООООО

= 1.5 Vdc)

BE(off)

= 1.5 Vdc, TC = 100_C)

BE(off)

Emitter Cutoff Current

(VEB = 9 Vdc, IC = 0)

ОООООООООООООООООО

SECOND BREAKDOWN

Second Breakdown Collector Current with base forward biased

ОООООООООООООООООО

Clamped Inductive SOA with Base Reverse Biased

ON CHARACTERISTICS (Note 2)

DC Current Gain

(IC = 5 Adc, VCE = 5 Vdc)

ОООООООООООООООООО

(IC = 8 Adc, VCE = 5 Vdc)

Collector−Emitter Saturation Voltage

ОООООООООООООООООО

(IC = 5 Adc, IB = 1 Adc) (IC = 8 Adc, IB = 1.6 Adc)

ОООООООООООООООООО

(IC = 12 Adc, IB = 3 Adc)

ОООООООООООООООООО

(IC = 8 Adc, IB = 1.6 Adc, TC = 100_C)

Base−Emitter Saturation Voltage

ОООООООООООООООООО

(IC = 5 Adc, IB = 1 Adc) (IC = 8 Adc, IB = 1.6 Adc)

ОООООООООООООООООО

(IC = 8 Adc, IB = 1.6 Adc, TC = 100_C)

DYNAMIC CHARACTERISTICS

Current−Gain − Bandwidth Product

ОООООООООООООООООО

(IC = 500 mAdc, VCE = 10 Vdc, f = 1 MHz)

Output Capacitance

(VCB = 10 Vdc, IE = 0, f = 0.1 MHz)

ОООООООООООООООООО

SWITCHING CHARACTERISTICS

Resistive Load (Table 1)

Delay Time Rise Time Storage Time Fall Time

(VCC = 125 Vdc, IC = 8 A,

ООООООООООО

IB1 = IB2 = 1.6 A, tp = 25 ms, Duty Cycle v 1%)

ООООООООООО

Inductive Load, Clamped (Table 1, Figure 13) Voltage Storage Time Crossover Time

(IC = 8 A, V IB1 = 1.6 A, V

ООООООООООО

= 300 Vdc,

clamp

= 5 Vdc, TC = 100_C)

BE(off)

2. Pulse Test: Pulse Width = 300 ms, Duty Cycle = 2%.

Symbol

V

CEO(sus)

I

CEV

ÎÎ

I

EBO

ÎÎ

I

S/b

ÎÎ

−

h

FE

ÎÎ

V

CE(sat)

ÎÎ

V

BE(sat)

ÎÎ

f

T

ÎÎ

C

ob

ÎÎ

t

d

t

r

t

s

t

f

t

sv

t

c

Min

400

ÎÎ

−

ÎÎ

−

ÎÎ

ООООООООО

8

ÎÎ

6

ÎÎ

−

ÎÎ

−

ÎÎ

−

Typ

−

Î

ÎÎ

−

ÎÎ

−

Î

ÎÎ

See Figure 1 See Figure 2

−

Î

ÎÎ

−

Î

ÎÎ

−

ÎÎ

−

ÎÎ

−

Max

−

1 5

1

40 30

1

1.5 3 2

Unit

Vdc

mAdc

Î

mAdc

Î

Vdc

Î

Vdc

ÎÎ

−

ÎÎ

−

4

ÎÎ

−

ÎÎ

−

Î

−

Î

−

Î

180

Î

0.06

0.45

1.3

0.2

0.92

0.12

ÎÎ

1.2

1.6

ÎÎ

1.5

−

ÎÎ

−

ÎÎ

0.1 1 3

0.7

2.3

0.7

Î

MHz

Î

pF

Î

ms ms ms ms

ms ms

http://onsemi.com

2

MJE13009

100

50

20 10

0.5

0.2

0.1

, COLLECTOR CURRENT (AMP)

C

0.05

I

0.02

0.01

5

2 1

T

= 25°C

C

CURVES APPLY BELOW RATED

7

10

VCE, COLLECTOR−EMITTER VOLTAGE (VOLTS)

dc

THERMAL LIMIT BONDING WIRE LIMIT SECOND BREAKDOWN LIMIT

V

CEO

30 50 70 100

1m

s

Figure 1. Forward Bias Safe Operating Area

100m

σ

200

10m

σ

300 500520

14

12

10

8

6

, COLLECTOR (AMP)

C

4

I

2

0

TC ≤ 100°C IB1 = 2.5 A

3 V

1.5

100 300

0

V

200 400 600

, COLLECTOR−EMITTER CLAMP VOLTAGE (VOLTS)

CEV

V

500 700

Figure 2. Reverse Bias Switching Safe

5 V

V

BE(off)

= 9 V

800

Operating Area

The Safe Operating Area figures shown in Figures 1 and 2 are specified ratings for these devices under the test conditions shown.

0.8

1

SECOND BREAK-

DOWN DERATING

There are two limitations on the power handling ability of a transistor: average junction temperature and second breakdown. Safe operating area curves indicate I

C

− V

CE

limits of the transistor that must be observed for reliable

0.6

0.4

THERMAL

DERATING

operation; i.e., the transistor must not be subjected to greater dissipation than the curves indicate.

The data of Figure 1 is based on TC = 25_C; T

J(pk)

is variable depending on power level. Second breakdown pulse limits are valid for duty cycles to 10% but must be

POWER DERATING FACTOR

0.2

derated when TC ≥ 25_C. Second breakdown limitations do not derate the same as thermal limitations. Allowable current at the voltages shown on Figure 1 may be found at

0

40 120 160

20

60 100 14080

TC, CASE TEMPERATURE (°C)

Figure 3. Forward Bias Power Derating

any case temperature by using the appropriate curve on Figure 3.

T

may be calculated from the data in Figure 4. At high

J(pk)

case temperatures, thermal limitations will reduce the power that can be handled to values less than the limitations imposed by second breakdown. Use of reverse biased safe operating area data (Figure 2) is discussed in the applications information section.

1

0.7 D = 0.5

0.5

0.3

0.2

0.1

0.07

0.05

0.03

0.02

0.01

r(t), TRANSIENT THERMAL RESISTANCE (NORMALIZED)

0.2

0.1

0.05

0.02

SINGLE PULSE

0.02

P

Z

= r(t) R

q

JC(t)

R

q

JC

D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t T

J(pk)

0.05 1 2 5 10 20 50 100 200 500

0.1 0.50.2 1.0 k

t, TIME (ms)

Figure 4. Typical Thermal Response [Z

q

JC

= 1.25°C/W MAX

(pk)

1

Z

q

− TC = P

JC(t)

(t)]

q

JC

(pk)

t

1

t

2

DUTY CYCLE, D = t1/t

2

http://onsemi.com

3

MJE13009

50

30

20

, DC CURRENT GAIN

10

FE

h

1.4

1.2

0.8

V, VOLTAGE (VOLTS)

0.6

2

, COLLECTOR−EMITTER VOLTAGE (VOLTS)

CE

V

V, VOLTAGE (VOLTS)

1.6

1.2

0.8

0.4

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

0.05

IC = 1 A

0.1 0.2 0.5 5

3 A

TJ = 25°C

IB, BASE CURRENT (AMP)

5 A 8 A 12 A

0.30.07

Figure 6. Collector Saturation Region

IC/IB = 3

0.7 1 2

TJ = 150°C

25°C

3

− 55°C

TJ = 150°C

25°C

−

55°C

7

5

0.2

0.5 1 5 7

0.3 IC, COLLECTOR CURRENT (AMP)

VCE = 5 V

0.7 3

2

10 20

Figure 5. DC Current Gain

IC/IB = 3

TJ = −55°C

1

25°C

150°C

0.4

0.3 1 70.7 100.2 0.5 325

20

0

0.3 1 70.7 100.2 0.5 325 20

IC, COLLECTOR CURRENT (AMP)IC, COLLECTOR CURRENT (AMP)

Figure 7. Base−Emitter Saturation Voltage Figure 8. Collector−Emitter Saturation

Voltage

10K

1K

100

10

, COLLECTOR CURRENT (A)μI

1

C

0.1

−0.4 −0.2

VCE = 250 V

TJ = 150°C

125°C

100°C

75°C 50°C

25°C

REVERSE FORWARD

0

VBE, BASE−EMITTER VOLTAGE (VOLTS)

Figure 9. Collector Cutoff Region

+0.4+0.2

+0.6

C, CAPACITANCE (pF)

4K

2K

1K 800 600

400

200

100

80 60 40

0.1

0.2 2 20

C

ib

C

ob

10 50

VR, REVERSE VOLTAGE (VOLTS)

Figure 10. Capacitance

TJ = 25°C

200100510.5

500

http://onsemi.com

4

MJE13009

Table 1. Test Conditions for Dynamic Performance

REVERSE BIAS SAFE OPERATING AREA AND INDUCTIVE SWITCHING

DUTY CYCLE ≤ 10%

tr, tf ≤ 10 ns

TEST CIRCUITS

NOTE

PW and V RB Adjusted for Desired I

Coil Data: Ferroxcube Core #6656

VALUES

CIRCUIT

Full Bobbin (~16 Turns) #16

I

C

V

CE

TEST WAVEFORMS

5 V

P

W

68

0.02 mF

Adjusted for Desired I

CC

B1

tf CLAMPED

I

CM

t

1

V

CEM

TIME

0.001 mF

1 k

1N4933

270

C

tf UNCLAMPED ≈ t

t

f

t

2

1N4933

33

1N4933

2N2222

1

+5 V

k

1 k

2N2905

47

100

1/2 W

GAP for 200 mH/20 A L

= 200 mH

coil

OUTPUT WAVEFORMS

2

t

V

clamp

+5 V

MJE210

R

B

I

B

D.U.T.

MJE200

−V

BE(off)

t1 ADJUSTED TO OBTAIN I

C

L

(ICM)

coil

t1 ≈

V

CC

L

(ICM)

coil

t2 ≈

V

clamp

V

CC

L

I

MR826*

C

*SELECTED FOR ≥ 1 kV

5.1 k V

51

VCC = 20 V V

clamp

Test Equipment Scope−Tektronics 475 or Equivalent

V

clamp

CE

= 300 Vdc

RESISTIVE

SWITCHING

+125 V

R

C

TUT

R

B

SCOPE

D1

−4.0 V

VCC = 125 V RC = 15 W D1 = 1N5820 or Equiv. RB = W

+10 V

25 ms

0

−8 V

tr, tf < 10 ns Duty Cycle = 1.0% RB and RC adjusted for desired IB and I

C

http://onsemi.com

5

MJE13009

APPLICATIONS INFORMATION FOR SWITCHMODE SPECIFICATIONS

INTRODUCTION

The primary considerations when selecting a power transistor for SWITCHMODE applications are voltage and current ratings, switching speed, and energy handling capability. In this section, these specifications will be discussed and related to the circuit examples illustrated in Table 2. (Note 3)

VOLTAGE REQUIREMENTS

Both blocking voltage and sustaining voltage are important in SWITCHMODE applications.

Circuits B and C in Table 2 illustrate applications that require high blocking voltage capability. In both circuits the switching transistor is subjected to voltages substantially higher than VCC after the device is completely off (see load line diagrams at IC = I

≈ 0 in Table 2). The blocking

leakage

capability at this point depends on the base to emitter conditions and the device junction temperature. Since the highest device capability occurs when the base to emitter junction is reverse biased (V and specified use condition. Maximum I

), this is the recommended

CEV

at rated V

CEV

is specified at a relatively low reverse bias (1.5 V) both at 25°C and 100_C. Increasing the reverse bias will give some improvement in device blocking capability.

The sustaining or active region voltage requirements in switching applications occur during turn−on and turn−off. If the load contains a significant capacitive component, high current and voltage can exist simultaneously during turn−on and the pulsed forward bias SOA curves (Figure 1) are the proper design limits.

For inductive loads, high voltage and current must be sustained simultaneously during turn−off, in most cases, with the base to emitter junction reverse biased. Under these conditions the collector voltage must be held to a safe level at or below a specific value of collector current. This can be accomplished by several means such as active clamping, RC snubbing, load line shaping, etc. The safe level for these devices is specified as a Reverse Bias Safe Operating Area (Figure 2) which represents voltage−current conditions that can be sustained during reverse biased turn−off. This rating is verified under clamped conditions so that the device is never subjected to an avalanche mode.

In the four application examples (Table 2) load lines are shown in relation to the pulsed forward and reverse biased SOA curves.

the output rectifiers, however, the voltage induced in the primary leakage inductance is not clamped by these diodes and could be large enough to destroy the device. A snubber network or an additional clamp may be required to keep the turn−off load line within the Reverse Bias SOA curve.

Load lines that fall within the pulsed forward biased SOA curve during turn−on and within the reverse bias SOA curve during turn−off are considered safe, with the following assumptions:

1. The device thermal limitations are not exceeded.

2. The turn−on time does not exceed 10 ms (see standard pulsed forward SOA curves in Figure 1).

3. The base drive conditions are within the specified limits shown on the Reverse Bias SOA curve (Figure 2).

CURRENT REQUIREMENTS

An efficient switching transistor must operate at the required current level with good fall time, high energy handling capability and low saturation voltage. On this data sheet, these parameters have been specified at 8 amperes which repre s ents typical design conditions for these devices. The current drive requirements are usually dictated by the V

specification because the maximum saturation

CE(sat)

voltage is specified at a forced gain condition which must be duplicated or exceeded in the application to control the saturation voltage.

SWITCHING REQUIREMENTS

In many switching applications, a major portion of the transistor power dissipation occurs during the fall time (tfi). For this reason considerable effort is usually devoted to reducing the fall time. The recommended way to accomplish this is to reverse bias the base−emitter junction during turn−off. The reverse biased switching characteristics for inductive loads are discussed in Figure 11 and Table 3 and resistive loads in Figures 13 and 14. Usually the inductive load component will be the dominant factor in SWITCHMODE applications and the inductive switching data will more closely represent the device performance in actual application. The inductive switching characteristics are derived from the same circuit used to specify the reverse biased SOA curves, (See Table 1) providing correlation between test procedures and actual use conditions.

In circuits A and D, inductive reactance is clamped by the

diodes shown. In circuits B and C the voltage is clamped by

http://onsemi.com

3. For detailed information on specific switching applications, see ON Semiconductor Application Notes AN−719, AN−767.

6

t, TIME (ns)

1K

700

500

300

200

VCC = 125 V I

= 5

C/IB

= 25°C

T

J

t

r

MJE13009

RESISTIVE SWITCHING PERFORMANCE

2K

1K

700

500

t, TIME (ns)

300

t

s

VCC = 125 V IC/IB = 5 TJ = 25°C

100

70

50

0.3

I

C

V

clamp

I

B 90% I

0.5

td @ V

0.7 3120.2

BE(off)

= 5 V

75 10 20 0.7 1 20.2 0.50.3 751020

IC, COLLECTOR CURRENT (AMP)

Figure 11. Turn−On Time

90% V

t

sv

10%

B1

V

TIME

CEM

t

CEM

90% I

C

rv

t

fi

t

c

10%

Figure 13. Inductive Switching

Measurements

200

t

f

100

IC, COLLECTOR CURRENT (AMP)

Figure 12. Turn−Off Time

I

CURRENT 2 A/DIV

V

CE

C

V

CE

VOLTAGE 50 V/DIV

I

C

V

clamp

t

ti

2%

I

CM

I

C

TIME 20 ns/DIV

Figure 14. Typical Inductive Switching Waveforms

(at 300 V and 12 A with I

= 2.4 A and V

B1

BE(off)

= 5 V)

http://onsemi.com

7

CIRCUIT LOAD LINE DIAGRAMS TIME DIAGRAMS

SERIES SWITCHING REGULATOR

A

V

CC

MJE13009

Table 2. Applications Examples of Switching Circuits

TURN−ON (FORWARD BIAS) SOA

24 A

TC = 100°C

12 A

TURN−

ON

V

O

Collector CurrentCollector CurrentCollector CurrentCollector Current

ton ≤ 10 ms DUTY CYCLE ≤ 10%

PD = 4000 W

350 V

TURN−

OFF

VCC400 V 700 V

COLLECTOR VOLTAGE

2

TURN−OFF (REVERSE BIAS) SOA

1.5 V ≤ V

BE(off)

DUTY CYCLE ≤ 10%

1

≤ 9.0 V

I

C

t

V

CE

TIME

V

CC

t

TIME

RINGING CHOKE INVERTER

V

CC

B

N

PUSH−PULL INVERTER/CONVERTER

C

V

CC

24 A

TURN−ON ton ≤ 10 ms

I

C

TURN−ON DUTY CYCLE ≤ 10%

TURN−ON (FORWARD BIAS) SOA

V

O

TC = 100°C

PD = 4000 W

12 A

TURN−OFF

TURN−ON

V

CC

400 V

VCC + N(Vo)

24 A

TURN−ON (FORWARD BIAS) SOA

TURN−ON ton ≤ 10 ms TURN−ON DUTY CYCLE ≤ 10%

TC = 100°C

V

O

12 A

PD = 4000 W

TURN−ON

TURN−OFF

V

CC

2

350 V

TURN−OFF (REVERSE BIAS) SOA

TURN−OFF 1.5 V ≤ V TURN−OFF DUTY CYCLE ≤ 10%

1

700 V

1

COLLECTOR VOLTAGE

2

350 V

TURN−OFF (REVERSE BIAS) SOA

TURN−OFF 1.5 V ≤ V TURN−OFF DUTY CYCLE ≤ 10%

2 V

CC

400 V

1

700 V

COLLECTOR VOLTAGE

t

off

t

BE(off)

≤ 9.0 V

on

V

CE

+

V

CC

LEAKAGE

t

SPIKE

N(Vo)

V

CC

t

I

C

t

off

t

on

V

≤ 9.0 V

BE(off)

1

CE

2 V

CC

V

CC

t

SOLENOID DRIVER

D

V

CC

SOLENOID

24 A

TC = 100°C

12 A

TURN−ON (FORWARD BIAS) SOA

TURN−ON ton ≤ 10 ms TURN−ON DUTY CYCLE ≤ 10%

PD = 4000 W

2

350 V

TURN−OFF (REVERSE BIAS) SOA

TURN−OFF 1.5 V ≤ V

TURN−OFF

TURN−OFF DUTY CYCLE ≤ 10%

TURN−ON

400 V

1

V

CC

COLLECTOR VOLTAGE

http://onsemi.com

8

700 V

I

C

t

on

off

t

V

≤ 9.0 V

BE(off)

1

CE

V

CC

t

MJE13009

ÎÎÎ

Î

ÎÎÎ

Î

ÎÎÎ

Î

ÎÎÎ

Table 3. Typical Inductive Switching Performance

I

C

AMP

ÎÎ

3

5

ÎÎ

8

ÎÎ

12

T

C

_C

ÎÎ

25

100

25

ÎÎ

100

25

100

ÎÎ

25

100

t

sv

ns

ÎÎ

770

1000

630

ÎÎ

820 720

920

ÎÎ

640 800

NOTE: All Data recorded In the Inductive Switching Circuit In Table 1.

SWITCHING TIME NOTES

In resistive switching circuits, rise, fall, and storage times have been defined and apply to both current and voltage waveforms since they are in phase. However, for inductive loads which are common to SWITCHMODE power supplies and hammer drivers, current and voltage waveforms are not in phase. Therefore, separate measurements must be made on each waveform to determine the total switching time. For this reason, the following new terms have been defined.

tsv = Voltage Storage Time, 90% IB1 to 10% V trv = Voltage Rise Time, 10−90% V tfi = Current Fall Time, 90−10% I tti = Current Tail, 10−2% I

CM

tc = Crossover Time, 10% V

CEM

CM

to 10% I

CEM

CM

An enlarged portion of the turn−off waveforms is shown in Figure 13 to aid in the visual identity of these terms.

t

rv

ns

ÎÎ

100 230

72

ÎÎ

100

55 70

ÎÎ

20 32

t

fi

ns

ÎÎ

150 160

26

ÎÎ

55 27

50

ÎÎ

17 24

t

ti

ns

ÎÎ

200 200

10

ÎÎ

30

2 8

ÎÎ

2 4

t

c

ns

ÎÎ

240 320

100

ÎÎ

180

77

120

ÎÎ

41 54

For the designer, there is minimal switching loss during storage time and the predominant switching power losses occur during the crossover interval and can be obtained using the standard equation from AN222/D:

P

= 1/2 VCCIC(tc) f

SWT

Typical inductive switching waveforms are shown in Figure 14. In general, trv + tfi ] tc. However, at lower test currents this relationship may not be valid.

As is common with most switching transistors, resistive switching is specified at 25_C and has become a benchmark for designers. However, for designers of high frequency converter circuits, the user oriented specifications which make this a “SWITCHMODE” transistor are the inductive switching speeds (tc and tsv) which are guaranteed at 100_C.

http://onsemi.com

9

MJE13009

PACKAGE DIMENSIONS

TO−220AB

CASE 221A−09

ISSUE AA

SEATING

−T−

PLANE

B

4

Q

123

F

T

A

U

C

S

H

K

Z

L

V

R

J

G

D

N

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION Z DEFINES A ZONE WHERE ALL BODY AND LEAD IRREGULARITIES ARE ALLOWED.

DIM MIN MAX MIN MAX

A 0.570 0.620 14.48 15.75 B 0.380 0.405 9.66 10.28 C 0.160 0.190 4.07 4.82 D 0.025 0.035 0.64 0.88

F 0.142 0.147 3.61 3.73 G 0.095 0.105 2.42 2.66 H 0.110 0.155 2.80 3.93

J 0.018 0.025 0.46 0.64 K 0.500 0.562 12.70 14.27

L 0.045 0.060 1.15 1.52 N 0.190 0.210 4.83 5.33 Q 0.100 0.120 2.54 3.04 R 0.080 0.110 2.04 2.79

S 0.045 0.055 1.15 1.39

T 0.235 0.255 5.97 6.47 U 0.000 0.050 0.00 1.27

V 0.045 −−− 1.15 −−−

Z −−− 0.080 −−− 2.04

STYLE 1:

PIN 1. BASE

2. COLLECTOR

3. EMITTER

4. COLLECTOR

MILLIMETERSINCHES

SWITCHMODE is a trademark of Semiconductor Components Industries, LLC.

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

PUBLICATION ORDERING INFORMATION

LITERATURE FULFILLMENT:

Literature Distribution Center for ON Semiconductor P.O. Box 61312, Phoenix, Arizona 85082−1312 USA

Phone: 480−829−7710 or 800−344−3860 Toll Free USA/Canada Fax: 480−829−7709 or 800−344−3867 Toll Free USA/Canada Email: [email protected]

N. American Technical Support: 800−282−9855 Toll Free

USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center

2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051

Phone: 81−3−5773−3850

http://onsemi.com

ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder

For additional information, please contact your local Sales Representative.

MJE13009/D

10