Datasheet mjd41c_mjd42c Datasheet

MJD41C (NPN) MJD42C (PNP)

Complementary Power Transistors

DPAK For Surface Mount Applications

Designed for general purpose amplifier and low speed switching

applications.

Features

• Lead Formed for Surface Mount Applications in Plastic Sleeves

(No Suffix)

• Straight Lead Version in Plastic Sleeves (“1” Suffix)

• Electrically Similar to Popular TIP41 and TIP42 Series

• Epoxy Meets UL 94 V−0 @ 0.125 in

• ESD Ratings: Human Body Model, 3B u 8000 V

Machine Model, C u 400 V

• These are Pb−Free Packages

MAXIMUM RATINGS

Rating Symbol Max Unit

Collector−Emitter Voltage V

Collector−Base Voltage V

Emitter−Base Voltage V

Collector Current − Continuous

Base Current I

Total Power Dissipation @ TC = 25°C

Derate above 25°C

Total Power Dissipation (Note 1)

@ T

= 25°C

A

Derate above 25°C

Operating and Storage Junction

Temperature Range

− Peak

TJ, T

CEO

CB

EB

I

C

B

P

D

P

D

stg

100 Vdc

5 Vdc

6

10

2 Adc

20

0.16

1.75

0.014

−65 to +150 °C

Adc

W/°C

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SILICON

POWER TRANSISTORS

6 AMPERES

100 VOLTS, 20 WATTS

MARKING

DIAGRAMS

4

AYWW

2

1

3

1

2

3

W

A = Assembly Location

W

Y = Year WW = Work Week J4xC = Device Code

G=Pb−Free Package

DPAK

CASE 369C

STYLE 1

4

DPAK−3

CASE 369D

STYLE 1

x = 1 or 2

J4xCG

AYWW J4xCG

THERMAL CHARACTERISTICS

Characteristic Symbol Max Unit

Thermal Resistance, Junction−to−Case

Thermal Resistance, Junction−to−Ambient (Note 1)

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.

1. These ratings are applicable when surface mounted on the minimum pad sizes recommended.

January, 2011 − Rev. 9

R

q

JC

R

q

JA

6.25 °C/W

71.4 °C/W

1 Publication Order Number:

ORDERING INFORMATION

See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet.

MJD41C/D

MJD41C (NPN) MJD42C (PNP)

ELECTRICAL CHARACTERISTICS (T

= 25_C unless otherwise noted)

C

Characteristic

OFF CHARACTERISTICS

Collector−Emitter Sustaining Voltage (Note 2)

= 30 mAdc, IB = 0)

(I

C

Collector Cutoff Current

= 60 Vdc, IB = 0)

(V

CE

Collector Cutoff Current

= 100 Vdc, VEB = 0)

(V

CE

Emitter Cutoff Current

= 5 Vdc, IC = 0)

(V

BE

ON CHARACTERISTICS (Note 2)

DC Current Gain

(IC = 0.3 Adc, VCE = 4 Vdc) (I

= 3 Adc, VCE = 4 Vdc)

C

Collector−Emitter Saturation Voltage

(IC = 6 Adc, IB = 600 mAdc)

Base−Emitter On Voltage

(I

= 6 Adc, VCE = 4 Vdc)

C

DYNAMIC CHARACTERISTICS

Current Gain − Bandwidth Product (Note 3)

(IC = 500 mAdc, VCE = 10 Vdc, f

= 1 MHz)

test

Small−Signal Current Gain

(IC = 0.5 Adc, VCE = 10 Vdc, f = 1 kHz)

2. Pulse Test: Pulse Width v 300 ms, Duty Cycle v 2%.

3. f

= ⎪hfe⎪• f

T

test

.

Symbol

V

CEO(sus)

I

CEO

I

CES

I

EBO

h

FE

V

CE(sat)

V

BE(on)

f

T

h

fe

Min

100

−

30 15

−

3

20

Max

−

50

10

0.5

−

75

1.5

2

−

Unit

Vdc

mAdc

−

Vdc

MHz

−

ORDERING INFORMATION

Device Package Type Package Shipping

MJD41CRLG DPAK

(Pb−Free)

MJD41CT4G DPAK

(Pb−Free)

369C

1800 / Tape & Reel

2500 / Tape & Reel

MJD42CG DPAK

(Pb−Free)

MJD42C1G DPAK−3

(Pb−Free)

MJD42CRLG DPAK

(Pb−Free)

MJD42CT4G DPAK

(Pb−Free)

369D

369C

75 Units / Rail

1800 / Tape & Reel

2500 / Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

†

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2

, POWER DISSIPATION (WATTS)

D

P

2.5

1.5

0.5

MJD41C (NPN) MJD42C (PNP)

TYPICAL CHARACTERISTICS

T

C

A

25

20

2

+11 V

15

TA SURFACE MOUNT

10

1

T

C

0

tr, tf ≤ 10 ns

DUTY CYCLE = 1%

5

0

25

50 75 100 125 150

T, TEMPERATURE (°C)

25 ms

R

B

-9 V

51

-4 V

RB and RC VARIED TO OBTAIN DESIRED CURRENT LEVELS D

MUST BE FAST RECOVERY TYPE, e.g.:

1

MSB5300 USED ABOVE I MSD6100 USED BELOW I

≈ 100 mA

B

≈ 100 mA

B

REVERSE ALL POLARITIES FOR PNP.

V

CC

+30 V

R

C

SCOPE

D

1

Figure 1. Power Derating

500

300 200

100

70

TJ = 150°C

25°C

50

30

, DC CURRENT GAIN

20

FE

h

-55°C

10

7 5

0.06

0.1

0.3 1

0.2 0.4 4

I

, COLLECTOR CURRENT (AMP)

C

Figure 3. DC Current Gain

2

TJ = 25°C

1.6

1.2

V

0.8

V, VOLTAGE (VOLTS)

0.4

0

0.06 0.2 0.4 40.3 1

@ IC/IB = 10

CE(sat)

VBE @ VCE = 4 V

V

BE(sat)

0.1

@ IC/IB = 10

IC, COLLECTOR CURRENT (AMP)

Figure 2. Switching Time Test Circuit

2

VCE = 2 V

1

0.7

0.5

0.3

0.2

t

r

t, TIME (s)μ

0.1

0.07

0.05

0.03

0.02

0.6 2 6

0.06 0.2 0.4 41

0.1

I

, COLLECTOR CURRENT (AMP)

C

0.6 2 6

Figure 4. Turn−On Time

5

3 2

t

1

0.7

0.5

t, TIME (s)μ

0.3

0.2

0.1

0.07

0.6 2 6 0.06 0.2 0.4 41

3

0.05

0.1

s

t

f

0.6 2

IC, COLLECTOR CURRENT (AMP)

td @ V

TJ = 25°C V

= 30 V

CC

= 10

I

C/IB

≈ 5 V

BE(off)

TJ = 25°C V

= 30 V

CC

= 10

I

C/IB

I

= I

B1

B2

6

Figure 5. “On” Voltages Figure 6. Turn−Off Time

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3

MJD41C (NPN) MJD42C (PNP)

0

2

TJ = 25°C

1.6

2.5 A

IB, BASE CURRENT (mA)

5 A

1000500300200100503020

, COLLECTOR-EMITTER VOLTAGE (VOLTS)

CE

V

1.2

0.8

0.4

IC = 1 A

0

10

Figure 7. Collector Saturation Region

1

0.7 D = 0.5

0.5

0.3

0.2

0.1

0.07

0.05

0.03

RESISTANCE (NORMALIZED)

0.02

r(t), EFFECTIVE TRANSIENT THERMAL

0.01

0.2

0.1

0.05

0.02

SINGLE PULSE

0.01 0.05 1 2 5 10 20 50 100 200 5000.1 0.50.2 100

0.01

0.03 0.3 3 30 3000.02

300

200

100

70

C, CAPACITANCE (pF)

50

30

0.5

R

= r(t) R

q

JC(t)

R

q

JC

D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t T

J(pk)

t, TIME (ms)

q

- TC = P

JC

1

(pk) qJC(t)

= 6.25°C/W MAX

C

ib

C

ob

1 3 10 30

2 5 20 50

VR, REVERSE VOLTAGE (VOLTS)

Figure 8. Capacitance

P

(pk)

t

1

t

2

DUTY CYCLE, D = t1/t

TJ = 25°C

2

10

5 3

2

1

0.5

0.3

0.1

0.05

, COLLECTOR CURRENT (AMP)

C

I

0.03

0.01

500ms

dc

5ms

WIRE BOND LIMIT THERMAL LIMIT

CURVES APPLY BELOW RATED V

TC = 25°C SINGLE PULSE T

J

SECOND BREAKDOWN LIMIT

CEO

= 150°C

V

, COLLECTOR-EMITTER VOLTAGE (VOLTS)

CE

Figure 10. Maximum Forward Bias

Safe Operating Area

MJD41C, 42C

Figure 9. Thermal Response

100ms

1ms

There are two limitations on the power handling ability of a transistor: average junction temperature and second breakdown. Safe operating area curves indicate I limits of the transistor that must be observed for reliable operation; i.e., the transistor must not be subjected to greater dissipation than the curves indicate.

The data of Figure 10 is based on T variable depending on conditions. Second breakdown pulse limits are valid for duty cycles to 10% provided T

v 150_C. T

J(pk)

Figure 9. At high case temperatures, thermal limitations will reduce the power that can be handled to values less than the

5030201075321

70

10

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limitations imposed by second breakdown.

4

= 150_C; TC is

J(pk)

may be calculated from the data in

J(pk)

C

− V

CE

L3

L4

b2

e

E

b3

4

12 3

A

B

D

b

0.005 (0.13) C

MJD41C (NPN) MJD42C (PNP)

PACKAGE DIMENSIONS

DPAK

CASE 369C−01

ISSUE D

C

A

c2

DETAIL A

c

M

H

GAUGE

L2

PLANE

L

L1

DETAIL A

ROTATED 90 CW5

A1

SOLDERING FOOTPRINT*

6.20

0.244

2.58

0.101

0.118

H

C

3.0

Z

SEATING PLANE

NOTES:

1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.

2. CONTROLLING DIMENSION: INCHES.

3. THERMAL PAD CONTOUR OPTIONAL WITHIN DIMENSIONS b3, L3 and Z.

4. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR BURRS. MOLD FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT EXCEED 0.006 INCHES PER SIDE.

5. DIMENSIONS D AND E ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY.

6. DATUMS A AND B ARE DETERMINED AT DATUM PLANE H.

DIM MIN MAX MIN MAX

A 0.086 0.094 2.18 2.38

A1 0.000 0.005 0.00 0.13

b 0.025 0.035 0.63 0.89 b2 0.030 0.045 0.76 1.14 b3 0.180 0.215 4.57 5.46

c 0.018 0.024 0.46 0.61 c2 0.018 0.024 0.46 0.61

D 0.235 0.245 5.97 6.22 E 0.250 0.265 6.35 6.73

e 0.090 BSC 2.29 BSC

H 0.370 0.410 9.40 10.41

L 0.055 0.070 1.40 1.78 L1 0.108 REF 2.74 REF L2 0.020 BSC 0.51 BSC L3 0.035 0.050 0.89 1.27 L4 −−− 0.040 −−− 1.01

Z 0.155 −−− 3.93 −−−

STYLE 1:

PIN 1. BASE

2. COLLECTOR

3. EMITTER

4. COLLECTOR

MILLIMETERSINCHES

5.80

0.228

1.6

0.063

SCALE 3:1

6.172

0.243

ǒ

inches

mm

Ǔ

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.

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5

MJD41C (NPN) MJD42C (PNP)

PACKAGE DIMENSIONS

DPAK−3

CASE 369D−01

ISSUE B

V

S

−T−

SEATING PLANE

F

B

R

4

123

G

A

K

3 PL

D

0.13 (0.005) T

C

E

J

H

M

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

DIM MIN MAX MIN MAX

Z

A 0.235 0.245 5.97 6.35 B 0.250 0.265 6.35 6.73 C 0.086 0.094 2.19 2.38 D 0.027 0.035 0.69 0.88 E 0.018 0.023 0.46 0.58 F 0.037 0.045 0.94 1.14

0.090 BSC 2.29 BSC

G

H 0.034 0.040 0.87 1.01 J 0.018 0.023 0.46 0.58 K 0.350 0.380 8.89 9.65 R 0.180 0.215 4.45 5.45 S 0.025 0.040 0.63 1.01 V 0.035 0.050 0.89 1.27 Z 0.155 −−− 3.93 −−−

STYLE 1:

PIN 1. BASE

2. COLLECTOR

3. EMITTER

4. COLLECTOR

MILLIMETERSINCHES

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice

to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

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MJD41C/D

6