Datasheet mjd200_mjd210 Datasheet

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MJD200 (NPN) MJD210 (PNP)

Complementary Plastic Power Transistors

NPN/PNP Silicon DPAK For Surface Mount Applications

http://onsemi.com

Designed for low voltage, low−power, high−gain audio

amplifier applications.

Features

• Collector−Emitter Sustaining Voltage −

CEO(sus)

• High DC Current Gain − h

= 25 Vdc (Min) @ IC = 10 mAdc

= 70 (Min) @ IC = 500 mAdc

= 45 (Min) @ I

= 2 Adc

= 10 (Min) @ IC = 5 Adc

• Lead Formed for Surface Mount Applications in Plastic Sleeves

(No Suffix)

• Low Collector−Emitter Saturation Voltage −

= 0.3 Vdc (Max) @ IC = 500 mAdc

CE(sat)

= 0.75 Vdc (Max) @ IC = 2.0 Adc

• High Current−Gain − Bandwidth Product −

= 65 MHz (Min) @ IC = 100 mAdc

• Annular Construction for Low Leakage −

= 100 nAdc @ Rated V

CBO

• Epoxy Meets UL 94 V−0 @ 0.125 in

• ESD Ratings: Human Body Model, 3B u 8000 V

Machine Model, C u 400 V

• These are Pb−Free Packages

MAXIMUM RATINGS

Rating Symbol Max Unit

Collector−Base Voltage V

Collector−Emitter Voltage V

Emitter−Base Voltage V

Collector Current − Continuous

Base Current I

Total Power Dissipation @ TC = 25°C Derate above 25°C

Total Power Dissipation (Note 1) @ T

= 25°C

Derate above 25°C

Operating and Storage Junction Temperature Range

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.

1. These ratings are applicable when surface mounted on the minimum pad sizes recommended.

− Peak

CEO

TJ, T

stg

40 Vdc

25 Vdc

8.0 Vdc

5.0 10

1.0 Adc

12.5

0.1

1.4

0.011

−65 to +150 °C

Adc

W/°C

SILICON

POWER TRANSISTORS

5 AMPERES

25 VOLTS, 12.5 WATTS

DPAK

CASE 369C

STYLE 1

MARKING DIAGRAM

AYWW

J2x0G

A = Assembly Location Y = Year WW = Work Week

x = 1 or 0

G=Pb−Free Package

ORDERING INFORMATION

See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet.

January, 2011 − Rev. 10

1 Publication Order Number:

MJD200/D

Page 2

MJD200 (NPN) MJD210 (PNP)

THERMAL CHARACTERISTICS

Characteristic Symbol Max Unit

Thermal Resistance, Junction−to−Case

Thermal Resistance, Junction−to−Ambient (Note 2)

2. These ratings are applicable when surface mounted on the minimum pad sizes recommended.

10 °C/W

89.3 °C/W

ELECTRICAL CHARACTERISTICS (T

= 25°C unless otherwise noted)

Characteristic

OFF CHARACTERISTICS

Collector−Emitter Sustaining Voltage (Note 3), (IC = 10 mAdc, IB = 0)

Collector Cutoff Current

= 40 Vdc, IE = 0)

= 40 Vdc, IE = 0, TJ = 125°C)

Emitter Cutoff Current (VBE = 8 Vdc, IC = 0)

ON CHARACTERISTICS

DC Current Gain (Note 3),

= 500 mAdc, VCE = 1 Vdc)

= 2 Adc, VCE = 1 Vdc)

= 5 Adc, VCE = 2 Vdc)

Collector−Emitter Saturation Voltage (Note 3)

= 500 mAdc, IB = 50 mAdc)

= 2 Adc, IB = 200 mAdc)

= 5 Adc, IB = 1 Adc)

Base−Emitter Saturation Voltage (Note 3), (IC = 5 Adc, IB = 1 Adc)

Base−Emitter On Voltage (Note 3), (IC = 2 Adc, VCE = 1 Vdc)

DYNAMIC CHARACTERISTICS

Current−Gain − Bandwidth Product (Note 4)

= 100 mAdc, VCE = 10 Vdc, f

= 10 MHz)

test

Output Capacitance MJD200

= 10 Vdc, IE = 0, f = 0.1 MHz) MJD210

3. Pulse Test: Pulse Width = 300 ms, Duty Cycle [ 2%.

4. f

= ⎪hfe⎪• f

test

Symbol

CEO(sus)

CBO

EBO

CE(sat)

BE(sat)

BE(on)

Min

−

70 45 10

−

Max

−

100 100

100

−

180

−

0.3

0.75

1.8

2.5

1.6

−

120

Unit

Vdc

nAdc mAdc

nAdc

−

Vdc

MHz

ORDERING INFORMATION

Device Package Type Shipping

MJD200G DPAK

(Pb−Free)

MJD200RLG DPAK

(Pb−Free)

MJD200T4G DPAK

(Pb−Free)

MJD210G DPAK

(Pb−Free)

MJD210RLG DPAK

(Pb−Free)

75 Units / Rail

1800 / Tape & Reel

2500 / Tape & Reel

75 Units / Rail

1800 / Tape & Reel

MJD210T4 DPAK

MJD210T4G DPAK

2500 / Tape & Reel

(Pb−Free)

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

†

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Page 3

2.5

1.5

0.5

, POWER DISSIPATION (WATTS)

MJD200 (NPN) MJD210 (PNP)

25 ms

+11 V

-9 V

50 75 100 125 150

TA (SURFACE MOUNT)

tr, tf ≤ 10 ns

DUTY CYCLE = 1%

and RC VARIED TO OBTAIN DESIRED CURRENT LEVELS

MUST BE FAST RECOVERY TYPE, e.g.:

1N5825 USED ABOVE I MSD6100 USED BELOW I

T, TEMPERATURE (°C)

≈ 100 mA

-4 V

REVERSE ALL POLARITIES

+30 V

SCOPE

FOR PNP TEST CIRCUIT,

Figure 1. Power Derating

500 300

200

100

50 30

t, TIME (ns)

5 3

0.01 0.03 0.05 0.50.2

0.02

MJD200 MJD210

, COLLECTOR CURRENT (A)

Figure 3. Turn−On Time Figure 4. Turn−Off Time

0.1 0.3 10

VCC = 30 V I

= 10

C/IB

= 25°C

5213

Figure 2. Switching Time Test Circuit

10K

5K 3K

500 300

200

t, TIME (ns)

100

50 30

MJD200

MJD210

0.01 0.03 0.05 0.50.2

0.02

, COLLECTOR CURRENT (A)

VCC = 30 V I

C/IB

= I

= 10

TJ = 25°C

0.1 0.3 105213

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Page 4

MJD200 (NPN) MJD210 (PNP)

400

200

100

, DC CURRENT GAIN

1.6

NPN MJD200

TJ = 150°C

0.07 0.1 0.3 50.05

TJ = 25°C

25°C

-55°C

0.2

VCE = 1 V V

= 2 V

PNP MJD210

400

200

TJ = 150°C

25°C

100

, DC CURRENT GAIN

0.7 1 320.5

0.07 0.1 0.30.2 0.7 1 20.5

-55°C

, COLLECTOR CURRENT (A)IC, COLLECTOR CURRENT (A)

VCE = 1 V V

= 2 V

50.05 3

Figure 5. DC Current Gain

TJ = 25°C

1.6

V, VOLTAGE (VOLTS)

, TEMPERATURE COEFFICIENTS (mV/ C)°θ

1.2

@ IC/IB = 10

BE(sat)

0.8

VBE @ VCE = 1 V

0.4

CE(sat)

0.05

+2.5

+2

*APPLIES FOR IC/IB ≤ h

+1.5

+1

+0.5

qVC for V

CE(sat)

-0.5

-1

-1.5

-2.5

qVB for V

-2

0.07 0.1 0.3 50.05 0.2 0.7 1 320.5

@ IC/IB = 10

, COLLECTOR CURRENT (A)

FE/3

25°C to 150°C

-55°C to 25°C

25°C to 150°C

, COLLECTOR CURRENT (A)

1.2

@ IC/IB = 10

BE(sat)

0.8

V, VOLTAGE (VOLTS)

VBE @ VCE = 1 V

0.4

320.07 0.20.1 0.50.3 10.7

0.05

CE(sat)

Figure 6. “On” Voltage

+2.5

+2

*APPLIES FOR IC/IB ≤ h

+1.5

+1

+0.5

*qVC for V

-0.5

-1

qVB for V

-2

0.07 0.1 0.3 50.05 0.2 0.7 1 320.5

-55°C to 25°C

, TEMPERATURE COEFFICIENTS (mV/ C)°θ

-1.5

-2.5

Figure 7. Temperature Coefficients

@ IC/IB = 10

IC, COLLECTOR CURRENT (A)

FE/3

25°C to 150°C

CE(sat)

-55°C to 25°C

25°C to 150°C

-55°C to 25°C

IC, COLLECTOR CURRENT (A)

320.07 0.20.1 0.50.3 10.7

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Page 5

0.7

0.5

0.3

0.2

0.1

0.07

0.05

r(t), TRANSIENT THERMAL

0.03

RESISTANCE (NORMALIZED)

0.02

0.01

0.02 0.05 1 2 5 10 20 50 100 2000.1 0.50.2

D = 0.5

0.2

0.1

0.05

0.01

0 (SINGLE PULSE)

0.02

MJD200 (NPN) MJD210 (PNP)

(t) = r(t) q

D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t T

J(pk)

t, TIME (ms)

Figure 8. Thermal Response

= 10°C/W MAX

- TC = P

(pk) qJC

(t)

(pk)

DUTY CYCLE, D = t1/t

5 3

0.1

, COLLECTOR CURRENT (AMP)

0.01

TJ = 150°C

, COLLECTOR−EMITTER VOLTAGE (V)

5ms

100ms

500ms

BONDING WIRE LIMITED THERMALLY LIMITED @ T (SINGLE PULSE) SECOND BREAKDOWN LIMITED CURVES APPLY BELOW RATED V

CEO

= 25°C

Figure 9. Active Region Safe Operating Area

200

100

1ms

There are two limitations on the power handling ability of a transistor: average junction temperature and second breakdown. Safe operating area curves indicate I

− V

limits of the transistor that must be observed for reliable operation; i.e., the transistor must not be subjected to greater dissipation than the curves indicate.

The data of Figure 9 is based on T

= 150°C; TC is

J(pk)

variable depending on conditions. Second breakdown pulse limits are valid for duty cycles to 10% provided T v 150°C. T

may be calculated from the data in

J(pk)

Figure 8. At high case temperatures, thermal limitations will reduce the power that can be handled to values less than the

2010753210.3

limitations imposed by second breakdown.

TJ = 25°C

C, CAPACITANCE (pF)

0.6

MJD200 (NPN) MJD210 (PNP)

, REVERSE VOLTAGE (V)

Figure 10. Capacitance

http://onsemi.com

201064210.4

Page 6

12 3

0.005 (0.13) C

MJD200 (NPN) MJD210 (PNP)

PACKAGE DIMENSIONS

DPAK

CASE 369C−01

ISSUE D

DETAIL A

GAUGE PLANE

DETAIL A

ROTATED 90 CW5

SOLDERING FOOTPRINT*

6.20

0.244

2.58

0.101

3.0

0.118

SEATING PLANE

NOTES:

1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.

2. CONTROLLING DIMENSION: INCHES.

3. THERMAL PAD CONTOUR OPTIONAL WITHIN DIMENSIONS b3, L3 and Z.

4. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR BURRS. MOLD FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT EXCEED 0.006 INCHES PER SIDE.

5. DIMENSIONS D AND E ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY.

6. DATUMS A AND B ARE DETERMINED AT DATUM PLANE H.

DIM MIN MAX MIN MAX

A 0.086 0.094 2.18 2.38

A1 0.000 0.005 0.00 0.13

b 0.025 0.035 0.63 0.89 b2 0.030 0.045 0.76 1.14 b3 0.180 0.215 4.57 5.46

c 0.018 0.024 0.46 0.61

c2 0.018 0.024 0.46 0.61 D 0.235 0.245 5.97 6.22

E 0.250 0.265 6.35 6.73

e 0.090 BSC 2.29 BSC

H 0.370 0.410 9.40 10.41

L 0.055 0.070 1.40 1.78 L1 0.108 REF 2.74 REF L2 0.020 BSC 0.51 BSC L3 0.035 0.050 0.89 1.27 L4 −−− 0.040 −−− 1.01

Z 0.155 −−− 3.93 −−−

STYLE 1:

PIN 1. BASE

2. COLLECTOR

3. EMITTER

4. COLLECTOR

MILLIMETERSINCHES

5.80

0.228

1.6

0.063

SCALE 3:1

6.172

0.243

inches

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

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MJD200/D