Datasheet mjd148 Datasheet

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MJD148

NPN Silicon Power Transistor

DPAK For Surface Mount Applications

Designed for general purpose amplifier and low speed switching

applications.

Features

• High Gain − 50 Min @ I

• Low Saturation Voltage − 0.5 V @ I

• High Current Gain − Bandwidth Product − f

= 250 mAdc

= 2.0 A

= 3.0 MHz Min @

• Epoxy Meets UL 94 V−0 @ 0.125 in

• ESD Ratings: Human Body Model, 3B; >8000 V

Machine Model, C; >400 V

• This is a Pb−Free Package

MAXIMUM RATINGS

Rating

Collector−Emitter Voltage

Collector−Base Voltage

Emitter−Base Voltage

Collector Current − Continuous

Base Current

Total Power Dissipation @ TC = 25°C

Derate above 25°C

Total Power Dissipation (Note 1)

@ T

= 25°C

Derate above 25°C

Operating and Storage Junction

Temperature Range

− Peak

Symbol

CEO

TJ, T

stg

Value

5.0

4.0

7.0

0.16

1.75

0.014

−55 to +150

Unit

Vdc

Adc

mAdc

W/°C

°C

http://onsemi.com

POWER TRANSISTOR

4.0 AMPERES

45 VOLTS, 20 WATTS

MARKING DIAGRAM

DPAK

CASE 369C

STYLE 1

A = Assembly Location Y = Year WW = Work Week J148 = Device Code G = Pb−Free Package

ORDERING INFORMATION

Device Package Shipping

MJD148T4 DPAK 2500/Tape & Reel

MJD148T4G DPAK

†For information on tape and reel specifications,

including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.

(Pb−Free)

AYWW

J148G

†

2500/Tape & Reel

THERMAL CHARACTERISTICS

Characteristic

Thermal Resistance, Junction−to−Case

Thermal Resistance, Junction−to−Ambient

(Note 1)

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.

1. These ratings are applicable when surface mounted on the minimum pad sizes recommended.

January, 2011 − Rev. 5

Symbol

Max

6.25

71.4

Unit

°C/W

1 Publication Order Number:

MJD148/D

Page 2

MJD148

ELECTRICAL CHARACTERISTICS (T

= 25°C unless otherwise noted)

Characteristic

OFF CHARACTERISTICS

Collector−Emitter Sustaining Voltage (Note 2)

Collector Cutoff Current

Emitter Cutoff Current

IC = 100 mAdc, IB = 0

VCB = 45 Vdc, IE = 0

VBE = 5 Vdc, IC = 0

ON CHARACTERISTICS

DC Current Gain (Note 2)

Collector−Emitter Saturation Voltage (Note 2)

Base−Emitter On Voltage (Note 2)

IC = 10 mAdc, VCE = 5 Vdc I

= 0.5 Adc, VCE = 1 Vdc

= 2 Adc, VCE = 1 Vdc

= 3 Adc, VCE = 1 Vdc

IC = 2 Adc, IB = 0.2 Adc

IC = 2 Adc, VCE = 1 Vdc

DYNAMIC CHARACTERISTICS

Current−Gain−Bandwidth Product

IC = 250 mAdc, VCE = 1 Vdc, f = 1 MHz

2. Pulse Test: Pulse Width v 300 ms, Duty Cycle v 2%.

Test Conditions

Symbol

CEO(sus)

CBO

EBO

CE(sat)

BE(on)

Min

−

40 85 50 30

−

Max

−

375

−

0.5

1.1

−

Unit

Vdc

mAdc

−

Vdc

MHz

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Page 3

MJD148

TJ = 150°C

= 25°C

0.5

0.3

0.2

, DC CURRENT GAIN (NORMALIZED)

0.1

0.004

0.007 0.02 0.050.03

0.01 0.1 0.2 0.3 0.5 1 2 3 4

TJ = 25°C

1.6

1.2

IC = 10 mA

TYPICAL CHARACTERISTICS

−55°C

IC, COLLECTOR CURRENT (A)

Figure 1. DC Current Gain

100 mA 1 A 3 A

VCE = 2 V V

= 10 V

0.8

0.4

, COLLECTOR−EMITTER VOLTAGE (V)

0.05

1.6

1.2

0.8

VOLTAGE (V)

0.4

0.005

0.1 1 2 3 5 10 20 30 500

0.07 0.2 0.50.3

0.7 7 50 70 100 200 300 IB, BASE CURRENT (mA)

Figure 2. Collector Saturation Region

TJ = 25°C

@ IC/IB = 10

BE(sat)

@ IC/IB = 10

CE(sat)

0.01 0.020.030.05 0.1 0.5 1 4

VBE @ VCE = 2 V

0.20.3 2 3

IC, COLLECTOR CURRENT (A)

Figure 3. “On” Voltages

+ 2.5

+ 1.5

+ 0.5

*qV for V

−0.5

(mV/°C)

−1

−1.5

−2

, TEMPERATURE COEFFICIENTS

−2.5

0.005 0.01 0.020.030.05 0.1 0.5 10.20.3 2 3

qV for V

IC, COLLECTOR CURRENT (A)

Figure 4. Temperature Coefficients

*APPLIES FOR IC/IB ≤ hFE/2

= − 65°C to + 150°C

CE(sat)

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Page 4

MJD148

VCE = 30 V

TJ = 150°C

100°C

0.7

0.5

0.3

0.2

0.1

0.07

0.05

(NORMALIZED)

0.03

0.02

0.01

r(t), TRANSIENT THERMAL RESISTANCE

0.01

, COLLECTOR CURRENT (mA)

D = 0.5

0.2

0.1

0.05

0.01

SINGLE PULSE

0.02 0.1 0.50.2

0.05 1 2 5 10 20 50 100 200 1 k500

−1

−2

−3

−0.4

REVERSE FORWARD

25°C

CES

−0.3 −0.2 −0.1 0 + 0.1 +0.2 + 0.3 + 0.4 + 0.5 + 0.6

VBE, BASE−EMITTER VOLTAGE (V)

Figure 5. Collector Cut−Off Region

= r(t) R

JC(t)

= 6.25°C/W MAX

qJC

D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t T

− TC = P

J(pk)

t, TIME (ms)

qJC

(pk) ZqJC

(pk)

(t)

DUTY CYCLE, D = t1/t

, COLLECTOR CURRENT (A)

0.5

0.3

0.2

0.1

0.05

0.03

0.02

0.01

5 3

= 25°C SINGLE PULSE, D ≤ 0.1%

= 150°C

VCE, COLLECTOR−EMITTER VOLTAGE (V)

5ms

1ms

BONDING WIRE LIMIT THERMAL LIMIT SECOND BREAKDOWN LIMIT

510

Figure 7. Maximum Rated Forward Bias

Figure 6. Thermal Response

500 ms

20 30 50 70

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FORWARD BIAS SAFE OPERATING AREA INFORMATION

There are two limitations on the power handling ability of a transistor: average junction temperature and second breakdown. Safe operating area curves indicate I limits of the transistor that must be observed for reliable operation; i.e., the transistor must not be subjected to greater dissipation than the curves indicate.

The data of Figure 7 is based on T

= 150°C; T

J(pk)

is variable depending on conditions. Second breakdown pulse limits are valid for duty cycles to 10% provided T v 150°C. T

may be calculated from the data in

J(pk)

Figure 6. At high case temperatures, thermal limitations will reduce the power that can be handled to values less than the limitations imposed by second breakdown.

− V

J(pk)

Page 5

12 3

0.005 (0.13) C

DETAIL A

MJD148

PACKAGE DIMENSIONS

DPAK (SINGLE GAUGE)

CASE 369C−01

ISSUE D

GAUGE

PLANE

DETAIL A

ROTATED 90 CW5

SOLDERING FOOTPRINT*

6.20

0.244

2.58

0.101

3.0

0.118

SEATING PLANE

NOTES:

1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.

2. CONTROLLING DIMENSION: INCHES.

3. THERMAL PAD CONTOUR OPTIONAL WITHIN DIMENSIONS b3, L3 and Z.

4. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR BURRS. MOLD FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT EXCEED 0.006 INCHES PER SIDE.

5. DIMENSIONS D AND E ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY.

6. DATUMS A AND B ARE DETERMINED AT DATUM PLANE H.

DIM MIN MAX MIN MAX

A 0.086 0.094 2.18 2.38

A1 0.000 0.005 0.00 0.13

b 0.025 0.035 0.63 0.89 b2 0.030 0.045 0.76 1.14 b3 0.180 0.215 4.57 5.46

c 0.018 0.024 0.46 0.61 c2 0.018 0.024 0.46 0.61

D 0.235 0.245 5.97 6.22

E 0.250 0.265 6.35 6.73

e 0.090 BSC 2.29 BSC

H 0.370 0.410 9.40 10.41

L 0.055 0.070 1.40 1.78

L1 0.108 REF 2.74 REF L2 0.020 BSC 0.51 BSC

L3 0.035 0.050 0.89 1.27 L4 −−− 0.040 −−− 1.01

Z 0.155 −−− 3.93 −−−

STYLE 1:

PIN 1. BASE

2. COLLECTOR

3. EMITTER

4. COLLECTOR

MILLIMETERSINCHES

5.80

0.228

1.6

0.063

SCALE 3:1

6.172

0.243

inches

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

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MJD148/D