Datasheet MJ13333 Datasheet (Motorola)

1

Motorola Bipolar Power Transistor Device Data

  

 
   

The MJ13333 transistor is designed for high voltage, high–speed, power switching
in inductive circuits where fall time is critical. It is particularly suited for line operated
switchmode applications such as:

• Switching Regulators

• Inverters

• Solenoid and Relay Drivers

• Motor Controls

• Deflection Circuits

Fast Turn Off Times

200 ns Inductive Fall Time — 25_C (Typ)

1.8 µs Inductive Storage Time — 25_C (Typ)

Operating Temperature Range –65 to +200_C
100_C Performance Specified for:

Reversed Biased SOA with Inductive Loads
Switching Times with Inductive Loads
Saturation Voltages
Leakage Currents

MAXIMUM RATINGS

Rating

Symbol

Value

Unit

Collector–Emitter Voltage

V

CEO

400

Vdc

Collector–Emitter voltage

V

CEV

700

Vdc

Emitter Base Voltage

V

EB

6.0

Vdc

Collector Current — Continuous

Peak (1)

I

C

I

CM

20
30

Adc

Base Current — Continuous

Peak (1)

I

B

I

BM

10
15

Adc

Total Power Dissipation @ TC = 25_C

@ TC = 100_C

Derate above 25_C

P

D

175
100

1.0

Watts

W/_C

Operating and Storage Junction Temperature Range

TJ, T

stg

–65 to +200

_

C

THERMAL CHARACTERISTICS

Characteristic

Symbol

Max

Unit

Thermal Resistance, Junction to Case

R

θJC

1.0

_

C/W

Maximum Lead Temperature for Soldering Purposes 1/8″ from Case for 5 Seconds

T

L

275

_

C

(1) Pulse Test: Pulse Width = 5 ms, Duty Cycle v10%.

(1) Similar device types available with lower V

CEO

ratings, see the MJ13330 (200 V) and MJ13331 (250 V).

Designer’s and SWITCHMODE are trademarks of Motorola, Inc.
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit

curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.



SEMICONDUCTOR TECHNICAL DATA

Order this document

by MJ13333/D

 Motorola, Inc. 1995

20 AMPERE

NPN SILICON

POWER TRANSISTORS

400–500 VOLTS

175 WATTS



CASE 1–07

TO–204AA

(TO–3)

REV 1

MJ13333

2

Motorola Bipolar Power Transistor Device Data

ELECTRICAL CHARACTERISTICS (T

C

= 25_C unless otherwise noted)

Characteristic

Symbol

Min

Typ

Max

Unit

OFF CHARACTERISTICS

Collector–Emitter Sustaining Voltage (Table 1)

(IC = 100 mA, IB = 0)

V

CEO(sus)

400

—

—

Vdc

Collector Cutoff Current

(V

CEV

= Rated Value, V

BE(off)

= 1.5 Vdc)

(V

CEV

= Rated Value, V

BE(off)

= 1.5 Vdc, TC = 150_C)

I

CEV

—
—

—
—

0.25

5.0

mAdc

Collector Cutoff Current

(VCE = Rated V

CEV

, RBE = 50 Ω, TC = 100_C)

I

CER

—

—

5.0

mAdc

Emitter Cutoff Current

(VEB = 6.0 Vdc, IC = 0)

I

EBO

—

—

1.0

mAdc

SECOND BREAKDOWN

Second Breakdown Collector Current with base forward biased

I

S/b

See Figure 12

Clamped Inductive SOA with Base Reverse Biased

RBSOA

See Figure 13

ON CHARACTERISTICS (1)

DC Current Gain

(IC = 5.0 Adc, VCE = 5.0 Vdc)

h

FE

10

—

60

—

Collector–Emitter Saturation Voltage

(IC = 10 Adc, IB = 2.0 Adc)
(IC = 20 Adc, IB = 6.7 Adc)
(IC = 10 Adc, IB = 2.0 Adc, TC = 100_C)

V

CE(sat)

—
—
—

—
—
—

1.8

5.0

2.4

Vdc

Base Emitter Saturation Voltage

(IC = 10 Adc, IB = 2.0 Adc)
(IC = 10 Adc, IB = 2.0 Adc, TC = 100_C)

V

BE(sat)

—
—

—
—

1.8

1.8

Vdc

DYNAMIC CHARACTERISTICS

Output Capacitance

(VCB = 10 Vdc, IE = 0, f

test

= 1.0 kHz)

C

ob

125

—

500

pF

SWITCHING CHARACTERISTICS

Resistive Load (Table 1)

Delay Time

t

d

—

0.02

0.1

µs

Rise Time

t

r

—

0.3

0.7

µs

Storage Time

IB1 = 2.0 A, V

BE(off)

= 5.0 Vdc, tp = 10 µs,

Duty Cycle  2.0%)

t

s

—

1.6

4.0

µs

Fall Time



2.0%)

t

f

—

0.3

0.7

µs

Inductive Load, Clamped (Table 1)

Storage Time

C

= 10 A(pk), V

clamp

= 250 Vdc, IB1 = 2.0 A,

t

sv

—

2.5

5.0

µs

Crossover Time

(IC = 10 A(pk), V

clamp

= 250 Vdc, IB1 = 2.0 A,

V

BE(off)

= 5 Vdc, TC = 100°C)

t

c

—

0.8

2.0

µs

Storage Time

t

sv

—

1.8

—

µs

Crossover Time

(IC = 10 A(pk), V

clamp

= 250 Vdc, IB1 = 2.0 A,

V

= 5 Vdc, T

= 25_C)

t

c

—

0.4

—

µs

Fall Time

V

BE(off)

= 5 Vdc, TC = 25_C)

t

fi

—

0.2

—

µs

(1) Pulse Test: PW = 300 µs, Duty Cycle  2%.

(I

(VCC = 250 Vdc, IC = 10 A,

MJ13333

3

Motorola Bipolar Power Transistor Device Data

, COLLECTOR CURRENT ( A)

µ

I

C

V

CE

, COLLECTOR–EMITTER VOLTAGE (VOLTS)

V

CE

, COLLECTOR–EMITTER VOLTAGE (VOLTS)

0.20.2
IC, COLLECTOR CURRENT (AMP)

1.2

0

0.8

IC, COLLECTOR CURRENT (AMP)

0.4

100

Figure 1. DC Current Gain

IC, COLLECTOR CURRENT (AMPS)

5.0

0.2 0.5 1.0 2.0 20

50

20

Figure 2. Collector Saturation Region

0.01
IB, BASE CURRENT (AMP)

0

1.6

0.8

0.4

h

FE

, DC CURRENT GAIN

10

TJ = 150°C

Figure 3. Collector–Emitter Saturation Region

1.0 5.00.5

Figure 4. Base–Emitter Voltage

Figure 5. Collector Cutoff Region

2.0

1.2

–0.4

Figure 6. Capacitance

VBE, BASE–EMITTER VOLTAGE (VOLTS)

10

–1

–0.2 0 + 0.2 +0.4 +0.6

3000

0.1
VR, REVERSE VOLTAGE (VOLTS)

30

10

1000

10

0

100 1000

100

FORWARD

VCE = 250 V

10 A1 A

REVERSE

10

1

10

2

10

3

10

4

C

ib

VCE = 5 V

25°C

5.0 10 0.02 0.5 1.0 2.0 105.00.1 0.20.05

5000.5 1.0 5.0 50

50

200

700

2000

1.6

IC/IB = 5

2.0

20

2.0

1.2

0

0.8

0.4

1.6

150°C

10 1.0 5.00.5 2.0 2010

500

5 A

150°C

25°C

V

BE(sat)

, BASE–EMITTER SATURATION VOLTAGE (VOLTS)

2.0
IC/IB = 5

25°C

150°C

125°C

100°C

75°C

25°C

C, CAPACITANCE (pF)

C

ob

MJ13333

4

Motorola Bipolar Power Transistor Device Data

V

BE(off)

, REVERSE BASE VOLTAGE (VOLTS)

Figure 7. Inductive Switching Measurements

Figure 8. Reverse Base Current versus

V

BE(off)

With No External Base Resistance

2.0 5.0 10

10

7.0

2.0

, BASE CURRENT (AMP)I

B2(pk)

0

IC = 10 A
IB1 = 2 A
V

clamp

= 250 V

TJ = 25

°

C

5.0

t

rv

TIME

I

C

V

CE

90% I

B1

t

sv

IC pk

V

clamp

90% V

clamp

90% I

C

10% V

clamp

10%

IC pk

2% I

C

I

B

t

fi

t

ti

t

c

SWITCHING TIMES NOTE

In resistive switching circuits, rise, fall, and storage times
have been defined and a pply to both current and voltage
waveforms since they are in phase. However, for inductive
loads which are common to SWITCHMODE power supplies
and hammer drivers, current and voltage waveforms are not
in phase. Therefore, separate measurements must be made
on each waveform to determine the total switching time. For
this reason, the following new terms have been defined.

tsv = Voltage Storage Time, 90% IB1 to 10% V

clamp

trv = Voltage Rise Time, 10 – 90% V

clamp

tfi = Current Fall Time, 90 – 10% I

C

tti = Current Tail, 10 – 2% I

C

tc = Crossover Time, 10% V

clamp

to 10% I

C

An enlarged portion of the inductive switching waveforms
is shown in Figure 7 to aid in the visual identity of these
terms.

For the designer, there is minimal switching loss during
storage time and the predominant switching power losses
occur during the crossover interval and can be obtained us­ing the standard equation from AN–222:

P

SWT

= 1/2 VCCIC(tc)f

In general, trv + tfi ] tc. However, at lower test currents this
relationship may not be valid.

As is common with most switching transistors, resistive
switching is specified at 25°C and has become a benchmark
for designers, However, for designers of high frequency con­verter circuits, the user oriented specifications which make
this a “SWITCHMODE” transistor are the inductive switching
speeds (tc and tsv) which are guaranteed at 100°C.

20

Figure 9. Turn–On Switching Times

IC, COLLECTOR CURRENT (AMP)

0.2 0.5

0.02

Figure 10. Turn–Off Switching Times

2.0

1.0

0.1

0.05

20

IC, COLLECTOR CURRENT (AMP)

1.0

0.05

5.0

2.0

1.0

t, TIME ( s)

µ

0.5

5.02.0 10

t, TIME ( s)

µ

0.5

0.2

0.2

VCC = 250 V
IC/IB = 5

VCE = 250 V
IC/IB = 5
V

BE(off)

= 5 V

t

r

t

d

0.2 0.5 1.0 5.02.0 10

0.1

t

s

t

f

RESISTIVE SWITCHING PERFORMANCE

MJ13333

5

Motorola Bipolar Power Transistor Device Data

Table 1. Test Conditions for Dynamic Performance

V

CEO(sus)

RBSOA AND INDUCTIVE SWITCHING RESISTIVE SWITCHING

INPUT

CONDITIONS

CIRCUIT

VALUES

TEST CIRCUITS

20

1

0

PW Varied to Attain
IC = 100 mA

L

coil

= 80 mH, VCC = 10 V

R

coil

= 0.7 Ω

L

coil

= 180 µH

R

coil

= 0.05 Ω

VCC = 20 V

VCC = 250 V
RL = 50 Ω
Pulse Width = 10 µs

INDUCTIVE TEST CIRCUIT

TURN–ON TIME

IB1 adjusted to

obtain the forced

hFE desired

TURN–OFF TIME

Use inductive switching

driver as the input to

the resistive test circuit.

t1 Adjusted to
Obtain I

C

Test Equipment

Scope — Tektronix

475 or Equivalent

RESISTIVE TEST CIRCUITOUTPUT WAVEFORMS

2

I

B1

1
2

V

clamp

= 250 V

RB adjusted to attain desired I

B1

+10 V

250 µF

15 V

0

50

Ω

100

Ω

330

Ω

430

Ω

39

Ω

250 µF

–5.2

1
2

R2

5.1

Ω

5 W

47

Ω

470

Ω

2 W

+15 V

R1

All Diodes — 1N4934
All NPN — MJE200
All PNP — MJE210

Adjust R1 to obtain I

B1

For switching and RBSOA, R2 = 0
For V

CEO(sus)

, R2 = ∞

1

INPUT

2

R

coil

L

coil

V

CC

V

clamp

RS =

0.1

Ω

1N4937

OR

EQUIVALENT

TUT

SEE ABOVE FOR
DETAILED CONDITIONS

t

1

I

C

V

CE

I

C(pk)

tf Clamped

t

f

t

t

t

2

TIME

VCE

or

V

clamp

1
2

TUT

R

L

V

CC

t1 ≈

L

coil (IC

pk

)

V

CC

t2 ≈

L

coil (IC

pk

)

V

Clamp

t, TIME (ms)

1

0.01

0.01

0.5

0.2

0.1

0.05

0.02

r(t), EFFECTIVE TRANSIENT THERMAL

0.05 1 2 3 10 20 50 100 200 300

R

θ

JC

(t) = r(t) R

θ

JC

R

θ

JC

= 1.0

°

C/W MAX
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t

1

T

J(pk)

– TC = P

(pk)

R

θ

JC

(t)

P

(pk)

t

1

t

2

DUTY CYCLE, D = t1/t

2

D = 0.5

0.2

0.05

0.02

0.01

SINGLE PULSE

0.1

0.1 0.50.2

RESISTANCE (NORMALIZED)

500 1000

0.7

0.3

0.07

0.03

0.02 0.03 0.3 5 30

Figure 11. Thermal Response

MJ13333

6

Motorola Bipolar Power Transistor Device Data

I

C(pk)

, PEAK COLLECTOR CURRENT (AMPS)

0.005

Figure 12. Forward Bias Safe Operating Area

6

VCE, COLLECTOR–EMITTER VOLTAGE (VOLTS)

10 50

50

10

2
1

5

0.2

45020 100

Figure 13. RBSOA, Reverse Bias Switching

Safe Operating Area

VCE, COLLECTOR–EMITTER VOLTAGE (VOLTS)

0

100 200

16

8.0

20

300

IC/IB ≥ 5
V

BE(off)

= 5 V

TJ = 100

°

C

I

C

, COLLECTOR CURRENT (AMP)

0.05

200 350

12

4.0

0.1

0.02

400 500

dc

1 ms

10 µs

100 µs

400 500

600

600

20

0.01

MJ13333

BONDING WIRE LIMIT
THERMAL LIMIT @ TC = 25

°

C
(SINGLE PULSE)
SECOND BREAKDOWN LIMIT

SAFE OPERATING AREA INFORMATION

FORWARD BIAS

There are two limitations on the power handling ability of a
transistor average junction temperature and second break­down. Safe operating area curves indicate IC – VCE limits of
the transistor that must be observed for reliable operation,
i.e., the transistor must not be subjected to greater dissipa­tion than the curves indicate.

The data of Figure 12 is based on TC = 25_C. T

J(pk)

is
variable depending on power level. Second breakdown pulse
limits are valid for duty cycles to 10% but must be derated
when TC ≥ 25_C. Second breakdown limitations do not der­ate the same as thermal limitations. Allowable current at the
voltages shown on Figure 12 may be found at any case tem­perature by using the appropriate curve on Figure 14.

T

J(pk)

may be calculated from the data in Figure 1 1. At high
case temperatures, thermal limitations will reduce the power
that can be handled to values less than the limitations im­posed by second breakdown.

REVERSE BIAS

For inductive loads, high voltage and high current must be
sustained simultaneously during turn–off, in most cases, with
the base to e mitter junction reverse biased. Under these
conditions the collector voltage must be held to a safe level
at or below a specific value of collector current. This can be
accomplished by several means such as active clamping,
RC snubbing, load line shaping, etc. The safe level for these
devices is specified as Reverse Bias Safe Operating Area
and represents the voltage–current condition allowable dur­ing reverse biased turn–off. This rating is verified under
clamped conditions so that the device is never subjected to
an avalanche mode. Figure 13 gives the complete RBSOA
characteristics.

0

Figure 14. Power Derating

TC, CASE TEMPERATURE (°C)

0

40 80

80

40

100

120

POWER DERATING FACTOR (%)

160 200

60

20

THERMAL

DERATING

FORWARD BIAS
SECOND BREAKDOWN
DERATING

MJ13333

7

Motorola Bipolar Power Transistor Device Data

PACKAGE DIMENSIONS

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. ALL RULES AND NOTES ASSOCIATED WITH
REFERENCED TO–204AA OUTLINE SHALL APPLY.

STYLE 1:

PIN 1. BASE

2. EMITTER

CASE: COLLECTOR

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A 1.550 REF 39.37 REF
B ––– 1.050 ––– 26.67
C 0.250 0.335 6.35 8.51
D 0.038 0.043 0.97 1.09
E 0.055 0.070 1.40 1.77
G 0.430 BSC 10.92 BSC
H 0.215 BSC 5.46 BSC
K 0.440 0.480 11.18 12.19
L 0.665 BSC 16.89 BSC
N ––– 0.830 ––– 21.08
Q 0.151 0.165 3.84 4.19
U 1.187 BSC 30.15 BSC
V 0.131 0.188 3.33 4.77

A

N

E

C

K

–T–

SEATING
PLANE

2 PLD

M

Q

M

0.13 (0.005) Y

M

T

M

Y

M

0.13 (0.005) T

–Q–

–Y–

2

1

U

L

G

B

V

H

CASE 1–07

TO–204AA (TO–3)

ISSUE Z

MJ13333

8

Motorola Bipolar Power Transistor Device Data

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MJ13333/D

*MJ13333/D*

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