Page 1
Preliminary Spec.
DESCRIPTION
APPLICATION
Type name
6ns (CL = 2, 3)
MH8S72DBFD-7
Frequency
100MHz
6ns (CL = 3)
MH8S72DBFD-8
100MHz
[component level]
Some contents are subject to change without notice.
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
The MH8S72DBFD is 8388608 - word x 72-bit Synchronous
DRAM module. This consist of nine industry standard
8M x 8 Synchronous DRAMs in TSOP.
The TSOP on a card edge dual in-line package provides any
application where high densities and large of quantities memory
are required.
This is a socket-type memory module ,suitable for easy
interchange or addition of module.
FEATURES
Max.
CLK
Access Time
MITSUBISHI LSIs
MH8S72DBFD-7,-8
85pin
94pin
95pin
1pin
10pin
11pin
Utilizes industry standard 8M X 8 Synchronous DRAMs in
TSOP package , industry standard Resistered buffer in TSSOP
package and industry standard PLL in TSSOP package
Single 3.3V +/- 0.3V supply
LVTTL Interface
Burst length 1/2/4/8/Full Page(programmable)
Burst Write / Single Write(programmable)
Auto precharge / All bank precharge controlled by A10
Auto refresh and Self refresh
4096 refresh cycles every 64ms
Discrete IC and module design conform to
PC/100 specification.
(module Spec. Rev. 1.2 and SPD 1.2A)
Main memory or graphic memory in computer systems
124pin
125pin
168pin
40pin
41pin
84pin
MIT-DS-0351-0.0
MITSUBISHI
ELECTRIC
30/Sep. /1999
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Page 2
Preliminary Spec.
/WE
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S72DBFD-7,-8
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
PIN NO. PIN NAME PIN NO. PIN NAME PIN NO. PIN NAME PIN NO. PIN NAME
1
2 DQ0 44 NC
3 DQ1 45 /S2
4 DQ2 46 DQMB2
5 DQ3 47 DQMB3
6 VDD 48 NC
7 DQ4 49 VDD
8 DQ5 50 NC
9 DQ6 51 NC
10 DQ7 52
11 DQ8 53
12
13 DQ9 55 DQ16
14 DQ10 56 DQ17
15 DQ11 57 DQ18
16 DQ12 58 DQ19
17 DQ13 59 VDD
18 VDD 60 DQ20
19 DQ14 61 NC
20 DQ15 62
21
22
23 VSS 65 DQ21
24 NC 66 DQ22
25 NC 67 DQ23
26 VDD 68
27
28 DQMB0 70 DQ25
29 DQMB1 71 DQ26
30 /S0 72 DQ27
31 NC 73 VDD
32 VSS 74 DQ28
33 A0 75 DQ29
34 A2 76 DQ30
35 A4 77 DQ31
36 A6 78 VSS
37 A8 79
38
39
40 VDD 82 SDA
41 VDD 83 SCL
42 CK0 84 VDD
VSS
VSS
CB0
CB1
A10
BA1
43
54 VSS
63
64 VSS
69 DQ24
80 NC
81
VSS 85
CB2
CB3
100
101
102
103
NC
CKE1
VSS 110
CK2
WP
104
105
106
107
108
109
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
86
87
88
89
90
91
92
93
94
95
96
97
98
99
VSS 127
DQ32 128
DQ33 129
DQ34 130 DQMB6
DQ35 131 DQMB7
VDD 132
DQ36 133 VDD
DQ37 134 NC
DQ38 135 NC
DQ39 136
DQ40 137
VSS 138 VSS
DQ41 139 DQ48
DQ42 140 DQ49
DQ43 141 DQ50
DQ44 142 DQ51
DQ45 143 VDD
VDD 144 DQ52
DQ46 145 NC
DQ47 146
CB4
CB5
VSS 149 DQ53
NC 150 DQ54
NC 151 DQ55
VDD 152 VSS
/CAS 153 DQ56
DQMB4 154 DQ57
DQMB5 155 DQ58
NC
/RAS 157 VDD
VSS 158 DQ60
A1 159 DQ61
A3 160 DQ62
A5 161 DQ63
A7 162 VSS
A9 163
BA0
A11
VDD 166 SA1
CK1 167 SA2
NC
147
148 VSS
156 DQ59
164 NC
165 SA0
168 VDD
VSS
CKE0
NC
NC
CB6
CB7
NC
REGE
CK3
NC = No Connection
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ELECTRIC
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Preliminary Spec.
D0
R/S0,2
RDQM 0
RDQM 1
RDQM 4
RDQM 3
RDQM 2
RDQM 7
RDQM 5
RDQM 6
D4D6D7
D8D5D2
D3
D1
Some contents are subject to change without notice.
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
MITSUBISHI LSIs
MH8S72DBFD-7,-8
Add
CKE0
/S0,2
DQM0-7
/W
/RAS
/CAS
10K
VDD
From PLL
CK0
CK1 - CK3
RCKE0
R/S0
R/S2
REGE
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
PLL
Terminated
D0-8
D0-2,5-6
D3-4,7-8
RCKE0
RDQM0-7
D0
D1-2
D3
D4
D5
D6
D7
D8
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
SCL
WP
47K
VDD
VSS
SERIAL PD
A0 A1 A2
SA0 SA1 SA2
SDA
D0 to D8
D0 to D8
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Preliminary Spec.
CKE0
Register enable:When REGE is low,All control signals and
Some contents are subject to change without notice.
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
PIN FUNCTION
MITSUBISHI LSIs
MH8S72DBFD-7,-8
CK0
/S0,2
/RAS,/CAS,/W
A0-11
Input
Input
Input
Input
Input
Master Clock:All other inputs are referenced to the rising
edge of CK
Clock Enable:CKE controls internal clock.When CKE is
low,internal clock for the following cycle is ceased. CKE is
also used to select auto / self refresh. After self refresh
mode is started, CKE E becomes asynchronous input.Self
refresh is maintained as long as CKE is low.
Chip Select: When /S is high,any command means
No Operation.
Combination of /RAS,/CAS,/W defines basic
commands.
A0-11 specify the Row/Column Address in conjunction with
BA.The Row Address is specified by A0-11.The Column
Address is specified by A0-8.A10 is also used to indicate
precharge option.When A10 is high at a read / write
command, an auto precharge is performed. When A10 is
BA0-1
DQ0-63
CB0-7
DQM0-7
Vdd,Vss
REGE
Input
Input/Output
Input
Power Supply
Input
high at a precharge command, both banks are precharged.
Bank Address:BA0,1 is specifies the four bank to which
a command is applied.BA must be set with ACT ,PRE
,READ ,WRITE commands
Data In and Data out are referenced to the rising edge
of CK
Din Mask/Output Disable:When DQMB is high in burst
write.Din for the current cycle is masked.When DQMB is high
in burst read,Dout is disabled at the next but one cycle.
Power Supply for the memory mounted
module.
address are buffered. (Buffer mode) When REGE is
high,All control and address are latched. (Latch mode)
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Preliminary Spec.
READ command starts burst read from the active bank indicated by BA.First output
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S72DBFD-7,-8
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
BASIC FUNCTIONS
The MH8S72DBFD provides basic functions,bank(row)activate,burst read / write,
bank(row)precharge,and auto / self refresh.
Each command is defined by control signals of /RAS,/CAS and /WE at CK rising edge. In
addition to 3 signals,/S,CKE and A10 are used as chip select,refresh option,and precharge
option,respectively.
To know the detailed definition of commands please see the command truth table.
CK
/S
/RAS
/CAS
/WE
CKE
Chip Select : L=select, H=deselect
Command
Command
Command
Refresh Option @refresh command
define basic commands
A10
Precharge Option @precharge or read/write command
Activate(ACT) [/RAS =L, /CAS = /WE =H]
ACT command activates a row in an idle bank indicated by BA.
Read(READ) [/RAS =H,/CAS =L, /WE =H]
data appears after /CAS latency. When A10 =H at this command,the bank is
deactivated after the burst read(auto-precharge,READA).
Write(WRITE) [/RAS =H, /CAS = /WE =L]
WRITE command starts burst write to the active bank indicated by BA. Total data
length to be written is set by burst length. When A10 =H at this command, the bank
is deactivated after the burst write(auto-precharge,WRITEA).
Precharge(PRE) [/RAS =L, /CAS =H,/WE =L]
PRE command deactivates the active bank indicated by BA. This command also
terminates burst read / write operation. When A10 =H at this command, both banks
are deactivated(precharge all, PREA).
Auto-Refresh(REFA) [/RAS =/CAS =L, /WE =CKE =H]
PEFA command starts auto-refresh cycle. Refresh address including bank address
are generated internally. After this command, the banks are precharged automatically.
MIT-DS-0351-0.0
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ELECTRIC
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Preliminary Spec.
& Read
Some contents are subject to change without notice.
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
COMMAND TRUTH TABLE
MITSUBISHI LSIs
MH8S72DBFD-7,-8
COMMAND MNEMONIC
Deselect DESEL H X H X X X X X X
No Operation NOP H X L H H H X X X
Row Adress Entry &
Bank Activate
Single Bank Precharge PRE H X L L H L V L X
Precharge All Bank PREA H X L L H L X H X
Column Address Entry
& Write
Column Address Entry
& Write with Auto-
Precharge
Column Address Entry
Column Address Entry
& Read with Auto
Precharge
Auto-Refresh REFA H H L L L H X X X
Self-Refresh Entry REFS H L L L L H X X X
Self-Refresh Exit REFSX
Burst Terminate TBST H X L H H L X X X
Mode Register Set MRS H X L L L L L L V*1
ACT H X L L H H V V V
WRITE H X L H L L V L V
WRITEA H X L H L L V H V
READ H X L H L H V L V
READA H X L H L H V H V
CKE
CKE
n-1
L H H X X X X X X
L H L H H H X X X
n
/RAS /CAS /WE BA0,1 A10 A0-9
/S
A11
X
X
V
X
X
X
X
X
X
X
X
X
X
X
L
H =High Level, L = Low Level, V = Valid, X = Don't Care, n = CK cycle number
NOTE:
1.A7-9 = 0, A0-6 = Mode Address
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Preliminary Spec.
Action
Begin Write,Latch CA,
Terminate Burst,Latch CA,
Terminate Burst,Latch CA,
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S72DBFD-7,-8
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
FUNCTION TRUTH TABLE
Current State /S /RAS /CAS /WE Address Command
IDLE H X X X X DESEL NOP
L H H H X NOP NOP
L H H L BA TBST ILLEGAL*2
L H L X BA,CA,A10 READ/WRITE ILLEGAL*2
L L H H BA,RA ACT Bank Active,Latch RA
L L H L BA,A10 PRE/PREA NOP*4
L L L H X REFA Auto-Refresh*5
L L L L
ROW ACTIVE H X X X X DESEL NOP
L H H H X NOP NOP
L H H L BA TBST NOP
L H L H BA,CA,A10 READ/READA
L H L L BA,CA,A10
L L H H BA,RA ACT Bank Active/ILLEGAL*2
L L H L BA,A10 PRE/PREA Precharge/Precharge All
L L L H X REFA ILLEGAL
L L L L
READ H X X X X DESEL NOP(Continue Burst to END)
L H H H X NOP NOP(Continue Burst to END)
L H H L BA TBST Terminate Burst
Op-Code,
Mode-Add
Op-Code,
Mode-Add
MRS Mode Register Set*5
Begin Read,Latch CA,
Determine Auto-Precharge
WRITE/
WRITEA
MRS ILLEGAL
Determine Auto-Precharge
MIT-DS-0351-0.0
L H L H BA,CA,A10 READ/READA
L H L L BA,CA,A10 WRITE/WRITEA
L L H H BA,RA ACT Bank Active/ILLEGAL*2
L L H L BA,A10 PRE/PREA Terminate Burst,Precharge
L L L H X REFA ILLEGAL
L L L L
Op-Code,
Mode-Add
MRS ILLEGAL
MITSUBISHI
Begin New Read,Determine
Auto-Precharge*3
Begin Write,Determine AutoPrecharge*3
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ELECTRIC
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Preliminary Spec.
Terminate Burst,Latch CA,
Terminate Burst,Latch CA,
Op-Code,
Op-Code,
Op-Code,
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S72DBFD-7,-8
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
FUNCTION TRUTH TABLE(continued)
Current State /S /RAS /CAS /WE Address Command Action
WRITE
H X X X X DESEL NOP(Continue Burst to END)
L H H H X NOP NOP(Continue Burst to END)
L H H L BA TBST Terminate Burst
READ with
AUTO
PRECHARGE
L H L H BA,CA,A10 READ/READA
L H L L BA,CA,A10
L L H H BA,RA ACT Bank Active/ILLEGAL*2
L L H L BA,A10 PRE/PREA Terminate Burst,Precharge
L L L H X REFA ILLEGAL
L L L L
H X X X X DESEL NOP(Continue Burst to END)
L H H H X NOP NOP(Continue Burst to END)
L H H L BA TBST ILLEGAL
L H L H BA,CA,A10 READ/READA ILLEGAL
L H L L BA,CA,A10
L L H H BA,RA ACT Bank Active/ILLEGAL*2
L L H L BA,A10 PRE/PREA ILLEGAL*2
L L L H X REFA ILLEGAL
Mode-Add
WRITE/
WRITEA
MRS ILLEGAL
WRITE/
WRITEA
Begin Read,Determine AutoPrecharge*3
Begin Write,Determine AutoPrecharge*3
ILLEGAL
WRITE with
AUTO
PRECHARGE
MIT-DS-0351-0.0
L L L L
H X X X X DESEL NOP(Continue Burst to END)
L H H H X NOP NOP(Continue Burst to END)
L H H L BA TBST ILLEGAL
L H L H BA,CA,A10 READ/READA ILLEGAL
L H L L BA,CA,A10
L L H H BA,RA ACT Bank Active/ILLEGAL*2
L L H L BA,A10 PRE/PREA ILLEGAL*2
L L L H X REFA ILLEGAL
L L L L
Mode-Add
Mode-Add
MITSUBISHI
MRS ILLEGAL
WRITE/
WRITEA
MRS ILLEGAL
ILLEGAL
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Preliminary Spec.
Action
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S72DBFD-7,-8
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
FUNCTION TRUTH TABLE(continued)
Current State /S /RAS /CAS /WE Address Command
PRE - H X X X X DESEL NOP(Idle after tRP)
CHARGING L H H H X NOP NOP(Idle after tRP)
L H H L BA TBST ILLEGAL*2
L H L X BA,CA,A10 READ/WRITE ILLEGAL*2
L L H H BA,RA ACT ILLEGAL*2
L L H L BA,A10 PRE/PREA NOP*4(Idle after tRP)
L L L H X REFA ILLEGAL
L L L L
ROW H X X X X DESEL NOP(Row Active after tRCD
ACTIVATING L H H H X NOP NOP(Row Active after tRCD
L H H L BA TBST ILLEGAL*2
L H L X BA,CA,A10 READ/WRITE ILLEGAL*2
L L H H BA,RA ACT ILLEGAL*2
L L H L BA,A10 PRE/PREA ILLEGAL*2
L L L H X REFA ILLEGAL
L L L L
WRITE RE- H X X X X DESEL NOP
COVERING L H H H X NOP NOP
L H H L BA TBST ILLEGAL*2
L H L X BA,CA,A10 READ/WRITE ILLEGAL*2
L L H H BA,RA ACT ILLEGAL*2
L L H L BA,A10 PRE/PREA ILLEGAL*2
L L L H X REFA ILLEGAL
L L L L
Op-Code,
Mode-Add
Op-Code,
Mode-Add
Op-Code,
Mode-Add
MRS ILLEGAL
MRS ILLEGAL
MRS ILLEGAL
MIT-DS-0351-0.0
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ELECTRIC
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Preliminary Spec.
Op-Code,
Op-Code,
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S72DBFD-7,-8
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
FUNCTION TRUTH TABLE(continued)
Current State /S /RAS /CAS /WE Address Command Action
RE- H X X X X DESEL NOP(Idle after tRC)
FRESHING L H H H X NOP
L H H L BA TBST ILLEGAL
L H L X BA,CA,A10 READ/WRITE ILLEGAL
L L H H BA,RA ACT ILLEGAL
L L H L BA,A10 PRE/PREA ILLEGAL
L L L H X REFA ILLEGAL
L L L L
Mode-Add
MODE H X X X X DESEL NOP(Idle after tRSC)
REGISTER L H H H X NOP NOP(Idle after tRSC)
SETTING L H H L BA TBST ILLEGAL
L H L X BA,CA,A10 READ/WRITE ILLEGAL
L L H H BA,RA ACT ILLEGAL
L L H L BA,A10 PRE/PREA ILLEGAL
L L L H X REFA ILLEGAL
L L L L
Mode-Add
MRS ILLEGAL
MRS ILLEGAL
NOP(Idle after tRC)
ABBREVIATIONS:
H = Hige Level, L = Low Level, X = Don't Care
BA = Bank Address, RA = Row Address, CA = Column Address, NOP = No Operation
NOTES:
1. All entries assume that CKE was High during the preceding clock cycle and the current
clock cycle.
2. ILLEGAL to bank in specified state; function may be legal in the bank indicated by BA,
depending on the state of that bank.
3. Must satisfy bus contention, bus turn around, write recovery requirements.
4. NOP to bank precharging or in idle state.May precharge bank indicated by BA.
5. ILLEGAL if any bank is not idle.
ILLEGAL = Device operation and / or date-integrity are not guaranteed.
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Preliminary Spec.
Action
2. Power-Down and Self-Refresh can be entered only form the All banks idle State.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S72DBFD-7,-8
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
FUNCTION TRUTH TABLE FOR CKE
CKE
Current State
SELF - H X X X X X X INVALID
REFRESH*1 L H H X X X X Exit Self-Refresh(Idle after tRC)
CKE
n-1
L H L H H H X Exit Self-Refresh(Idle after tRC)
L H L H H L X ILLEGAL
L H L H L X X ILLEGAL
L H L L X X X ILLEGAL
L L X X X X X NOP(Maintain Self-Refresh)
n
/RAS /CAS /WE Add
/S
POWER H X X X X X X INVALID
DOWN L H X X X X X Exit Power Down to Idle
L L X X X X X NOP(Maintain Self-Refresh)
ALL BANKS H H X X X X X Refer to Function Truth Table
IDLE*2 H L L L L H X Enter Self-Refresh
H L H X X X X Enter Power Down
H L L H H H X Enter Power Down
H L L H H L X ILLEGAL
H L L H L X X ILLEGAL
H L L L X X X ILLEGAL
L X X X X X X Refer to Current State = Power Down
ANY STATE H H X X X X X Refer to Function Truth Table
other than H L X X X X X Begin CK0 Suspend at Next Cycle*3
listed above L H X X X X X Exit CK0 Suspend at Next Cycle*3
L L X X X X X Maintain CK0 Suspend
ABBREVIATIONS:
H = High Level, L = Low Level, X = Don't Care
NOTES:
1. CKE Low to High transition will re-enable CK and other inputs asynchronously.
A minimum setup time must be satisfied before any command other than EXIT.
3. Must be legal command.
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Preliminary Spec.
POWER ON SEQUENCE
1. Clock will be applied at power up along with power. Attempt to maintain CKE high, DQMB
MODE REGISTER
LENGTH
BURST
LATENCY
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S72DBFD-7,-8
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Before starting normal operation, the following power on sequence is necessary to prevent
a SDRAM from damaged or malfunctioning.
high and NOP condition at the inputs along with power.
2. Maintain stable power, stable cock, and NOP input conditions for a minimum of 200µs.
3. Issue precharge commands for all banks. (PRE or PREA)
4. After all banks become idle state (after tRP), issue 8 or more auto-refresh commands.
5. Issue a mode register set command to initialize the mode register.
After these sequence, the SDRAM is idle state and ready for normal operation.
Burst Length, Burst Type and /CAS Latency can be programmed by setting the mode
register(MRS). The mode register stores these date until the next MRS command, which
may be issue when both banks are in idle state. After tRSC from a MRS command, the
SDRAM is ready for new command.
CK
/S
/RAS
/CAS
/WE
BT= 0 BT= 1
1
2
4
8
R
R
R
FP
SEQUENTIAL
INTERLEAVED
V
1
2
4
8
R
R
R
R
MODE
00
CL
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0BA1BA0
0 0 WM 0 0
/CAS LATENCY
R
R
2
3
R
R
R
R
LTMODE BT BL
BURST
TYPE
BA0,1 A11-0
BL
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
0
1
0
WRITE
MODE
MIT-DS-0351-0.0
1
BURST
SINGLE BIT
R:Reserved for Future Use
FP: Full Page
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Preliminary Spec.
Write
Burst Type
Some contents are subject to change without notice.
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
CK
Command
Read
MITSUBISHI LSIs
MH8S72DBFD-7,-8
Address
DQ
Initial Address
A2 A1 A0
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
CL= 3
BL= 4
BL
8
Y
Q0 Q1 Q2 Q3
/CAS
Latency
Sequential Interleaved
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
1 2 3 4 5 6 7 0 1 0 3 2 5 4 7 6
2 3 4 5 6 7 0 1 2 3 0 1 6 7 4 5
3 4 5 6 7 0 1 2 3 2 1 0 7 6 5 4
4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3
Burst
Length
Column Addressing
Y
D0 D1
Burst
Length
D2
D3
1 0 1
1 1 0
1 1 1
- 0 0
- 0 1
- 1 0
- 1 1
- - 0
- - 1
MIT-DS-0351-0.0
5 6 7 0 1 2 3 4 5 4 7 6 1 0 3 2
6 7 0 1 2 3 4 5 6 7 4 5 2 3 0 1
7 0 1 2
0 1 2 3
1 2 3 0
4
2 3 0 1
3 0
0 1
2
1 0
3 4 5 6 3 2 1 0
1 2
7 6 5 4
0 1 2 3
1 0 3 2
2 3 0 1
3 2
0 1
1 0
1 0
MITSUBISHI
ELECTRIC
30/Sep. /1999
13
Page 14
Preliminary Spec.
ABSOLUTE MAXIMUM RATINGS
Parameter
mA
RECOMMENDED OPERATING CONDITION
(Ta=0 ~ 70C, unless otherwise noted)
Parameter
CAPACITANCE
Parameter
f=1MHz
Some contents are subject to change without notice.
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
MITSUBISHI LSIs
MH8S72DBFD-7,-8
Symbol
Vdd
VI
VO
IO
Pd
Topr
Tstg
Symbol
Supply Voltage
Input Voltage
Output Voltage
Output Current
Power Dissipation
Operating Temperature
Storage Temperature
Condition Ratings Unit
with respect to Vss
with respect to Vss
with respect to Vss
Ta=25C
Limits
Min. Typ. Max.
-0.5 ~ 4.6
-0.5 ~ 4.6
-0.5 ~ 4.6
50
12
0 ~ 70
-40 ~ 100
V
V
V
W
C
C
Unit
Vdd
Vss
VIH*1
VIL*2
Note)
1:VIH(max)=5.5V for pulse width less than 10ns.
2.VIL(min)=-1.0 for pulse width less than 10ns.
(Ta=0 ~ 70C, Vdd = 3.3 +/- 0.3V, Vss = 0V, unless otherwise noted)
Symbol
CI(A)
CI(C)
CI(K)
CI/O
High-Level Input Voltage all inputs
Low-Level Input Voltage all inputs
Input Capacitance, address pin
Input Capacitance, control pin
Input Capacitance, CK0 pin
Input Capacitance, I/O pin
Supply Voltage
Supply Voltage
3.0
0
2.0
-0.3
Test Condition Limits(max.) Unit
VI = Vss
Vi=25mVrms
3.3
0
Vdd+0.3
20
20
20
22
3.6
0
0.8
V
V
V
V
pF
pF
pF
pF
MIT-DS-0351-0.0
MITSUBISHI
ELECTRIC
30/Sep. /1999
14
Page 15
Preliminary Spec.
AVERAGE SUPPLY CURRENT from Vdd
AC OPERATING CONDITIONS AND CHARACTERISTICS
Limits
Unit
IOH=-2mA
Limits
(max)
precharge stanby
in power-down mode
precharge stanby current
in non power-down mode
active stanby current
one bank active (discrete)
Some contents are subject to change without notice.
MH8S72DBFD-7,-8
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
(Ta=0 ~70C, Vdd = 3.3 ± 0.3V, Vss = 0V, unless otherwise noted)
MITSUBISHI LSIs
Parameter
operating current
one bank active (discrete)
current
in non power-down mode
burst current
auto-refresh current
self-refresh current
Note)
1.Icc(max) is specified at the output open condition.
2.Input signal are changed one time during 30ns.
Symbol
Icc1
Icc2P
Icc2PS
Icc2N
Icc2NS
Icc3N
Icc3NS
Icc4
Icc5
Icc6
tRC=min.tCLK=min, BL=1,CL=3
CKE=L,tCLK=15ns, /CS>Vcc-0.2V
CKE=CLK=L, /CS>Vcc-0.2V
CKE=H,tCLK=15ns,VIH>Vcc-0.2V,VIL<0.2V
CKE=H,CLK=L,VIH>Vcc-0.2V,VIL<0.2V(fixed)
CKE=H,tCLK=15ns
CKE=H,CLK=L
tCLK=min, BL=4, CL=3,all banks active(discerte)
tRC=min, tCLK=min
CKE <0.2V
Test Condition
-7,8
655
43
34
205
160
295
250
655
1015
34
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
(Ta=0 ~ 70C, Vdd = 3.3 ± 0.3V, Vss = 0V, unless otherwise noted)
Symbol Parameter Test Condition
VOH(DC) High-Level Output Voltage(DC)
VOL(DC) Low-Level Output Voltage(DC) IOL=2mA
IOZ Off-stare Output Current Q floating VO=0 ~ Vdd
Ii Input Current VIH=0 ~ Vdd+0.3V -10 10 uA
MIT-DS-0351-0.0
MITSUBISHI
Min. Max.
2.4 V
-10
ELECTRIC
0.4 V
uA
10
30/Sep. /1999
15
Page 16
Preliminary Spec.
AC TIMING REQUIREMENTS
Note:1 The timing requirements are assumed tT=1ns.If tT is longer than 1ns,(tT-1)ns
should be added to the parameter.
tSRX
Some contents are subject to change without notice.
MH8S72DBFD-7,-8
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
(Ta=0 ~ 70C, Vdd = 3.3 +/- 0.3V, Vss = 0V, unless otherwise noted)
Input Pulse Levels: 0.8V to 2.0V
Input Timing Measurement Level: 1.4V
LATCH MODE
Limits
Symbol
tCLK
tCH
tCL
tT
tIS
tIH
tRC
tRCD
tRAS
tRP
tWR
tRRD
tRSC
tPDE
tREF
Parameter
CK cycle time
CL=3
CL=4
CK High pulse width
CK Low pilse width
Transition time of CK
Input Setup time(all inputs)
Input Hold time(all inputs)
Row cycle time
Row to Column Delay
Row Active time
Row Precharge time
Write Recovery time
Act to Act Deley time
Mode Register Set Cycle time
Self Refresh Exit time
Power Down Exit time
Refresh Interval time
Min.
-7
Max.
10
10
3
3 ns
1
2 ns
1 ns
70
20
50 100000
20
20
20 ns
10
10
10
10
64
Min.
13
10 ns
3
3
1
2
1
70
20
50
20
20
20
10
10
10
MITSUBISHI LSIs
-8
Unit
Max.
ns
ns
10
ns
ns
ns
100000
ns
ns
ns
ns
ns
ns
64
ms
CK
1.4V
Any AC timing is
referenced to the input
signal crossing
Signal
MIT-DS-0351-0.0
1.4V
MITSUBISHI
through 1.4V.
30/Sep. /1999
ELECTRIC
16
Page 17
Preliminary Spec.
tSRX
Some contents are subject to change without notice.
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
BUFFER MODE
Symbol
tCLK
tCH
tCL
tT
tIS
tIH
tRC
tRCD
tRAS
tRP
tWR
tRRD
tRSC
tPDE
tREF
Parameter
CK cycle time
CL=2
CL=3
CK High pulse width
CK Low pilse width
Transition time of CK
Input Setup time(all inputs)
Input Hold time(all inputs)
Row cycle time
Row to Column Delay
Row Active time
Row Precharge time
Write Recovery time
Act to Act Deley time
Mode Register Set Cycle time
Self Refresh Exit time
Power Down Exit time
Refresh Interval time
MITSUBISHI LSIs
MH8S72DBFD-7,-8
Limits
-7
Min.
10
10
3
3 ns
1
7 ns
0
70
20
50 100000
20
20 ns
20 ns
10
10
10
Max.
10
64
Min.
-8
Max.
13
10 ns
3
3
1
7
0
70
20
50
20
20
20
10
10
10
10
100000
64
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
Note:1 The timing requirements are assumed tT=1ns. If tT is longer than 1ns, (tT-1)ns
should be added to the parameter.
SWITCHING CHARACTERISTICS
(Ta=0 ~ 70°C, Vdd = 3.3 +/- 0.3V, Vss = 0V, unless otherwise noted)
LATCH MODE
Limits
Min.
-7
Max.
6
6
Symbol
tAC
Parameter
Access time from CK
CL=3
CL=4
Output Hold time
tOH
from CK
Delay time, output low
tOLZ
impedance from CK
Delay time, output high
tOHZ
Note)
1 If clock rising time is longer than 1ns,(tT/2-0.5)ns should be added to parameter.
impedance from CK
3
0
3
6
Min.
3
0
3
-8
Max.
7
6
6
Unit
ns
ns
ns
ns
MIT-DS-0351-0.0
MITSUBISHI
ELECTRIC
30/Sep. /1999
17
Page 18
Preliminary Spec.
1.4V
1.4V
Some contents are subject to change without notice.
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
BUFFER MODE
Symbol
tAC
Parameter
Access time from CK
CL=2
CL=3
MITSUBISHI LSIs
MH8S72DBFD-7,-8
Limits
Unit
Min.
-7
Max.
6
6
Min.
-8
Max.
7
6
ns
tOH
from CK
Delay time, output low
tOLZ
impedance from CK
Delay time, output high
tOHZ
Note)
1 If clock rising time is longer than 1ns,(tT/2-0.5)ns should be added to parameter.
impedance from CK
3
0
3
6
Output Load Condition
Output Hold time
VTT=1.4V
50½
VOUT
50pF
CK
DQ
Output Timing
Measurement
Reference Point
3
0
3
6
ns
ns
ns
1.4V
1.4V
MIT-DS-0351-0.0
CK
DQ
tAC
tOH
tOHZ
MITSUBISHI
ELECTRIC
30/Sep. /1999
18
Page 19
Preliminary Spec.
WRITE#0
Some contents are subject to change without notice.
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Burst WRITE (single bank)
BL=4,Buffer mode(REGE="L")
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK
tRC
/CS
MITSUBISHI LSIs
MH8S72DBFD-7,-8
/RAS
/CAS
/WE
CKE
DQM
A0-9
A10
tRAS
tRCD
tWR
X
X
Y
tRP
tRCD
X
X
Y
A11
BA0,1
REGE
DQ
MIT-DS-0351-0.0
X
0
ACT#0 WRITE#0 PRE#0 ACT#0
0 0
D0 D0 D0 D0
X
0
Italic parameter indicates minimum case
MITSUBISHI
ELECTRIC
0
D0 D0 D0 D0
30/Sep. /1999
19
Page 20
Preliminary Spec.
WRITE#0
WRITE#0
WRITE#1
Some contents are subject to change without notice.
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Burst WRITE (multi bank)
BL=4,Buffer mode(REGE="L")
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK
tRC
/CS
tRRD
tRAS
/RAS
MITSUBISHI LSIs
MH8S72DBFD-7,-8
tRRD
tRP
/CAS
/WE
CKE
DQM
A0-9
A10
A11
tRCD
tWR
X
X
X
Y
X
X
X
Y
tWR
tRCD
X
X
X
Y
X
X
X
BA0,1
REGE
DQ
MIT-DS-0351-0.0
0
ACT#0
0 1
1
D0 D0 D0 D0
ACT#1
0
D1 D1 D1 D1
PRE#0 ACT#0
Italic parameter indicates minimum case
MITSUBISHI
ELECTRIC
0
1
2
ACT#2
PRE#1
0
D0 D0 D0 D0
30/Sep. /1999
20
Page 21
Preliminary Spec.
WRITE#0
Some contents are subject to change without notice.
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Burst WRITE (single bank)
BL=4,Lacth mode(REGE="H")
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK
tRC
/CS
MITSUBISHI LSIs
MH8S72DBFD-7,-8
/RAS
/CAS
/WE
CKE
DQM
A0-9
A10
tRAS
tRCD
tWR
X
X
Y
tRP
tRCD
X
X
Y
A11
BA0,1
REGE
DQ
MIT-DS-0351-0.0
X
0
ACT#0 WRITE#0 PRE#0 ACT#0
0 0
D0 D0 D0 D0
X
0
Italic parameter indicates minimum case
MITSUBISHI
ELECTRIC
0
D0 D0 D0 D0
30/Sep. /1999
21
Page 22
Preliminary Spec.
WRITE#0
WRITE#0
WRITE#1
Some contents are subject to change without notice.
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Burst WRITE (multi bank)
BL=4,Latch mode(REGE="H")
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK
tRC
/CS
tRRD
tRAS
/RAS
MITSUBISHI LSIs
MH8S72DBFD-7,-8
tRRD
tRP
/CAS
/WE
CKE
DQM
A0-9
A10
A11
tRCD
tWR
X
X
X
Y
X
X
X
Y
tWR
tRCD
X
X
X
Y
X
X
X
BA0,1
REGE
DQ
ACT#0
MIT-DS-0351-0.0
0
0 1
1
D0 D0 D0 D0
ACT#1
0
D1 D1 D1 D1
PRE#0 ACT#0
Italic parameter indicates minimum case
MITSUBISHI
0
1
2
ACT#2
PRE#1
0
D0 D0 D0
30/Sep. /1999
22
ELECTRIC
Page 23
Preliminary Spec.
READ#0
Some contents are subject to change without notice.
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Burst READ (single bank)
BL=4,CL=3,Buffer mode(REGE="L")
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK
tRC
/CS
tRAS tRP
/RAS
MITSUBISHI LSIs
MH8S72DBFD-7,-8
/CAS
/WE
CKE
DQM
A0-9
A10
A11
tRCD
DQM read latency =2
X
X
X
Y
tRCD
X
X
X
Y
BA0,1
REGE
DQ
MIT-DS-0351-0.0
0
ACT#0
0 0
CL=3
Q0 Q0 Q0 Q0
PRE#0 ACT#0 READ#0
READ to PRE ³BL allows full data out
0
Italic parameter indicates minimum case
MITSUBISHI
ELECTRIC
0
Q0 Q0
30/Sep. /1999
23
Page 24
Preliminary Spec.
READ#0
READ#0
Some contents are subject to change without notice.
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Burst READ (multi bank)
BL=4,CL=3,Buffer mode(REGE="L")
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK
tRC
/CS
tRRD
tRAS tRP
/RAS
MITSUBISHI LSIs
MH8S72DBFD-7,-8
tRRD
/CAS
/WE
CKE
DQM
A0-9
A10
A11
tRCD
DQM read latency =2
X
X
X
Y
X
X
X
Y
tRCD
X
X
X
Y
X
X
X
BA0,1
0
REGE
DQ
ACT#0
MIT-DS-0351-0.0
0 0
1
CL=3
ACT#1
1
CL=3
Q0 Q0 Q0 Q0
PRE#0 ACT#0
READ#1 PRE#1 ACT#2
Italic parameter indicates minimum case
0
Q1 Q1 Q1 Q1
MITSUBISHI
ELECTRIC
0
21
30/Sep. /1999
Q0
24
Page 25
Preliminary Spec.
READ#0
READ#0
Some contents are subject to change without notice.
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Burst READ (single bank)
BL=4, CL=4,Latch mode(REGE="H")
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK
tRC
/CS
tRAS tRP
/RAS
MITSUBISHI LSIs
MH8S72DBFD-7,-8
/CAS
/WE
CKE
DQM
A0-9
A10
A11
tRCD
DQM read latency =3
X
X
X
Y
tRCD
X
X
X
Y
BA0,1
REGE
DQ
MIT-DS-0351-0.0
0
ACT#0
0 0
CL=4
Q0 Q0 Q0 Q0
PRE#0 ACT#0
READ to PRE ³BL allows full data out
0
Italic parameter indicates minimum case
MITSUBISHI
ELECTRIC
0
Q0
30/Sep. /1999
25
Page 26
Preliminary Spec.
READ#0
READ#0
READ#1
Some contents are subject to change without notice.
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Burst READ (multi bank)
BL=4,CL=4,Latch mode(REGE="H")
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK
tRC
/CS
tRRD
tRAS tRP
/RAS
MITSUBISHI LSIs
MH8S72DBFD-7,-8
tRRD
/CAS
/WE
CKE
DQM
A0-9
A10
A11
tRCD
DQM read latency =3
X
X
X
Y
X
X
X
Y
tRCD
X
X
X
Y
X
X
X
BA0,1
REGE
DQ
MIT-DS-0351-0.0
0
ACT#0
0 0
1
CL=4
ACT#1
1
CL=4
Q0 Q0 Q0 Q0
PRE#0 ACT#0
Italic parameter indicates minimum case
MITSUBISHI
ELECTRIC
0
Q1 Q1 Q1 Q1
PRE#1 ACT#2
21
0
30/Sep. /1999
26
Page 27
Preliminary Spec.
WRITE#0
WRITE#1
Some contents are subject to change without notice.
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Burst WRITE (multi bank) with AUTO-PRECHARGE
BL=4,Buffer mode(REGE="L")
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK
tRC
/CS
MITSUBISHI LSIs
MH8S72DBFD-7,-8
/RAS
/CAS
/WE
CKE
DQM
A0-9
A10
tRRD
tRCD
BL-1+ tWR + tRP
BL-1+ tWR + tRP
X
X
Y
X
X
Y X
X
tRRD
tRCD
tRCD
Y
X
X
Y
A11
BA0,1
REGE
DQ
MIT-DS-0351-0.0
X
0
ACT#0 WRITE#0 with
X
0 1
1
D0 D0 D0 D0
ACT#1 WRITE#1 with
AutoPrecharge
D1 D1 D1 D1
AutoPrecharge
X
0
ACT#0
Italic parameter indicates minimum case
MITSUBISHI
ELECTRIC
X
0
1
D0 D0 D0 D0
ACT#1
30/Sep. /1999
1
D1
27
Page 28
Preliminary Spec.
WRITE#0
WRITE#1
Some contents are subject to change without notice.
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Burst WRITE (multi bank) with AUTO-PRECHARGE
BL=4,Latch mode(REGE="H")
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK
tRC
/CS
MITSUBISHI LSIs
MH8S72DBFD-7,-8
/RAS
/CAS
/WE
CKE
DQM
A0-9
A10
tRRD
tRCD
BL-1+ tWR + tRP
BL-1+ tWR + tRP
X
X
Y
X
X
Y X
X
tRRD
tRCD
tRCD
Y
X
X
Y
A11
BA0,1
REGE
DQ
MIT-DS-0351-0.0
X
0
ACT#0 WRITE#0 with
X
0 1
1
D0 D0 D0 D0
ACT#1 WRITE#1 with
AutoPrecharge
AutoPrecharge
X
0
D1 D1 D1 D1
ACT#0
Italic parameter indicates minimum case
MITSUBISHI
ELECTRIC
X
0
1
D0 D0 D0 D0
ACT#1
30/Sep. /1999
1
28
Page 29
Preliminary Spec.
READ#0
Some contents are subject to change without notice.
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Burst READ (multi bank) with AUTO-PRECHARGE
BL=4,CL=3 Buffer mode(REGE="L")
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK
tRC
/CS
MITSUBISHI LSIs
MH8S72DBFD-7,-8
/RAS
/CAS
/WE
CKE
DQM
A0-9
A10
X
X
tRRD
tRCD
tRRD
tRCD
BL+tRP
BL+tRP
DQM read latency =2
Y
X
X
Y
X
X
Y
tRCD
X
X
Y
A11
BA0,1
REGE
DQ
MIT-DS-0351-0.0
X
0
ACT#0 READ#0 with
ACT#1
X
0
1
CL=3
Auto-Precharge
1
CL=3
Q0 Q0 Q0 Q0
READ#1 with
Auto-Precharge
MITSUBISHI
ELECTRIC
X
0
Q1 Q1 Q1 Q1
ACT#0
Italic parameter indicates minimum case
0
X
1
CL=3
ACT#1
30/Sep. /1999
Q0
1
Q0
29
Page 30
Preliminary Spec.
READ#0
Some contents are subject to change without notice.
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Burst READ (multi bank) with AUTO-PRECHARGE
BL=4,CL=4 Latch mode(REGE="H")
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK
tRC
/CS
MITSUBISHI LSIs
MH8S72DBFD-7,-8
/RAS
/CAS
/WE
CKE
DQM
A0-9
A10
X
X
tRRD
tRCD
BL+tRP
DQM read latency =3
Y
X
X
tRRD
tRCD
BL+tRP
Y
X
X
Y
tRCD
X
X
Y
A11
BA0,1
REGE
DQ
MIT-DS-0351-0.0
X
0
ACT#0 READ#0 with
ACT#1
X
0
1
CL=4
Auto-Precharge
1
CL=4
Q0 Q0 Q0 Q0
ACT#0
READ#1 with
Auto-Precharge
Italic parameter indicates minimum case
MITSUBISHI
ELECTRIC
X
0
Q1 Q1 Q1 Q1
0
X
1
CL=4
ACT#1
30/Sep. /1999
1
Q0
30
Page 31
Preliminary Spec.
Some contents are subject to change without notice.
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Page Mode Burst Write (multi bank)
BL=4,Buffer mode(REGE="L")
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK
/CS
tRRD
/RAS
tRCD
/CAS
MITSUBISHI LSIs
MH8S72DBFD-7,-8
/WE
CKE
DQM
A0-9
A10
A11
BA0,1
REGE
X
X
X
0
Y
X
X
X
0 0
1
Y Y
Y
1
0
DQ
MIT-DS-0351-0.0
D0 D0 D0 D0
ACT#0 WRITE#0 WRITE#0
ACT#1
D0 D0 D0 D0 D0 D0 D0
WRITE#0
Italic parameter indicates minimum case
MITSUBISHI
D1 D1 D1 D1
WRITE#1
30/Sep. /1999
ELECTRIC
31
Page 32
Preliminary Spec.
WRITE#0
WRITE#0
WRITE#1
WRITE#0
Some contents are subject to change without notice.
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Page Mode Burst Write (multi bank)
BL=4,Latch mode(REGE="H")
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK
/CS
tRRD
/RAS
tRCD
/CAS
MITSUBISHI LSIs
MH8S72DBFD-7,-8
/WE
CKE
DQM
A0-9
A10
A11
BA0,1
REGE
X
X
X
0
Y
X
X
X
0 0
1
Y Y
Y
1
0
DQ
MIT-DS-0351-0.0
ACT#0
ACT#1
D0 D0 D0 D0
D0 D0 D0 D0 D0 D0
Italic parameter indicates minimum case
MITSUBISHI
D1 D1 D1 D1
30/Sep. /1999
ELECTRIC
32
Page 33
Preliminary Spec.
READ#1
READ#0
Some contents are subject to change without notice.
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Page Mode Burst Read (multi bank)
BL=4,CL=3 Buffer mode(REGE="L")
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK
/CS
tRRD
/RAS
tRCD
/CAS
MITSUBISHI LSIs
MH8S72DBFD-7,-8
/WE
CKE
DQM
A0-9
A10
A11
BA0,1
REGE
DQM read latency=2
X
X
X
0
Y
X
X
X
0 0
1
Y Y
Y
1
0
DQ
MIT-DS-0351-0.0
CL=3 CL=3 CL=3
Q0 Q0 Q0
Q0
ACT#0 READ#0 READ#0
ACT#1
Q0 Q0 Q0 Q0
Italic parameter indicates minimum case
MITSUBISHI
Q1 Q1 Q1 Q1
30/Sep. /1999
ELECTRIC
33
Page 34
Preliminary Spec.
Some contents are subject to change without notice.
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Page Mode Burst Read (multi bank)
BL=4,CL=4 Latch mode(REGE="H")
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK
/CS
tRRD
/RAS
tRCD
/CAS
MITSUBISHI LSIs
MH8S72DBFD-7,-8
/WE
CKE
DQM
A0-9
A10
A11
BA0,1
REGE
DQM read latency=3
X
X
X
0
Y
X
X
X
0 0
1
Y Y
Y
1
0
DQ
MIT-DS-0351-0.0
CL=4 CL=4 CL=4
Q0 Q0 Q0
Q0
ACT#0 READ#0 READ#0
ACT#1
READ#0
Q0 Q0 Q0 Q0
READ#1
Italic parameter indicates minimum case
MITSUBISHI
Q1 Q1 Q1
30/Sep. /1999
ELECTRIC
34
Page 35
Preliminary Spec.
WRITE#0
WRITE#1
WRITE#0
Some contents are subject to change without notice.
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Write Interrupted by Write / Read
BL=4,Buffer mode(REGE="L")
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK
/CS
tRRD
/RAS
MITSUBISHI LSIs
MH8S72DBFD-7,-8
/CAS
/WE
CKE
DQM
A0-9
A10
A11
tRCD
X
X
X
Y
X
X
X
tCCD
Y Y
Y
Y
BA0,1
REGE
DQ
MIT-DS-0351-0.0
0
ACT#0
0
1
D0 D0 D0 D0
ACT#1
Burst Write can be interrupted by Write or Read of any active bank.
0 0 0
D0 D0 D1 D1 Q0 Q0 Q0
WRITE#0
1
CL=3
Q0
READ#0
Italic parameter indicates minimum case
MITSUBISHI
ELECTRIC
30/Sep. /1999
35
Page 36
Preliminary Spec.
WRITE#0
WRITE#1
WRITE#0
Some contents are subject to change without notice.
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Write Interrupted by Write / Read
BL=4,Latch mode(REGE="H")
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK
/CS
tRRD
/RAS
MITSUBISHI LSIs
MH8S72DBFD-7,-8
/CAS
/WE
CKE
DQM
A0-9
A10
A11
tRCD
X
X
X
Y
X
X
X
tCCD
Y Y
Y
Y
BA0,1
REGE
DQ
MIT-DS-0351-0.0
0
ACT#0
0
1
D0 D0 D0 D0
ACT#1
Burst Write can be interrupted by Write or Read of any active bank.
0 0 0
WRITE#0
1
CL=4
D0 D0 D1 D1 Q0 Q0 Q0
READ#0
Italic parameter indicates minimum case
MITSUBISHI
30/Sep. /1999
ELECTRIC
36
Page 37
Preliminary Spec.
READ#0
WRITE#0
READ#1
READ#0
READ#0
Some contents are subject to change without notice.
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Read Interrupted by Read / Write
BL=4,CL=3 Buffer mode(REGE="L")
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK
/CS
tRRD
/RAS
tRCD
/CAS
/WE
MITSUBISHI LSIs
MH8S72DBFD-7,-8
CKE
DQM
A0-9
A10
A11
BA0,1
DQ
REGE
DQM read latency=2
X
X
X
0
Y
X
X
X
0 0
1
Y Y
Y
0
Q0 Q0 Q0
Q0
Y
1
Y
0
Q0 Q0 Q1 Q1
Q0 D0 D0
0
ACT#0
MIT-DS-0351-0.0
READ#0
ACT#1
Burst Read can be interrupted by Read or Write of any active bank.
Italic parameter indicates minimum case
MITSUBISHI
blank to prevent bus contention
30/Sep. /1999
ELECTRIC
37
Page 38
Preliminary Spec.
READ#0
WRITE#0
READ#1
READ#0
READ#0
READ#0
Some contents are subject to change without notice.
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Read Interrupted by Read / Write
BL=4,CL=4 Latch mode(REGE="H")
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK
/CS
tRRD
/RAS
tRCD
/CAS
/WE
MITSUBISHI LSIs
MH8S72DBFD-7,-8
CKE
DQM
A0-9
A10
A11
BA0,1
DQ
REGE
DQM read latency=3
X
X
X
0
Y
X
X
X
0 0
1
Y Y
Y
0
Q0 Q0 Q0
Y
1
Q0
Y
0
Q0 Q0 Q1 Q1
Q0 D0
0
ACT#0
MIT-DS-0351-0.0
ACT#1
Burst Read can be interrupted by Read or Write of any active bank.
Italic parameter indicates minimum case
MITSUBISHI
blank to prevent bus contention
30/Sep. /1999
ELECTRIC
38
Page 39
Preliminary Spec.
Some contents are subject to change without notice.
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Write Interrupted by Precharge
BL=4,Buffer mode(REGE="L")
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK
/CS
tRRD
/RAS
tRCD
/CAS
/WE
MITSUBISHI LSIs
MH8S72DBFD-7,-8
CKE
DQM
A0-9
A10
A11
BA0,1
DQ
REGE
X
X
X
0
Y
X
X
X
0
1
D0 D0 D0 D0
Y
1 1
D1 D1 D1 D1 D1
1
0
X
X
X
1
Y
ACT#0 WRITE#0
MIT-DS-0351-0.0
ACT#1
Burst Write is not interrupted
by Precharge of the other bank.
WRITE#1
PRE#0
PRE#1
Burst Write is interrupted by
Precharge of the same bank.
Italic parameter indicates minimum case
MITSUBISHI
ELECTRIC
ACT#1 WRITE#1
30/Sep. /1999
39
Page 40
Preliminary Spec.
WRITE#0
WRITE#1
Some contents are subject to change without notice.
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Write Interrupted by Precharge
BL=4,Latch mode(REGE="H")
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK
/CS
tRRD
/RAS
tRCD
/CAS
/WE
MITSUBISHI LSIs
MH8S72DBFD-7,-8
CKE
DQM
A0-9
A10
A11
BA0,1
DQ
REGE
X
X
X
0
Y
X
X
X
0
1
D0 D0 D0 D0
Y
1 1
1
0
D1 D1 D1 D1
X
X
X
1
Y
ACT#0
MIT-DS-0351-0.0
ACT#1
Burst Write is not interrupted
by Precharge of the other bank.
WRITE#1
PRE#0
PRE#1
Burst Write is interrupted by
Precharge of the same bank.
Italic parameter indicates minimum case
MITSUBISHI
ELECTRIC
ACT#1
30/Sep. /1999
40
Page 41
Preliminary Spec.
READ#0
READ#1
Some contents are subject to change without notice.
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Read Interrupted by Precharge
BL=4,CL=3 Buffer mode(REGE="L")
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK
/CS
tRRD
/RAS
tRCD
/CAS
MITSUBISHI LSIs
MH8S72DBFD-7,-8
tRP
tRCD
/WE
CKE
DQM
A0-9
A10
A11
BA0,1
DQ
DQM read latency=2
X
X
X
0
Y
X
X
X
0
1
Y
1
Q0 Q0 Q0
Q0
1
0
X
X
X
1
Q1 Q1
Y
1
REGE
ACT#0
MIT-DS-0351-0.0
ACT#1
Burst Read is not interrupted
by Precharge of the other bank.
READ#1 ACT#1
PRE#0
PRE#1
Italic parameter indicates minimum case
MITSUBISHI
ELECTRIC
Burst Read is interrupted
by Precharge of the same bank.
30/Sep. /1999
41
Page 42
Preliminary Spec.
READ#1
READ#1
Some contents are subject to change without notice.
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Read Interrupted by Precharge
BL=4,CL=4 Latch mode(REGE="H")
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK
/CS
MITSUBISHI LSIs
MH8S72DBFD-7,-8
/RAS
/CAS
/WE
CKE
DQM
A0-9
A10
X
X
tRRD
tRCD
tRP
tRCD
DQM read latency=3
Y
X
X
Y
X
X
Y
A11
BA0,1
X
0
DQ
REGE
ACT#0 READ#0
MIT-DS-0351-0.0
X
0
1
ACT#1
Burst Read is not interrupted
by Precharge of the other bank.
1
Q0 Q0 Q0
1
0
Q0
PRE#0
PRE#1
Italic parameter indicates minimum case
MITSUBISHI
ELECTRIC
X
1
Q1 Q1
ACT#1
Burst Read is interrupted
by Precharge of the same bank.
1
30/Sep. /1999
42
Page 43
Preliminary Spec.
WRITE#0
Some contents are subject to change without notice.
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Mode Register Setting
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK
/CS
tRC
/RAS
/CAS
MITSUBISHI LSIs
MH8S72DBFD-7,-8
tRSC
tRCD
/WE
CKE
DQM
A0-9
A10
A11
BA0,1
DQ
M
0
X
X
X
0
Y
0
D0
D0 D0 D0
REGE
MIT-DS-0351-0.0
Auto-Ref (last of 8 cycles)
Mode
Register
Setting
Italic parameter indicates minimum case
MITSUBISHI
ACT#0
30/Sep. /1999
ELECTRIC
43
Page 44
Preliminary Spec.
Auto-Refresh @BL=4
After tRC from Auto-Refresh,
Some contents are subject to change without notice.
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK
/CS
tRC
/RAS
/CAS
MITSUBISHI LSIs
MH8S72DBFD-7,-8
tRCD
/WE
CKE
DQM
A0-9
A10
A11
BA0,1
DQ
X
X
X
0
Y
0
D0
D0 D0 D0
REGE
Auto-Refresh
Before Auto-Refresh,
all banks must be idle state.
MIT-DS-0351-0.0
ACT#0 WRITE#0
all banks are idle state.
Italic parameter indicates minimum case
MITSUBISHI
ELECTRIC
30/Sep. /1999
44
Page 45
Preliminary Spec.
Some contents are subject to change without notice.
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Self-Refresh
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK
CLK can be stopped
/CS
/RAS
/CAS
MITSUBISHI LSIs
MH8S72DBFD-7,-8
tRC+1
/WE
CKE
DQM
A0-9
A10
A11
BA0,1
DQ
tSRX
CKE must be low to maintain Self-Refresh
X
X
X
0
REGE
MIT-DS-0351-0.0
Self-Refresh Entry
Before Self-Refresh Entry,
all banks must be idle state.
Self-Refresh Exit ACT#0
After tRC from Self-Refresh Exit,
all banks are idle state.
Italic parameter indicates minimum case
MITSUBISHI
ELECTRIC
30/Sep. /1999
45
Page 46
Preliminary Spec.
DQM Write Mask
WRITE#0
Some contents are subject to change without notice.
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
BL=4,Buffer mode(REGE="L")
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK
/CS
/RAS
tRCD
/CAS
/WE
MITSUBISHI LSIs
MH8S72DBFD-7,-8
CKE
DQM
A0-9
A10
A11
BA0,1
DQ
REGE
X
X
X
0
Y
0 0
D0 D0 D0 D0
Y
masked
Y
0
masked
D0 D0 D0
MIT-DS-0351-0.0
ACT#0 WRITE#0
Italic parameter indicates minimum case
MITSUBISHI
ELECTRIC
WRITE#0
30/Sep. /1999
46
Page 47
Preliminary Spec.
DQM Write Mask
WRITE#0
Some contents are subject to change without notice.
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
BL=4,Latch mode(REGE="H")
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK
/CS
/RAS
tRCD
/CAS
MITSUBISHI LSIs
MH8S72DBFD-7,-8
/WE
CKE
DQM
A0-9
A10
A11
BA0,1
DQ
X
X
X
0
Y
0 0
D0 D0 D0 D0
Y
masked
Y
0
masked
D0 D0 D0
REGE
MIT-DS-0351-0.0
ACT#0 WRITE#0
Italic parameter indicates minimum case
MITSUBISHI
ELECTRIC
WRITE#0
30/Sep. /1999
47
Page 48
Preliminary Spec.
READ#0
READ#0
Some contents are subject to change without notice.
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
DQM Read Mask
BL=4, CL=3 Buffer mode(REGE="L")
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK
/CS
/RAS
tRCD
/CAS
/WE
MITSUBISHI LSIs
MH8S72DBFD-7,-8
CKE
DQM
A0-9
A10
A11
BA0,1
DQ
REGE
DQM read latency=2
X
X
X
0
Y
0 0
Q0 Q0 Q0 Q0
Y
Y
0
masked
masked
Q0 Q0 Q0
ACT#0 READ#0
MIT-DS-0351-0.0
Italic parameter indicates minimum case
MITSUBISHI
30/Sep. /1999
ELECTRIC
48
Page 49
Preliminary Spec.
READ#0
READ#0
READ#0
Some contents are subject to change without notice.
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
DQM Read Mask
BL=4,CL=4 Latch mode(REGE="H")
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK
/CS
/RAS
tRCD
/CAS
/WE
MITSUBISHI LSIs
MH8S72DBFD-7,-8
CKE
DQM
A0-9
A10
A11
BA0,1
DQ
REGE
DQM read latency=3
X
X
X
0
Y
0 0
Y
Q0 Q0 Q0 Q0
Y
0
masked
masked
Q0 Q0
ACT#0
MIT-DS-0351-0.0
Italic parameter indicates minimum case
MITSUBISHI
ELECTRIC
30/Sep. /1999
49
Page 50
Preliminary Spec.
Some contents are subject to change without notice.
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Power Down
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK
/CS
/RAS
/CAS
MITSUBISHI LSIs
MH8S72DBFD-7,-8
/WE
CKE
DQM
A0-9
A10
A11
BA0,1
DQ
Standby Power Down
CKE latency=1
Active Power Down
X
X
X
0
REGE
Precharge All ACT#0
MIT-DS-0351-0.0
Italic parameter indicates minimum case
MITSUBISHI
ELECTRIC
30/Sep. /1999
50
Page 51
Preliminary Spec.
CLK Suspend
WRITE#0
CLK suspended
Some contents are subject to change without notice.
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
BL=4,CL=3 Buffer mode(REGE="L")
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK
/CS
/RAS
tRCD
/CAS
MITSUBISHI LSIs
MH8S72DBFD-7,-8
/WE
CKE
DQM
A0-9
A10
A11
BA0,1
DQ
CKE latency=1 CKE latency=1
X
X
X
0
Y
0 0
D0 D0 D0D0
Y
Q0 Q0 Q0 Q0
REGE
MIT-DS-0351-0.0
ACT#0
CLK suspended
READ#0
Italic parameter indicates minimum case
MITSUBISHI
ELECTRIC
30/Sep. /1999
51
Page 52
Preliminary Spec.
CLK Suspend
READ#0
CLK suspended
CLK suspended
Some contents are subject to change without notice.
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
BL=4,CL=4 Latch mode(REGE="H")
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK
/CS
/RAS
tRCD
/CAS
/WE
MITSUBISHI LSIs
MH8S72DBFD-7,-8
CKE
DQM
A0-9
A10
A11
BA0,1
DQ
REGE
CKE latency=2 CKE latency=2
X
X
X
0
Y
0 0
D0 D0 D0D0
Y
Q0 Q0 Q0 Q0
MIT-DS-0351-0.0
ACT#0 WRITE#0
Italic parameter indicates minimum case
MITSUBISHI
ELECTRIC
30/Sep. /1999
52
Page 53
Preliminary Spec.
SDRAM Cycletime at Max. Supported CAS Latency (CL).
ECC
Minimum Clock Delay,Back to Back Random Column Addresses
1/2/4/8/Full page
buffered,registered
Precharge All,Auto precharge
SDRAM Access form Clock(2nd highest CAS latency)
SDRAM Access form Clock(3rd highest CAS latency)
-8-8-7
-7
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH8S72DBFD-7,-8
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Serial Presence Detect Table I
Byte Function described SPD enrty data SPD DATA(hex)
0 Defines # bytes written into serial memory at module mfgr 128 80
1 Total # bytes of SPD memory device 256 Bytes 08
2 Fundamental memory type SDRAM 04
3 # Row Addresses on this assembly A0-A11 0C
4 # Column Addresses on this assembly
5 # Module Banks on this assembly
6 Data Width of this assembly...
7 ... Data Width continuation 0 00
8 Voltage interface standard of this assembly LVTTL 01
9
Cycle time for CL=3
10 SDRAM Access from Clock
tAC for CL=3
11 DIMM Configuration type (Non-parity,Parity,ECC)
12 Refresh Rate/Type self refresh(15.625uS) 80
13 SDRAM width,Primary DRAM
14 Error Checking SDRAM data width
15
16 Burst Lengths Supported
17 # Banks on Each SDRAM device 4bank 04
18 CAS# Latency 2/3 06
19 CS# Latency 0 01
20 Write Latency 0 01
21 SDRAM Module Attributes
22 SDRAM Device Attributes:General
23 SDRAM Cycle time(2nd highest CAS latency)
Cycle time for CL=2
24
tAC for CL=2
25 SDRAM Cycle time(3rd highest CAS latency) N/A 00
26
A0-A8 09
1BANK 01
x72 48
10ns
6ns 60
x8 08
x8 08
1 01
Write1/Read Burst
10ns
13ns D0
6ns 60
7ns 70
N/A 00
A0
02
8F
1F
0E
A0
27 Precharge to Active Minimum 20ns 14
28 Row Active to Row Active Min. 20ns 14
29 RAS to CAS Delay Min 20ns 14
30 Active to Precharge Min 50ns 32
MIT-DS-0351-0.0
MITSUBISHI
ELECTRIC
30/Sep. /1999
53
Page 54
Preliminary Spec.
4D4838533732444246442D37202020202020
4D4838533732444246442D38202020202020
-8
-7
Some contents are subject to change without notice.
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Serial Presence Detect Table II
MITSUBISHI LSIs
MH8S72DBFD-7,-8
31 Density of each bank on module
32
33 Command and Address signal input hold time
34 Data signal input setup time 2ns
35 Data signal input hold time
36-61
62 SPD Revision
63 Checksum for bytes 0-62
64-71 Manufactures Jedec ID code per JEP-108E MITSUBISHI 1CFFFFFFFFFFFFFF
72 Manufacturing location Miyoshi,Japan 01
73-90 Manufactures Part Number
Command and Address signal input setup time 2ns 20
Superset Information (may be used in future) option 00
64MByte 10
1ns 10
1ns 10
rev 1.2A 12
Check sum for -7
Check sum for -8
Tajima,Japan 02
NC,USA 03
Germany 04
MH8S72DBFD-7
MH8S72DBFD-8
20
36
76
91-92 Revision Code PCB revision rrrr
93-94 Manufacturing date year/week code yyww
95-98 Assembly Serial Number serial number ssssssss
99-125 Manufacture Specific Data option 00
126 Intetl specification frequency
127 Intel specification CAS# Latency support
128+ Unused storage locations open 00
100MHz 64
CL=2/3,AP,CK0
CL=3,AP,CK0
8F
8D
MIT-DS-0351-0.0
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ELECTRIC
30/Sep. /1999
54
Page 55
Preliminary Spec.
Some contents are subject to change without notice.
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
133.35
MITSUBISHI LSIs
MH8S72DBFD-7,-8
3
8.89
11.43
3
24.495
6.35
36.83
42.18
6.35
1.27
54.61
127.35
38.10
4.0Max
MIT-DS-0351-0.0
MITSUBISHI
ELECTRIC
1.27
30/Sep. /1999
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Preliminary Spec.
Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering
7.Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S72DBFD-7,-8
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Keep safety first in your circuit designs!
Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products
better and more reliable,but there is always the possibility that trouble may occur with them.
Trouble with semiconductors consideration to safety when making your circuit designs,with
appropriate measures such as (i) placement of substitutive,auxiliary circuits,(ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
1.These materials are intended as a reference to assist our customers in the selection of the Mitsubishi
semiconductor product best suited to the customer's application;they do not convey any license under any
intellectual property rights,or any other rights,belonging to Mitsubishi Electric Corporation or a third party.
2.Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any thirdparty's rights,originating in the use of any product data,diagrams,charts or circuit application examples
contained in these materials.
3.All information contained in these materials,including product data, diagrams and charts,represent
information on products at the time of publication of these materials,and are subject to change by Mitsubishi
Electric Corporation without notice due to product improvements or other reasons. It is therefore
recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubish
Semiconductor product
distributor for the latest product information before purchasing a product listed herein.
4.Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or
system that is used under circumstances in which human life is potentially at stake. Please contact
the use of a product contained herein for special applications,such as apparatus or systems for
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the approved destination. Any diversion or reexport contrary to the export control laws and regulations of
Japan and/or the country of destination is prohibited.
for further details on these materials or the products contained therein.
MIT-DS-0351-0.0
MITSUBISHI
30/Sep. /1999
ELECTRIC
56
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