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603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
DESCRIPTION
APPLICATION
FEATURES
Type name
MH8S72BCFD-6
Frequency
133MHz
PRELIMINARY
Some of contents are subject to change without notice.
The MH8S72BCFD is 8388608 - word x 72-bit Synchronous
DRAM module. This consist of eighteen industry standard
8M x 8 Synchronous DRAMs in TSOP.
The TSOP on a card edge dual in-line package provides any
application where high densities and large of quantities memory
are required.
This is a socket-type memory module ,suitable for easy
interchange or addition of module.
MITSUBISHI LSIs
MH8S72BCFD-6
85pin
1pin
Max.
Utilizes industry standard 8M X 8 Synchronous DRAMs in TSOP
package , industry standard Resistered buffer in TSSOP
package,industry standard PLL in TSSOP package
Single 3.3V +/- 0.3V supply
Max.Clock frequency 133MHz
Fully synchronous operation referenced to clock rising edge
4-bank operation controlled by BA0,BA1(Bank Address)
/CAS latency -2/3(programmable,at buffer mode)
LVTTL Interface
Burst length 1/2/4/8/Full Page(programmable)
Burst type- Sequential and interleave burst (programmable)
Random column access
Burst Write / Single Write(programmable)
Auto precharge / All bank precharge controlled by A10
Auto refresh and Self refresh
4096 refresh cycles every 64ms
Discrete IC and module design conform to
PC133 specification.
Main memory or graphic memory in computer systems
Access Time from CLK
[component level]
5.4ns
(CL = 4 at Latch mode)
94pin
95pin
124pin
125pin
168pin
10pin
11pin
40pin
41pin
84pin
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MITSUBISHI LSIs
/WE
MH8S72BCFD-6
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
PIN NO. PIN NAME PIN NO. PIN NAME PIN NO. PIN NAME PIN NO. PIN NAME
1
2 DQ0 44 NC
3 DQ1 45 /S2
4 DQ2 46 DQMB2
5 DQ3 47 DQMB3
6 VDD 48 NC
7 DQ4 49 VDD
8 DQ5 50 NC
9 DQ6 51 NC
10 DQ7 52
11 DQ8 53
12
13 DQ9 55 DQ16
14 DQ10 56 DQ17
15 DQ11 57 DQ18
16 DQ12 58 DQ19
17 DQ13 59 VDD
18 VDD 60 DQ20
19 DQ14 61 NC
20 DQ15 62
21
22
23 VSS 65 DQ21
24 NC 66 DQ22
25 NC 67 DQ23
26 VDD 68
27
28 DQMB0 70 DQ25
29 DQMB1 71 DQ26
30 /S0 72 DQ27
31 NC 73 VDD
32 VSS 74 DQ28
33 A0 75 DQ29
34 A2 76 DQ30
35 A4 77 DQ31
36 A6 78 VSS
37 A8 79
38
39
40 VDD 82 SDA
41 VDD 83 SCL
42 CK0 84 VDD
VSS
VSS
CB0
CB1
A10
BA1
43
54 VSS
63
64 VSS
69 DQ24
80 NC
81
VSS 85
CB2
CB3
100
101
102
103
NC
CKE1
VSS 110
CK2
WP
104
105
106
107
108
109
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
86
87
88
89
90
91
92
93
94
95
96
97
98
99
VSS 127
DQ32 128
DQ33 129
DQ34 130 DQMB6
DQ35 131 DQMB7
VDD 132
DQ36 133 VDD
DQ37 134 NC
DQ38 135 NC
DQ39 136
DQ40 137
VSS 138 VSS
DQ41 139 DQ48
DQ42 140 DQ49
DQ43 141 DQ50
DQ44 142 DQ51
DQ45 143 VDD
VDD 144 DQ52
DQ46 145 NC
DQ47 146
CB4
CB5
VSS 149 DQ53
NC 150 DQ54
NC 151 DQ55
VDD 152 VSS
/CAS 153 DQ56
DQMB4 154 DQ57
DQMB5 155 DQ58
NC
/RAS 157 VDD
VSS 158 DQ60
A1 159 DQ61
A3 160 DQ62
A5 161 DQ63
A7 162 VSS
A9 163
BA0
A11
VDD 166 SA1
CK1 167 SA2
NC
147
148 VSS
156 DQ59
164 NC
165 SA0
168 VDD
VSS
CKE0
NC
NC
CB6
CB7
NC
REGE
CK3
NC = No Connection
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MITSUBISHI LSIs
D0
D4
D6
D7D8D5
D2
D3
D1
MH8S72BCFD-6
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Add
CKE0
/S0,2
DQM0-7
/W
/RAS
/CAS
10K
REGE
VDD
From PLL
CK0
CK1 - CK3 Terminated
RCKE0
R/S0
R/S2
PLL
D0-8
D0-2,5-6
D3-4,7-8
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
RCKE0
R/S0,2
RDQM0-7
RDQM 0
RDQM 1
RDQM 2
RDQM 3
RDQM 4
RDQM 5
RDQM 6
RDQM 7
D0
D1-2
D3
D4
D5
D6
D7
D8
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
SCL
WP
47K
VDD
VSS
SERIAL PD
A0 A1 A2
SA0 SA1 SA2
SDA
D0 to D8
D0 to D8
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603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
CKE0
PIN FUNCTION
MITSUBISHI LSIs
MH8S72BCFD-6
CK0
/S0,2
/RAS,/CAS,/W
A0-11
BA0-1
Input
Input
Input
Input
Input
Input
Master Clock:All other inputs are referenced to the rising
edge of CK
Clock Enable:CKE controls internal clock.When CKE is
low,internal clock for the following cycle is ceased. CKE is
also used to select auto / self refresh. After self refresh
mode is started, CKE E becomes asynchronous input.Self
refresh is maintained as long as CKE is low.
Chip Select: When /S is high,any command means
No Operation.
Combination of /RAS,/CAS,/W defines basic
commands.
A0-11 specify the Row/Column Address in conjunction with
BA.The Row Address is specified by A0-11.The Column
Address is specified by A0-8.A10 is also used to indicate
precharge option.When A10 is high at a read / write
command, an auto precharge is performed. When A10 is
high at a precharge command, both banks are precharged.
Bank Address:BA0,1 is specifies the four bank to which
a command is applied.BA must be set with ACT ,PRE
,READ ,WRITE commands
DQ0-63
CB0-7
DQM0-7
Vdd,Vss
REGE
MIT-DS-0312-0.0
Input/Output
Input
Power Supply
Input
Data In and Data out are referenced to the rising edge
of CK
Din Mask/Output Disable:When DQMB is high in burst
write.Din for the current cycle is masked.When DQMB is high
in burst read,Dout is disabled at the next but one cycle.
Power Supply for the memory mounted
module.
Register enable:When REGE is low,All control signals and
address are buffered. (Buffer mode) When REGE is
high,All control and address are latched. (Latch mode)
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MH8S72BCFD-6
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
BASIC FUNCTIONS
The MH8S72BCFD provides basic functions,bank(row)activate,burst read / write,
bank(row)precharge,and auto / self refresh.
Each command is defined by control signals of /RAS,/CAS and /WE at CK rising edge. In
addition to 3 signals,/S,CKE and A10 are used as chip select,refresh option,and precharge
option,respectively.
To know the detailed definition of commands please see the command truth table.
CK
/S
/RAS
/CAS
/WE
CKE
A10
Chip Select : L=select, H=deselect
Command
Command
Command
Refresh Option @refresh command
Precharge Option @precharge or read/write command
define basic commands
Activate(ACT) [/RAS =L, /CAS = /WE =H]
ACT command activates a row in an idle bank indicated by BA.
Read(READ) [/RAS =H,/CAS =L, /WE =H]
READ command starts burst read from the active bank indicated by BA.First output
data appears after /CAS latency. When A10 =H at this command,the bank is
deactivated after the burst read(auto-precharge,READA).
Write(WRITE) [/RAS =H, /CAS = /WE =L]
WRITE command starts burst write to the active bank indicated by BA. Total data
length to be written is set by burst length. When A10 =H at this command, the bank
is deactivated after the burst write(auto-precharge,WRITEA).
Precharge(PRE) [/RAS =L, /CAS =H,/WE =L]
PRE command deactivates the active bank indicated by BA. This command also
terminates burst read / write operation. When A10 =H at this command, both banks
are deactivated(precharge all, PREA).
Auto-Refresh(REFA) [/RAS =/CAS =L, /WE =CKE =H]
PEFA command starts auto-refresh cycle. Refresh address including bank address
are generated internally. After this command, the banks are precharged automatically.
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MH8S72BCFD-6
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
COMMAND TRUTH TABLE
CKE
COMMAND MNEMONIC
Deselect DESEL H X H X X X X X X
No Operation NOP H X L H H H X X X
n-1
CKE
n
/RAS /CAS /WE BA0,1 A10 A0-9
/S
A11
X
X
Row Adress Entry &
Bank Activate
Single Bank Precharge PRE H X L L H L V L X
Precharge All Bank PREA H X L L H L X H X
Column Address Entry
& Write
Column Address Entry
& Write with Auto-
Precharge
Column Address Entry
& Read
Column Address Entry
& Read with Auto
Precharge
Auto-Refresh REFA H H L L L H X X X
Self-Refresh Entry REFS H L L L L H X X X
Self-Refresh Exit REFSX
Burst Terminate TBST H X L H H L X X X
Mode Register Set MRS H X L L L L L L V*1
ACT H X L L H H V V V
WRITE H X L H L L V L V
WRITEA H X L H L L V H V
READ H X L H L H V L V
READA H X L H L H V H V
L H H X X X X X X
L H L H H H X X X
V
X
X
X
X
X
X
X
X
X
X
X
L
H =High Level, L = Low Level, V = Valid, X = Don't Care, n = CK cycle number
NOTE:
1.A7-9 = 0, A0-6 = Mode Address
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MITSUBISHI LSIs
MH8S72BCFD-6
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
FUNCTION TRUTH TABLE
Current State /S /RAS /CAS /WE Address Command Action
IDLE H X X X X DESEL NOP
L H H H X NOP NOP
L H H L BA TBST ILLEGAL*2
L H L X BA,CA,A10 READ/WRITE ILLEGAL*2
L L H H BA,RA ACT Bank Active,Latch RA
L L H L BA,A10 PRE/PREA NOP*4
L L L H X REFA Auto-Refresh*5
L L L L
ROW ACTIVE H X X X X DESEL NOP
L H H H X NOP NOP
L H H L BA TBST NOP
L H L H BA,CA,A10 READ/READA
L H L L BA,CA,A10
L L H H BA,RA ACT Bank Active/ILLEGAL*2
L L H L BA,A10 PRE/PREA Precharge/Precharge All
L L L H X REFA ILLEGAL
L L L L
READ H X X X X DESEL NOP(Continue Burst to END)
L H H H X NOP NOP(Continue Burst to END)
L H H L BA TBST Terminate Burst
L H L H BA,CA,A10 READ/READA
L H L L BA,CA,A10 WRITE/WRITEA
L L H H BA,RA ACT Bank Active/ILLEGAL*2
L L H L BA,A10 PRE/PREA Terminate Burst,Precharge
L L L H X REFA ILLEGAL
L L L L
Op-Code,
Mode-Add
Op-Code,
Mode-Add
Op-Code,
Mode-Add
MRS Mode Register Set*5
Begin Read,Latch CA,
Determine Auto-Precharge
WRITE/
WRITEA
MRS ILLEGAL
MRS ILLEGAL
Begin Write,Latch CA,
Determine Auto-Precharge
Terminate Burst,Latch CA,
Begin New Read,Determine
Auto-Precharge*3
Terminate Burst,Latch CA,
Begin Write,Determine AutoPrecharge*3
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MITSUBISHI LSIs
MH8S72BCFD-6
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
FUNCTION TRUTH TABLE(continued)
Current State /S /RAS /CAS /WE Address Command Action
WRITE
READ with
AUTO
PRECHARGE
H X X X X DESEL NOP(Continue Burst to END)
L H H H X NOP NOP(Continue Burst to END)
L H H L BA TBST Terminate Burst
Terminate Burst,Latch CA,
L H L H BA,CA,A10 READ/READA
L H L L BA,CA,A10
L L H H BA,RA ACT Bank Active/ILLEGAL*2
L L H L BA,A10 PRE/PREA Terminate Burst,Precharge
L L L H X REFA ILLEGAL
Op-Code,
L L L L
H X X X X DESEL NOP(Continue Burst to END)
L H H H X NOP NOP(Continue Burst to END)
L H H L BA TBST ILLEGAL
L H L H BA,CA,A10 READ/READA ILLEGAL
Mode-Add
WRITE/
WRITEA
MRS ILLEGAL
Begin Read,Determine AutoPrecharge*3
Terminate Burst,Latch CA,
Begin Write,Determine AutoPrecharge*3
WRITE with
AUTO
PRECHARGE
L H L L BA,CA,A10
L L H H BA,RA ACT Bank Active/ILLEGAL*2
L L H L BA,A10 PRE/PREA ILLEGAL*2
L L L H X REFA ILLEGAL
L L L L
H X X X X DESEL NOP(Continue Burst to END)
L H H H X NOP NOP(Continue Burst to END)
L H H L BA TBST ILLEGAL
L H L H BA,CA,A10 READ/READA ILLEGAL
L H L L BA,CA,A10
L L H H BA,RA ACT Bank Active/ILLEGAL*2
L L H L BA,A10 PRE/PREA ILLEGAL*2
L L L H X REFA ILLEGAL
L L L L
Op-Code,
Mode-Add
Op-Code,
Mode-Add
WRITE/
WRITEA
MRS ILLEGAL
WRITE/
WRITEA
MRS ILLEGAL
ILLEGAL
ILLEGAL
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MH8S72BCFD-6
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
FUNCTION TRUTH TABLE(continued)
Current State /S /RAS /CAS /WE Address Command Action
PRE - H X X X X DESEL NOP(Idle after tRP)
CHARGING L H H H X NOP NOP(Idle after tRP)
L H H L BA TBST ILLEGAL*2
L H L X BA,CA,A10 READ/WRITE ILLEGAL*2
L L H H BA,RA ACT ILLEGAL*2
L L H L BA,A10 PRE/PREA NOP*4(Idle after tRP)
L L L H X REFA ILLEGAL
L L L L
ROW H X X X X DESEL NOP(Row Active after tRCD
ACTIVATING L H H H X NOP NOP(Row Active after tRCD
L H H L BA TBST ILLEGAL*2
L H L X BA,CA,A10 READ/WRITE ILLEGAL*2
L L H H BA,RA ACT ILLEGAL*2
L L H L BA,A10 PRE/PREA ILLEGAL*2
L L L H X REFA ILLEGAL
L L L L
Op-Code,
Mode-Add
Op-Code,
Mode-Add
MRS ILLEGAL
MRS ILLEGAL
WRITE RE- H X X X X DESEL NOP
COVERING L H H H X NOP NOP
L H H L BA TBST ILLEGAL*2
L H L X BA,CA,A10 READ/WRITE ILLEGAL*2
L L H H BA,RA ACT ILLEGAL*2
L L H L BA,A10 PRE/PREA ILLEGAL*2
L L L H X REFA ILLEGAL
L L L L
MIT-DS-0312-0.0
Op-Code,
Mode-Add
MITSUBISHI
MRS ILLEGAL
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MITSUBISHI LSIs
MH8S72BCFD-6
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
FUNCTION TRUTH TABLE(continued)
Current State /S /RAS /CAS /WE Address Command Action
RE- H X X X X DESEL NOP(Idle after tRC)
FRESHING L H H H X NOP
L H H L BA TBST ILLEGAL
L H L X BA,CA,A10 READ/WRITE ILLEGAL
L L H H BA,RA ACT ILLEGAL
L L H L BA,A10 PRE/PREA ILLEGAL
L L L H X REFA ILLEGAL
NOP(Idle after tRC)
L L L L
MODE H X X X X DESEL NOP(Idle after tRSC)
REGISTER L H H H X NOP NOP(Idle after tRSC)
SETTING L H H L BA TBST ILLEGAL
L H L X BA,CA,A10 READ/WRITE ILLEGAL
L L H H BA,RA ACT ILLEGAL
L L H L BA,A10 PRE/PREA ILLEGAL
L L L H X REFA ILLEGAL
L L L L
Op-Code,
MRS ILLEGAL
Mode-Add
Op-Code,
MRS ILLEGAL
Mode-Add
ABBREVIATIONS:
H = Hige Level, L = Low Level, X = Don't Care
BA = Bank Address, RA = Row Address, CA = Column Address, NOP = No Operation
NOTES:
1. All entries assume that CKE was High during the preceding clock cycle and the current
clock cycle.
2. ILLEGAL to bank in specified state; function may be legal in the bank indicated by BA,
depending on the state of that bank.
3. Must satisfy bus contention, bus turn around, write recovery requirements.
4. NOP to bank precharging or in idle state.May precharge bank indicated by BA.
5. ILLEGAL if any bank is not idle.
ILLEGAL = Device operation and / or date-integrity are not guaranteed.
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MITSUBISHI LSIs
MH8S72BCFD-6
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
FUNCTION TRUTH TABLE FOR CKE
CKE
Current State
SELF - H X X X X X X INVALID
REFRESH*1 L H H X X X X Exit Self-Refresh(Idle after tRC)
POWER H X X X X X X INVALID
DOWN L H X X X X X Exit Power Down to Idle
CKE
n-1
n
L H L H H H X Exit Self-Refresh(Idle after tRC)
L H L H H L X ILLEGAL
L H L H L X X ILLEGAL
L H L L X X X ILLEGAL
L L X X X X X NOP(Maintain Self-Refresh)
L L X X X X X NOP(Maintain Self-Refresh)
/RAS /CAS /WE Add Action
/S
ALL BANKS H H X X X X X Refer to Function Truth Table
IDLE*2 H L L L L H X Enter Self-Refresh
H L H X X X X Enter Power Down
H L L H H H X Enter Power Down
H L L H H L X ILLEGAL
H L L H L X X ILLEGAL
H L L L X X X ILLEGAL
L X X X X X X Refer to Current State = Power Down
ANY STATE H H X X X X X Refer to Function Truth Table
other than H L X X X X X Begin CK0 Suspend at Next Cycle*3
listed above L H X X X X X Exit CK0 Suspend at Next Cycle*3
L L X X X X X Maintain CK0 Suspend
ABBREVIATIONS:
H = High Level, L = Low Level, X = Don't Care
NOTES:
1. CKE Low to High transition will re-enable CK and other inputs asynchronously.
A minimum setup time must be satisfied before any command other than EXIT.
2. Power-Down and Self-Refresh can be entered only form the All banks idle State.
3. Must be legal command.
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MITSUBISHI LSIs
POWER ON SEQUENCE
MODE REGISTER
MH8S72BCFD-6
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Before starting normal operation, the following power on sequence is necessary to prevent
a SDRAM from damaged or malfunctioning.
1. Clock will be applied at power up along with power. Attempt to maintain CKE high, DQMB
high and NOP condition at the inputs along with power.
2. Maintain stable power, stable cock, and NOP input conditions for a minimum of 200µs.
3. Issue precharge commands for all banks. (PRE or PREA)
4. After all banks become idle state (after tRP), issue 8 or more auto-refresh commands.
5. Issue a mode register set command to initialize the mode register.
After these sequence, the SDRAM is idle state and ready for normal operation.
Burst Length, Burst Type and /CAS Latency can be programmed by setting the mode
register(MRS). The mode register stores these date until the next MRS command, which
may be issue when both banks are in idle state. After tRSC from a MRS command, the
SDRAM is ready for new command.
CK
LATENCY
MODE
WRITE
MODE
A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0BA1BA0
0 0 WM 0 0
00
CL
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
0
1
/CAS LATENCY
BURST
SINGLE BIT
/S
/RAS
/CAS
LTMODE BT BL
BA0,1 A11-0
BL
0 0 0
0 0 1
0 1 0
R
R
2
3
R
R
R
R
BURST
LENGTH
BURST
TYPE
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
0
1
/WE
BT= 0 BT= 1
1
2
4
8
R
R
R
FP
SEQUENTIAL
INTERLEAVED
V
1
2
4
8
R
R
R
R
R:Reserved for Future Use
FP: Full Page
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CK
Command
MITSUBISHI LSIs
MH8S72BCFD-6
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Read
Write
Address
DQ
Initial Address
A2 A1 A0
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
CL= 3
BL= 4
BL
8
Y
Q0 Q1 Q2 Q3
/CAS
Latency
Sequential Interleaved
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
1 2 3 4 5 6 7 0 1 0 3 2 5 4 7 6
2 3 4 5 6 7 0 1 2 3 0 1 6 7 4 5
3 4 5 6 7 0 1 2 3 2 1 0 7 6 5 4
4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3
5 6 7 0 1 2 3 4 5 4 7 6 1 0 3 2
Burst
Length
Column Addressing
Burst Type
Y
D0 D1 D2 D3
Burst
Length
1 1 0
1 1 1
- 0 0
- 0 1
- 1 0
- 1 1
- - 0
- - 1
MIT-DS-0312-0.0
6 7 0 1 2 3 4 5 6 7 4 5 2 3 0 1
7 0 1 2
0 1 2 3
1 2 3 0
4
2 3 0 1
3 0
0 1
2
1 0
3 4 5 6 3 2 1 0
1 2
7 6 5 4
0 1 2 3
1 0 3 2
2 3 0 1
3 2
0 1
1 0
1 0
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MITSUBISHI LSIs
ABSOLUTE MAXIMUM RATINGS
RECOMMENDED OPERATING CONDITION
CAPACITANCE
MH8S72BCFD-6
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Symbol Parameter Condition Ratings Unit
Vdd
VI
VO
IO
Pd
Topr
Tstg
(Ta=0 ~ 70C, unless otherwise noted)
Symbol
Vdd
Vss
VIH*1
Supply Voltage
Input Voltage
Output Voltage
Output Current
Power Dissipation
Operating Temperature
Storage Temperature
Parameter
Supply Voltage
Supply Voltage
High-Level Input Voltage all inputs
with respect to Vss
with respect to Vss
with respect to Vss
Ta=25C
Min. Typ. Max.
3.0
0
2.0
Limits
3.3
0
-0.5 ~ 4.6
-0.5 ~ 4.6
-0.5 ~ 4.6
50
13
0 ~ 70
-45 ~ 100
3.6
0
Vdd+0.3
V
V
V
mA
W
C
C
Unit
V
V
V
VIL*2
NOTES)
1. VIH(max)= Vdd-2.0V AC for pulse width less than 3ns acceptable.
2. VIL('min)= -2.0V AC for pulse width less than 3ns acceotable.
(Ta=0 ~ 70C, Vdd = 3.3 +/- 0.3V, Vss = 0V, unless otherwise noted)
Symbol
CI(A)
CI(C)
CI(K)
CI/O
MIT-DS-0312-0.0
Low-Level Input Voltage all inputs
Parameter
Input Capacitance, address pin
Input Capacitance, control pin
Input Capacitance, CK0 pin
Input Capacitance, I/O pin
MITSUBISHI
ELECTRIC
-0.3
Test Condition Limits(max.) Unit
1MHz,
1.4V bias
200mV swing
20
20
20
16.5
0.8
pF
pF
pF
pF
9/May. /1999
V
14
Page 15
MH8S72BCFD-6
AVERAGE SUPPLY CURRENT from Vdd
AC OPERATING CONDITIONS AND CHARACTERISTICS
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
(Ta=0 ~70C, Vdd = 3.3 ± 0.3V, Vss = 0V, unless otherwise noted)
MITSUBISHI LSIs
Parameter
operating current
single bank operation (discrete)
precharge stanby current in
Non power-down mode
precharge stanby current
in Power-down mode
active stanby current
in Non Power Down Mode
active stanby current
in Power Down Mode
burst current
auto-refresh current
self-refresh current
Note)
1.Icc(max) is specified at the output open condition.
2.Input signal are changed one time during 30ns.
Symbol
Icc1
Icc2N
Icc2NS
Icc2P
Icc2PS
Icc3N
Icc3P
Icc4
Icc5
Icc6
Test Condition
tRC=min.tCLK=min, BL=1, CL=3,IOL=0mA
CKE=VIHmin,tCLK=15ns
CLK=VILmax,CKE=VIHmin (fixed)
CKE=VILmax,tCLK=15ns
CKE=CLK=VILmax(fixed)
CKE=/CS=VIHmin,tCLK=15ns
CKE=/CS=VIHmin,CLK=VILmax(fixed)
CKE=VILmax,tCLK=15ns
CKE=CLK=VILmax(fixed)
tCLK=min, BL=4, CL=3, IOL=0mA
all banks active(discerte)
tRFC=min, tCLK=min 1384 mA
CKE <0.2V 43 mA
Limits
(max)
1114 mA
1339 mA
Unit
259 mA
214 mA
70 mA
43 mA
529 mA
394 mAIcc3NS
70 mA
43 mAIcc3PS
Note
*1
*1,2
*1
*1,2
*1
*1,2
*1
*1,2
*1
*1
*1
*1
(Ta=0 ~ 70C, Vdd = 3.3 ± 0.3V, Vss = 0V, unless otherwise noted)
Symbol Parameter Test Condition
VOH(DC) High-Level Output Voltage(DC) IOH=-2mA 2.4 V
VOL(DC) Low-Level Output Voltage(DC) IOL=2mA
IOZ Off-stare Output Current Q floating VO=0 ~ Vdd
Ii Input Current VIH=0 ~ Vdd+0.3V -10 10 uA
MIT-DS-0312-0.0
MITSUBISHI
Limits
Min. Max.
-10
ELECTRIC
Unit
0.4 V
uA
10
9/May. /1999
15
Page 16
MH8S72BCFD-6
AC TIMING REQUIREMENTS
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
(Ta=0 ~ 70C, Vdd = 3.3 +/- 0.3V, Vss = 0V, unless otherwise noted)
Input Pulse Levels: 0.8V to 2.0V
Input Timing Measurement Level: 1.4V
LATCH MODE
Symbol Parameter
tCLK CK cycle time
tCH CK High pulse width
tCL CK Low pulse width
tT Transition time of CK
tIS Input Setup time(all inputs)
tIH Input Hold time(all inputs)
tRC Row Cycle time
tRFC Row Refresh Cycle time
tRCD Row to Column Delay
tRAS Row Active time
tRP Row Precharge time
tWR
Write Recovery time
tRRD Act to Act Deley time
tRSC Mode Register Set Cycle time
tSRX Self Refresh Exit time
tPDE Power Down Exit time
tREF Refresh Interval time
CL=3
CL=4
Min. Max.
67.5
22.5
22.5
MITSUBISHI LSIs
Limits
Unit
7.5
-
2.5
2.5
1.5
0.8
80
45
15
15
15
7.5
7.5
1
10
100K
64
ns
ns
ns
ns
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CK
Signal
MIT-DS-0312-0.0
MITSUBISHI
ELECTRIC
1.4V
1.4V
Any AC timing is
referenced to the input
signal crossing
through 1.4V.
9/May. /1999
16
Page 17
MITSUBISHI LSIs
MH8S72BCFD-6
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
BUFFER MODE
Limits
Symbol Parameter
CL=2
tCLK CK cycle time
CL=3
tCH CK High pulse width ns
tCL CK Low pulse width
tT Transition time of CK
tIS Input Setup time(all inputs)
tIH Input Hold time(all inputs) ns
tRC Row Cycle time
tRFC Row Refresh Cycle time
tRCD Row to Column Delay
tRAS Row Active time
tRP Row Precharge time
tWR
Write Recovery time
tRRD Act to Act Deley time
tRSC Mode Register Set Cycle time
tSRX Self Refresh Exit time
tPDE Power Down Exit time
tREF Refresh Interval time
Min. Max.
7.5
-
2.5
2.5
1
6.5
0
67.5
80
22.5
45
22.5
15
15
15
7.5
7.5
10
100K
64
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
SWITCHING CHARACTERISTICS
(Ta=0 ~ 70C, Vdd = 3.3 +/- 0.3V, Vss = 0V, unless otherwise noted)
LATCH MODE
Symbol
Parameter
CL=3
Min. Max.
5.4
tAC Access time from CK
CL=4
Limits
tOH Output Hold time from CK
2.7
Delay time, output low
tOLZ
tOHZ
impedance from CK
Delay time, output high
impedance from CK
0
2.7 5.4
NOTE)
1.If clock rising time is longer than 1ns, (tr /2-0.5ns) should be added to the parameter.
MIT-DS-0312-0.0
MITSUBISHI
ELECTRIC
-
9/May. /1999
Unit
ns
ns
ns
ns
Note
*1
17
Page 18
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
BUFFER MODE
MITSUBISHI LSIs
MH8S72BCFD-6
Limits
Symbol Parameter
Min. Max.
tAC Access time from CK
tOH Output Hold time from CK
tOLZ
Delay time, output low
impedance from CK
CL=2
CL=3
2.7
0
5.4
-
Delay time, output high
tOHZ
impedance from CK
2.7 5.4
NOTE)
1.If clock rising time is longer than 1ns, (tr /2-0.5ns) should be added to the parameter.
Output Load Condition
CK
Unit
ns
ns
ns
ns
Note
*1
1.4V
VOUT
MIT-DS-0312-0.0
Ext.CL=50pF
CK
tAC tOH
Output Timing
Measurement
Reference Point
tOHZ
MITSUBISHI
ELECTRIC
DQ
1.4V
1.4VDQ
9/May. /1999
1.4V
18
Page 19
CLK
/CS
MITSUBISHI LSIs
MH8S72BCFD-6
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Burst WRITE (single bank)
BL=4,Buffer mode(REGE="L")
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
tRC
/RAS
/CAS
/WE
CKE
DQM
A0-9
A10
A11
tRAS
tRCD
tWR
X
X
X
Y
tRP
tRCD
X
X
X
Y
BA0,1
REGE
DQ
MIT-DS-0312-0.0
0
ACT#0 WRITE#0 PRE#0 ACT#0 WRITE#0
0 0
D0 D0 D0 D0
Italic parameter indicates minimum case
MITSUBISHI
0
0
D0 D0 D0 D0
9/May. /1999
ELECTRIC
19
Page 20
CLK
/CS
/RAS
MITSUBISHI LSIs
MH8S72BCFD-6
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Burst WRITE (multi bank)
BL=4,Buffer mode(REGE="L")
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
tRC
tRRD
tRAS
tRP
tRRD
/CAS
/WE
CKE
DQM
A0-9
A10
A11
BA0,1
tRCD
tWR
X
X
X
0
Y
X
X
X
0 1
1
Y
tWR
0
tRCD
X
X
X
0
1
Y
X
X
X
0
2
REGE
DQ
MIT-DS-0312-0.0
D0 D0 D0 D0
ACT#0 WRITE#0 PRE#0 ACT#0 WRITE#0
ACT#1 WRITE#1 PRE#1
D1 D1 D1 D1
ACT#2
Italic parameter indicates minimum case
MITSUBISHI
D0 D0 D0 D0
9/May. /1999
ELECTRIC
20
Page 21
CLK
/CS
MITSUBISHI LSIs
MH8S72BCFD-6
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Burst WRITE (single bank)
BL=4,Lacth mode(REGE="H")
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
tRC
/RAS
/CAS
/WE
CKE
DQM
A0-9
A10
A11
tRAS
tRCD
tWR
X
X
X
Y
tRP
tRCD
X
X
X
Y
BA0,1
REGE
DQ
MIT-DS-0312-0.0
0
ACT#0 WRITE#0 PRE#0 ACT#0 WRITE#0
0 0
D0 D0 D0 D0
0
Italic parameter indicates minimum case
0
D0 D0 D0 D0
MITSUBISHI
ELECTRIC
9/May. /1999
21
Page 22
CLK
/CS
/RAS
MITSUBISHI LSIs
MH8S72BCFD-6
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Burst WRITE (multi bank)
BL=4,Latch mode(REGE="H")
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
tRC
tRRD
tRAS
tRP
tRRD
/CAS
/WE
CKE
DQM
A0-9
A10
A11
BA0,1
tRCD
tWR
X
X
X
0
Y
X
X
X
0 1
1
Y
tWR
0
tRCD
X
X
X
0
1
Y
X
X
X
0
2
REGE
DQ
MIT-DS-0312-0.0
D0 D0 D0 D0
ACT#0 WRITE#0 PRE#0 ACT#0 WRITE#0
ACT#1 WRITE#1 PRE#1
D1 D1 D1 D1
ACT#2
Italic parameter indicates minimum case
MITSUBISHI
D0 D0 D0
9/May. /1999
ELECTRIC
22
Page 23
CLK
/CS
/RAS
MITSUBISHI LSIs
MH8S72BCFD-6
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Burst READ (single bank)
BL=4,CL=3,Buffer mode(REGE="L")
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
tRC
tRAS tRP
/CAS
/WE
CKE
DQM
A0-9
A10
A11
BA0,1
tRCD
DQM read latency =2
X
X
X
0
Y
0 0
tRCD
X
X
X
0
Y
0
REGE
DQ
MIT-DS-0312-0.0
CL=3
Q0 Q0 Q0 Q0
ACT#0 READ#0 PRE#0 ACT#0 READ#0
READ to PRE ³BL allows full data out
Italic parameter indicates minimum case
MITSUBISHI
ELECTRIC
Q0 Q0
9/May. /1999
23
Page 24
CLK
/CS
/RAS
MITSUBISHI LSIs
MH8S72BCFD-6
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Burst READ (multi bank)
BL=4,CL=3,Buffer mode(REGE="L")
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
tRC
tRRD
tRAS tRP
tRRD
/CAS
/WE
CKE
DQM
A0-9
A10
A11
BA0,1
tRCD
DQM read latency =2
X
X
X
0
Y
X
X
X
0 0
1
Y
1
tRCD
X
X
X
0
Y
X
X
X
0
21
REGE
DQ
ACT#0 READ#0 PRE#0 ACT#0 READ#0
MIT-DS-0312-0.0
ACT#1
CL=3
CL=3
Q0 Q0 Q0 Q0
READ#1 PRE#1 ACT#2
Q1 Q1 Q1 Q1
Italic parameter indicates minimum case
MITSUBISHI
ELECTRIC
9/May. /1999
Q0
24
Page 25
CLK
/CS
/RAS
MITSUBISHI LSIs
MH8S72BCFD-6
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Burst READ (single bank)
BL=4, CL=4,Latch mode(REGE="H")
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
tRC
tRAS tRP
/CAS
/WE
CKE
DQM
A0-9
A10
A11
BA0,1
tRCD
DQM read latency =3
X
X
X
0
Y
0 0
tRCD
X
X
X
0
Y
0
REGE
DQ
MIT-DS-0312-0.0
CL=4
Q0 Q0 Q0 Q0
ACT#0 READ#0 PRE#0 ACT#0 READ#0
READ to PRE ³BL allows full data out
Italic parameter indicates minimum case
MITSUBISHI
ELECTRIC
9/May. /1999
Q0
25
Page 26
CLK
/CS
/RAS
MITSUBISHI LSIs
MH8S72BCFD-6
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Burst READ (multi bank)
BL=4,CL=4,Latch mode(REGE="H")
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
tRC
tRRD
tRAS tRP
tRRD
/CAS
/WE
CKE
DQM
A0-9
A10
A11
BA0,1
tRCD
DQM read latency =3
X
X
X
0
Y
X
X
X
0 0
1
Y
1
tRCD
X
X
X
0
Y
X
X
X
0
21
REGE
DQ
ACT#0 READ#0 PRE#0 ACT#0 READ#0
MIT-DS-0312-0.0
ACT#1
CL=4
CL=4
Q0 Q0 Q0 Q0
READ#1 PRE#1 ACT#2
Italic parameter indicates minimum case
Q1 Q1 Q1 Q1
MITSUBISHI
ELECTRIC
9/May. /1999
26
Page 27
CLK
/CS
MITSUBISHI LSIs
MH8S72BCFD-6
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Burst WRITE (multi bank) with AUTO-PRECHARGE
BL=4,Buffer mode(REGE="L")
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
tRC
/RAS
/CAS
/WE
CKE
DQM
A0-9
A10
A11
tRRD
tRCD
BL-1+ tWR + tRP
BL-1+ tWR + tRP
X
X
X
Y
X
X
X
Y X
X
X
tRRD
tRCD
tRCD
Y
X
X
X
Y
BA0,1
REGE
DQ
MIT-DS-0312-0.0
0
ACT#0 WRITE#0 with
ACT#1 WRITE#1 with
0 1
1
D0 D0 D0 D0
AutoPrecharge
D1 D1 D1 D1
AutoPrecharge
ACT#0 WRITE#0
Italic parameter indicates minimum case
MITSUBISHI
ELECTRIC
0
0
1
D0 D0 D0 D0
ACT#1 WRITE#1
9/May. /1999
1
D1
27
Page 28
CLK
/CS
MITSUBISHI LSIs
MH8S72BCFD-6
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Burst WRITE (multi bank) with AUTO-PRECHARGE
BL=4,Latch mode(REGE="H")
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
tRC
/RAS
/CAS
/WE
CKE
DQM
A0-9
A10
A11
tRRD
tRCD
BL-1+ tWR + tRP
BL-1+ tWR + tRP
X
X
X
Y
X
X
X
Y X
X
X
tRRD
tRCD
tRCD
Y
X
X
X
Y
BA0,1
REGE
DQ
MIT-DS-0312-0.0
0
ACT#0 WRITE#0 with
ACT#1 WRITE#1 with
0 1
1
D0 D0 D0 D0
AutoPrecharge
AutoPrecharge
D1 D1 D1 D1
ACT#0 WRITE#0
Italic parameter indicates minimum case
MITSUBISHI
ELECTRIC
0
0
1
D0 D0 D0 D0
ACT#1 WRITE#1
9/May. /1999
1
28
Page 29
CLK
/CS
MITSUBISHI LSIs
MH8S72BCFD-6
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Burst READ (multi bank) with AUTO-PRECHARGE
BL=4,CL=3 Buffer mode(REGE="L")
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
tRC
/RAS
/CAS
/WE
CKE
DQM
A0-9
A10
A11
X
X
X
tRRD
tRCD
tRRD
tRCD
BL+tRP
BL+tRP
DQM read latency =2
Y
X
X
X
Y
X
X
X
Y
tRCD
X
X
X
Y
BA0,1
REGE
DQ
MIT-DS-0312-0.0
0
ACT#0 READ#0 with
ACT#1
0
1
Auto-Precharge
CL=3
1
CL=3
Q0 Q0 Q0 Q0
READ#1 with
Auto-Precharge
MITSUBISHI
ELECTRIC
0
Q1 Q1 Q1 Q1
ACT#0 READ#0
Italic parameter indicates minimum case
0
1
CL=3
ACT#1
9/May. /1999
Q0
1
Q0
29
Page 30
CLK
/CS
MITSUBISHI LSIs
MH8S72BCFD-6
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Burst READ (multi bank) with AUTO-PRECHARGE
BL=4,CL=4 Latch mode(REGE="H")
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
tRC
/RAS
/CAS
/WE
CKE
DQM
A0-9
A10
A11
X
X
X
tRRD
tRCD
DQM read latency =3
Y
X
X
X
BL+tRP
Y
BL+tRP
X
X
X
tRRD
tRCD
tRCD
Y
X
X
X
Y
BA0,1
REGE
DQ
MIT-DS-0312-0.0
0
ACT#0 READ#0 with
ACT#1
0
1
Auto-Precharge
CL=4
1
CL=4
Q0 Q0 Q0 Q0
ACT#0 READ#0
READ#1 with
Auto-Precharge
Italic parameter indicates minimum case
MITSUBISHI
ELECTRIC
0
Q1 Q1 Q1 Q1
0
1
CL=4
ACT#1
9/May. /1999
1
Q0
30
Page 31
CLK
/CS
/RAS
/CAS
/WE
MITSUBISHI LSIs
MH8S72BCFD-6
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Page Mode Burst Write (multi bank)
BL=4,Buffer mode(REGE="L")
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
tRRD
tRCD
CKE
DQM
A0-9
A10
A11
BA0,1
REGE
DQ
X
X
X
0
Y
X
X
X
0 0
1
D0 D0 D0 D0
Y Y
D0 D0 D0 D0 D0 D0 D0
Y
1
D1 D1 D1 D1
0
ACT#0 WRITE#0 WRITE#0
MIT-DS-0312-0.0
ACT#1
WRITE#0
MITSUBISHI
ELECTRIC
WRITE#1
Italic parameter indicates minimum case
9/May. /1999
31
Page 32
CLK
/CS
/RAS
/CAS
/WE
MITSUBISHI LSIs
MH8S72BCFD-6
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Page Mode Burst Write (multi bank)
BL=4,Latch mode(REGE="H")
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
tRRD
tRCD
CKE
DQM
A0-9
A10
A11
BA0,1
REGE
DQ
X
X
X
0
Y
X
X
X
0 0
1
D0 D0 D0 D0
Y Y
D0 D0 D0 D0 D0 D0
Y
1
D1 D1 D1 D1
0
ACT#0 WRITE#0 WRITE#0
MIT-DS-0312-0.0
ACT#1
WRITE#0
Italic parameter indicates minimum case
MITSUBISHI
ELECTRIC
WRITE#1
9/May. /1999
32
Page 33
CLK
/CS
/RAS
/CAS
/WE
MITSUBISHI LSIs
MH8S72BCFD-6
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Page Mode Burst Read (multi bank)
BL=4,CL=3 Buffer mode(REGE="L")
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
tRRD
tRCD
CKE
DQM
A0-9
A10
A11
BA0,1
REGE
DQ
DQM read latency=2
X
X
X
0
Y
X
X
X
0 0
1
CL=3 CL=3 CL=3
Y Y
Q0 Q0 Q0
Q0
Y
1
Q0 Q0 Q0 Q0
0
Q1 Q1 Q1 Q1
ACT#0 READ#0 READ#0
MIT-DS-0312-0.0
ACT#1
READ#0
MITSUBISHI
ELECTRIC
READ#1
Italic parameter indicates minimum case
9/May. /1999
33
Page 34
CLK
/CS
/RAS
/CAS
/WE
MITSUBISHI LSIs
MH8S72BCFD-6
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Page Mode Burst Read (multi bank)
BL=4,CL=4 Latch mode(REGE="H")
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
tRRD
tRCD
CKE
DQM
A0-9
A10
A11
BA0,1
REGE
DQ
DQM read latency=3
X
X
X
0
Y
X
X
X
0 0
1
CL=4 CL=4 CL=4
Y Y
Q0 Q0 Q0
Q0
Y
1
Q0 Q0 Q0 Q0
0
Q1 Q1 Q1
ACT#0 READ#0 READ#0
MIT-DS-0312-0.0
ACT#1
READ#0
MITSUBISHI
ELECTRIC
READ#1
Italic parameter indicates minimum case
9/May. /1999
34
Page 35
CLK
/CS
/RAS
MITSUBISHI LSIs
MH8S72BCFD-6
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Write Interrupted by Write / Read
BL=4,Buffer mode(REGE="L")
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
tRRD
/CAS
/WE
CKE
DQM
A0-9
A10
A11
BA0,1
tRCD
X
X
X
0
Y
X
X
X
0
1
tCCD
Y Y
0 0 0
Y
1
Y
REGE
CL=3
DQ
ACT#0 WRITE#0
ACT#1
Burst Write can be interrupted by Write or Read of any active bank.
MIT-DS-0312-0.0 35
D0 D0 D0 D0
WRITE#0 READ#0
D0 D0 D1 D1 Q0 Q0 Q0
WRITE#0
WRITE#1
Italic parameter indicates minimum case
MITSUBISHI
Q0
9/May. /1999
ELECTRIC
Page 36
CLK
/CS
/RAS
MITSUBISHI LSIs
MH8S72BCFD-6
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Write Interrupted by Write / Read
BL=4,Latch mode(REGE="H")
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
tRRD
/CAS
/WE
CKE
DQM
A0-9
A10
A11
BA0,1
tRCD
X
X
X
0
Y
X
X
X
0
1
tCCD
Y Y
0 0 0
Y
1
Y
REGE
DQ
MIT-DS-0312-0.0
D0 D0 D0 D0
ACT#0 WRITE#0
ACT#1
Burst Write can be interrupted by Write or Read of any active bank.
WRITE#0 READ#0
D0 D0 D1 D1 Q0 Q0 Q0
WRITE#0
WRITE#1
Italic parameter indicates minimum case
MITSUBISHI
ELECTRIC
CL=4
9/May. /1999
36
Page 37
CLK
/CS
/RAS
/CAS
/WE
MITSUBISHI LSIs
MH8S72BCFD-6
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Read Interrupted by Read / Write
BL=4,CL=3 Buffer mode(REGE="L")
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
tRRD
tRCD
CKE
DQM
A0-9
A10
A11
BA0,1
DQ
REGE
DQM read latency=2
X
X
X
0
Y
X
X
X
0 0
1
Y Y
Y
0
Q0 Q0 Q0
Q0
Y
1
Y
0
Q0 Q0 Q1 Q1
Q0 D0 D0
0
ACT#0 READ#0 WRITE#0
MIT-DS-0312-0.0
READ#0 READ#0
ACT#1
Burst Read can be interrupted by Read or Write of any active bank.
READ#0
READ#1
Italic parameter indicates minimum case
blank to prevent bus contention
MITSUBISHI
ELECTRIC
9/May. /1999
37
Page 38
CLK
/CS
/RAS
/CAS
/WE
MITSUBISHI LSIs
MH8S72BCFD-6
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Read Interrupted by Read / Write
BL=4,CL=4 Latch mode(REGE="H")
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
tRRD
tRCD
CKE
DQM
A0-9
A10
A11
BA0,1
DQ
REGE
DQM read latency=3
X
X
X
0
Y
X
X
X
0 0
1
Y Y
Y
0
Q0 Q0 Q0
Y
1
Q0
Y
0
Q0 Q0 Q1 Q1
Q0 D0
0
ACT#0 READ#0 WRITE#0
MIT-DS-0312-0.0
READ#0 READ#0
ACT#1
Burst Read can be interrupted by Read or Write of any active bank.
READ#0
READ#1
Italic parameter indicates minimum case
blank to prevent bus contention
MITSUBISHI
ELECTRIC
9/May. /1999
38
Page 39
CLK
/CS
/RAS
/CAS
/WE
MITSUBISHI LSIs
MH8S72BCFD-6
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Write Interrupted by Precharge
BL=4,Buffer mode(REGE="L")
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
tRRD
tRCD
CKE
DQM
A0-9
A10
A11
BA0,1
DQ
REGE
X
X
X
0
Y
X
X
X
0
1
D0 D0 D0 D0
Y
1 1
D1 D1 D1 D1 D1
1
0
X
X
X
1
Y
ACT#0 WRITE#0
MIT-DS-0312-0.0
ACT#1
Burst Write is not interrupted
by Precharge of the other bank.
WRITE#1
PRE#0
PRE#1
Italic parameter indicates minimum case
MITSUBISHI
ELECTRIC
ACT#1 WRITE#1
Burst Write is interrupted by
Precharge of the same bank.
9/May. /1999
39
Page 40
CLK
/CS
/RAS
/CAS
/WE
MITSUBISHI LSIs
MH8S72BCFD-6
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Write Interrupted by Precharge
BL=4,Latch mode(REGE="H")
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
tRRD
tRCD
CKE
DQM
A0-9
A10
A11
BA0,1
DQ
REGE
X
X
X
0
Y
X
X
X
0
1
D0 D0 D0 D0
Y
1 1
1
0
D1 D1 D1 D1
X
X
X
1
Y
ACT#0 WRITE#0
MIT-DS-0312-0.0
ACT#1
Burst Write is not interrupted
by Precharge of the other bank.
WRITE#1
PRE#0
PRE#1
Italic parameter indicates minimum case
MITSUBISHI
ELECTRIC
ACT#1 WRITE#1
Burst Write is interrupted by
Precharge of the same bank.
9/May. /1999
40
Page 41
CLK
/CS
/RAS
/CAS
/WE
MITSUBISHI LSIs
MH8S72BCFD-6
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Read Interrupted by Precharge
BL=4,CL=3 Buffer mode(REGE="L")
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
tRRD
tRCD
tRP
tRCD
CKE
DQM
A0-9
A10
A11
BA0,1
DQ
REGE
DQM read latency=2
X
X
X
0
Y
X
X
X
0
1
Y
1
0
Q0 Q0 Q0
Q0
1
X
X
X
1
Q1 Q1
Y
1
ACT#0 READ#0
MIT-DS-0312-0.0
ACT#1
Burst Read is not interrupted
by Precharge of the other bank.
READ#1 ACT#1 READ#1
MITSUBISHI
ELECTRIC
PRE#0
PRE#1
Burst Read is interrupted
by Precharge of the same bank.
Italic parameter indicates minimum case
9/May. /1999
41
Page 42
CLK
/CS
MITSUBISHI LSIs
MH8S72BCFD-6
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Read Interrupted by Precharge
BL=4,CL=4 Latch mode(REGE="H")
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
/RAS
/CAS
/WE
CKE
DQM
A0-9
A10
A11
X
X
X
tRRD
tRCD
tRP
tRCD
DQM read latency=3
Y
X
X
X
Y
X
X
X
Y
BA0,1
DQ
REGE
MIT-DS-0312-0.0
0
ACT#0 READ#0
ACT#1
0
1
Burst Read is not interrupted
by Precharge of the other bank.
1
Q0 Q0 Q0
PRE#0
READ#1 ACT#1 READ#1
1
0
Q0
PRE#1
Burst Read is interrupted
by Precharge of the same bank.
Italic parameter indicates minimum case
1
Q1 Q1
MITSUBISHI
1
9/May. /1999
ELECTRIC
42
Page 43
CLK
/CS
/RAS
/CAS
/WE
MITSUBISHI LSIs
MH8S72BCFD-6
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Mode Register Setting
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
tRSC
tRC
tRCD
CKE
DQM
A0-9
A10
A11
BA0,1
DQ
REGE
M
0
X
X
X
0
Y
0
D0
D0 D0 D0
Auto-Ref (last of 8 cycles)
MIT-DS-0312-0.0
Mode
Register
Setting
Italic parameter indicates minimum case
MITSUBISHI
ELECTRIC
ACT#0 WRITE#0
9/May. /1999
43
Page 44
Auto-Refresh @BL=4
CLK
/CS
/RAS
/CAS
/WE
MITSUBISHI LSIs
MH8S72BCFD-6
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
tRC
tRCD
CKE
DQM
A0-9
A10
A11
BA0,1
DQ
REGE
X
X
X
0
Y
0
D0
D0 D0 D0
Auto-Refresh
Before Auto-Refresh,
all banks must be idle state.
MIT-DS-0312-0.0
ACT#0 WRITE#0
After tRC from Auto-Refresh,
all banks are idle state.
Italic parameter indicates minimum case
MITSUBISHI
ELECTRIC
9/May. /1999
44
Page 45
CLK
/CS
/RAS
/CAS
/WE
CKE
MITSUBISHI LSIs
MH8S72BCFD-6
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Self-Refresh
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK can be stopped
tSRX
CKE must be low to maintain Self-Refresh
tRC+1
DQM
A0-9
A10
A11
BA0,1
DQ
REGE
Self-Refresh Entry
X
X
X
0
Self-Refresh Exit ACT#0
Before Self-Refresh Entry,
all banks must be idle state.
MIT-DS-0312-0.0
After tRC from Self-Refresh Exit,
all banks are idle state.
Italic parameter indicates minimum case
MITSUBISHI
ELECTRIC
9/May. /1999
45
Page 46
CLK
/CS
/RAS
/CAS
/WE
MITSUBISHI LSIs
MH8S72BCFD-6
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
DQM Write Mask
BL=4,Buffer mode(REGE="L")
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
tRCD
CKE
DQM
A0-9
A10
A11
BA0,1
DQ
REGE
X
X
X
0
Y
0 0
D0 D0 D0 D0
Y
masked
Y
0
masked
D0 D0 D0
ACT#0 WRITE#0 WRITE#0 WRITE#0
MIT-DS-0312-0.0
Italic parameter indicates minimum case
MITSUBISHI
ELECTRIC
9/May. /1999
46
Page 47
CLK
/CS
/RAS
/CAS
/WE
MITSUBISHI LSIs
MH8S72BCFD-6
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
DQM Write Mask
BL=4,Latch mode(REGE="H")
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
tRCD
CKE
DQM
A0-9
A10
A11
BA0,1
DQ
REGE
X
X
X
0
Y
0 0
D0 D0 D0 D0
Y
masked
Y
0
masked
D0 D0 D0
ACT#0 WRITE#0 WRITE#0 WRITE#0
MIT-DS-0312-0.0
Italic parameter indicates minimum case
MITSUBISHI
ELECTRIC
9/May. /1999
47
Page 48
CLK
/CS
/RAS
/CAS
/WE
MITSUBISHI LSIs
MH8S72BCFD-6
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
DQM Read Mask
BL=4, CL=3 Buffer mode(REGE="L")
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
tRCD
CKE
DQM
A0-9
A10
A11
BA0,1
DQ
REGE
DQM read latency=2
X
X
X
0
Y
0 0
Q0 Q0 Q0 Q0
Y
Y
0
masked
masked
Q0 Q0 Q0
ACT#0 READ#0 READ#0 READ#0
MIT-DS-0312-0.0
Italic parameter indicates minimum case
MITSUBISHI
ELECTRIC
9/May. /1999
48
Page 49
CLK
/CS
/RAS
/CAS
/WE
MITSUBISHI LSIs
MH8S72BCFD-6
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
DQM Read Mask
BL=4,CL=4 Latch mode(REGE="H")
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
tRCD
CKE
DQM
A0-9
A10
A11
BA0,1
DQ
REGE
DQM read latency=3
X
X
X
0
Y
0 0
Y
Q0 Q0 Q0 Q0
Y
0
masked
masked
Q0 Q0
ACT#0 READ#0 READ#0 READ#0
MIT-DS-0312-0.0
Italic parameter indicates minimum case
MITSUBISHI
ELECTRIC
9/May. /1999
49
Page 50
CLK
/CS
/RAS
/CAS
/WE
MITSUBISHI LSIs
MH8S72BCFD-6
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Power Down
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CKE
DQM
A0-9
A10
A11
BA0,1
DQ
REGE
Standby Power Down
CKE latency=1
Active Power Down
X
X
X
0
Precharge All ACT#0
MIT-DS-0312-0.0
Italic parameter indicates minimum case
MITSUBISHI
ELECTRIC
9/May. /1999
50
Page 51
CLK Suspend
CLK
/CS
/RAS
/CAS
/WE
MITSUBISHI LSIs
MH8S72BCFD-6
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
BL=4,CL=3 Buffer mode(REGE="L")
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
tRCD
CKE
DQM
A0-9
A10
A11
BA0,1
DQ
REGE
CKE latency=1 CKE latency=1
X
X
X
0
Y
0 0
D0 D0 D0D0
Y
Q0 Q0 Q0 Q0
MIT-DS-0312-0.0
ACT#0 WRITE#0 READ#0
MITSUBISHI
ELECTRIC
CLK suspendedCLK suspended
Italic parameter indicates minimum case
9/May. /1999
51
Page 52
CLK Suspend
CLK
/CS
/RAS
/CAS
/WE
MITSUBISHI LSIs
MH8S72BCFD-6
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
BL=4,CL=4 Latch mode(REGE="H")
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
tRCD
CKE
DQM
A0-9
A10
A11
BA0,1
DQ
REGE
CKE latency=2 CKE latency=2
X
X
X
0
Y
0 0
D0 D0 D0D0
Y
Q0 Q0 Q0 Q0
MIT-DS-0312-0.0
ACT#0 WRITE#0 READ#0
MITSUBISHI
ELECTRIC
CLK suspendedCLK suspended
Italic parameter indicates minimum case
9/May. /1999
52
Page 53
MITSUBISHI LSIs
Serial Presence Detect Table I
SDRAM Cycletime at Max. Supported CAS Latency (CL).
ECC
buffered,registered with PLL
Write1/Read Burst
SDRAM Access form Clock(2nd highest CAS latency)
SDRAM Access form Clock(3rd highest CAS latency)
MH8S72BCFD-6
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Byte Function described SPD enrty data SPD DATA(hex)
0 # of Serial PD Bytes Written during Production 128 80
1 Total # of Bytes in SPD device 256 Bytes 08
2 Fundamental memory type SDRAM 04
3 # Row Addresses on this assembly A0-A11 0C
4 # Column Addresses on this assembly
5 # Module Banks on this assembly
6 Data Width of this assembly...
7 ... Data Width continuation 0 00
8 Voltage interface standard of this assembly LVTTL 01
9
Cycle time for CL=3
10 SDRAM Access from Clock
tAC for CL=3
11 DIMM Configuration type (Non-parity,Parity,ECC)
12 Refresh Rate/Type self refresh(15.625uS) 80
13 SDRAM width,Primary DRAM x8 08
14
Minimum Clock Delay,Back to Back Random Column Addresses
15
16
17 # Banks on Each SDRAM device 4bank 04
18
19
20
21 SDRAM Module Attributes
22 SDRAM Device Attributes:General
23 SDRAM Cycle time(2nd highest CAS latency)
Error Checking SDRAM data width x8 08
Burst Lengths Supported 1/2/4/8/Full page 8F
CAS# Latency
CS# Latency
Write Latency
Cycle time for CL=2
A0-A8
1BANK 01
x72 48
7.5ns
5.4ns 54
1 01
3 04
0 01
0 01
Precharge All,Auto precharge
N/A
09
75
02
1F
0E
00
24
tAC for CL=2
25 SDRAM Cycle time(3rd highest CAS latency) N/A 00
27 Precharge to Active Minimum 23ns(22.5ns) 17
28 Row Active to Row Active Min.
29 RAS to CAS Delay Min
30 Active to Precharge Min 45ns 2D
MIT-DS-0312-0.0
MITSUBISHI
N/A
N/A 0026
15ns 0F
23ns(22.5ns) 17
00
9/May. /1999
ELECTRIC
53
Page 54
MITSUBISHI LSIs
4D4838533732424346442D36202020202020
MH8S72BCFD-6
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Serial Presence Detect Table II
31 Density of each bank on module 64MByte 10
32 Command and Address signal input setup time 1.5ns 15
33 Command and Address signal input hold time 0.8ns 08
34 Data signal input setup time 1.5ns
35 Data signal input hold time 0.8ns
36-61 Superset Information (may be used in future) option 00
62 SPD Revision
63 Checksum for bytes 0-62 C3
64-71 Manufactures Jedec ID code per JEP-108E MITSUBISHI 1CFFFFFFFFFFFFFF
72 Manufacturing location
73-90 Manufactures Part Number
91-92 Revision Code PCB revision rrrr
93-94 Manufacturing date year/week code yyww
95-98 Assembly Serial Number serial number ssssssss
99-125 Manufacture Specific Data option 00
126 Intetl specification frequency 64
127 Intel specification CAS# Latency support
128+ Unused storage locations open 00
JEDEC2 02
Miyoshi,Japan 01
Tajima,Japan 02
NC,USA 03
Germany 04
MH8S72BCFD-6
15
08
8DCL=3,AP,CK0
MIT-DS-0312-0.0
MITSUBISHI
ELECTRIC
9/May. /1999
54
Page 55
MITSUBISHI LSIs
MH8S72BCFD-6
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
133.35
3
8.89
11.43
3
24.495
6.35
36.83
42.18
6.35
1.27
54.61
127.35
38.10
4.0Max
MIT-DS-0312-0.0
MITSUBISHI
ELECTRIC
1.27
9/May. /1999
55
Page 56
MITSUBISHI LSIs
MH8S72BCFD-6
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Keep safety first in your circuit designs!
Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products
better and more reliable,but there is always the possibility that trouble may occur with them.
Trouble with semiconductors consideration to safety when making your circuit designs,with
appropriate measures such as (i) placement of substitutive,auxiliary circuits,(ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
1.These materials are intended as a reference to assist our customers in the selection of the Mitsubishi
semiconductor product best suited to the customer's application;they do not convey any license under any
intellectual property rights,or any other rights,belonging to Mitsubishi Electric Corporation or a third party.
2.Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any thirdparty's rights,originating in the use of any product data,diagrams,charts or circuit application examples
contained in these materials.
3.All information contained in these materials,including product data, diagrams and charts,represent
information on products at the time of publication of these materials,and are subject to change by Mitsubishi
Electric Corporation without notice due to product improvements or other reasons. It is therefore
recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubish
Semiconductor product
distributor for the latest product information before purchasing a product listed herein.
4.Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or
system that is used under circumstances in which human life is potentially at stake. Please contact
Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering
the use of a product contained herein for special applications,such as apparatus or systems for
transportation, vehicular,medical,aerospace,nuclear,or undersea repeater use.
5.The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or
in part these materials.
6.If these products or technologies are subject the Japanese export control restrictions,they must be
exported under a license from the Japanese government and cannot be imported into a country other than
the approved destination. Any diversion or reexport contrary to the export control laws and regulations of
Japan and/or the country of destination is prohibited.
7.Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor
for further details on these materials or the products contained therein.
MIT-DS-0312-0.0
MITSUBISHI
ELECTRIC
9/May. /1999
56
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