1,207,959,552-BIT ( 16,777,216-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
DESCRIPTION
APPLICATION
easy interchange or addition of module.
FEATURES
Type name
6ns (CL = 2, 3)
MH16S72BDFA-7
Frequency
[component level]
100MHz
6ns (CL = 3)
MH16S72BDFA-8
100MHz
PRELIMINARY
Some of contents are subject to change without notice.
The MH16S72BDFA is 16777216 - word x 72-bit
Synchronous DRAM module. This consist of eighteen
industry standard 16M x 4 Synchronous DRAMs in
TSOP.
The TSOP on a card edge dual in-line package provides
any application where high densities and large of
quantities memory are required.
This is a socket-type memory module ,suitable for
CLK
Max.
Access Time
MITSUBISHI LSIs
MH16S72BDFA-7, -8
85pin
94pin
1pin
10pin
Utilizes industry standard 16M X 4 Synchronous DRAMs in
TSOP package , industry standard Resistered buffer in TSSOP
package and industry standard PLL in TSSOP package
Single 3.3V +/- 0.3V supply
LVTTL Interface
Burst length 1/2/4/8/Full Page(programmable)
Burst Write / Single Write(programmable)
Auto precharge / All bank precharge controlled by A10
Auto refresh and Self refresh
4096 refresh cycles every 64ms
Discrete IC and module design conform to
PC/100 specification.
(module Spec. Rev. 1.2 and SPD 1.2A)
Main memory unit for computers, Microcomputer memory.
95pin
124pin
125pin
168pin
11pin
40pin
41pin
84pin
MIT-DS-0329-0.0
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ELECTRIC
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MITSUBISHI LSIs
MH16S72BDFA-7, -8
1,207,959,552-BIT ( 16,777,216-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
PIN NO.PIN NAMEPIN NO.PIN NAMEPIN NO.PIN NAMEPIN NO.PIN NAME
Combination of /RAS,/CAS,/W defines basic commands.
the bank to which a command is applied.BA must be set
Register enable:When REGE is low,All control signals and
MH16S72BDFA-7, -8
1,207,959,552-BIT ( 16,777,216-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
CK0
CKE0
/S0,2
/RAS,/CAS,/W
A0-11
Input
Input
Input
Input
Input
Master Clock:All other inputs are referenced to the rising
edge of CK
Clock Enable:CKE controls internal clock.When CKE is
low,internal clock for the following cycle is ceased. CKE is
also used to select auto / self refresh. After self refresh
mode is started, CKE E becomes asynchronous input.Self
refresh is maintained as long as CKE is low.
Chip Select: When /S is high,any command means
No Operation.
A0-11 specify the Row/Column Address in conjunction with
BA.The Row Address is specified by A0-11.The Column
Address is specified by A0-9.A10 is also used to indicate
precharge option.When A10 is high at a read / write
command, an auto precharge is performed. When A10 is
BA0-1
DQ0-63
CB0-7
DQM0-7
Vdd,Vss
REGE
Input
Input/Output
Input
Power Supply
Output
high at a precharge command, both banks are precharged.
Bank Address:BA0,1 is not simply BA.BA0,1 specifies
with ACT,PRE,READ,WRITE commands
Data In and Data out are referenced to the rising edge
of CK
Din Mask/Output Disable:When DQMB is high in burst
write.Din for the current cycle is masked.When DQMB is
high in burst read,Dout is disabled at the next but one cycle.
Power Supply for the memory mounted module.
address are buffered. (Buffer mode) When REGE is
high,All control and address are latched. (Latch mode)
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ELECTRIC
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MITSUBISHI LSIs
BASIC FUNCTIONS
Each command is defined by control signals of /RAS,/CAS and /WE at CK rising edge. In
READ command starts burst read from the active bank indicated by BA.First output
MH16S72BDFA-7, -8
1,207,959,552-BIT ( 16,777,216-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
The MH16S72BDFA provides basic functions,bank(row)activate,burst read / write,
bank(row)precharge,and auto / self refresh.
addition to 3 signals,/S,CKE and A10 are used as chip select,refresh option,and
precharge option,respectively.
To know the detailed definition of commands please see the command truth table.
ACT command activates a row in an idle bank indicated by BA.
Read(READ) [/RAS =H,/CAS =L, /WE =H]
data appears after /CAS latency. When A10 =H at this command,the bank is
deactivated after the burst read(auto-precharge, READA).
Write(WRITE) [/RAS =H, /CAS = /WE =L]
WRITE command starts burst write to the active bank indicated by BA. Total data
length to be written is set by burst length. When A10 =H at this command, the bank
is deactivated after the burst write(auto-precharge, WRITEA).
Precharge(PRE) [/RAS =L, /CAS =H,/WE =L]
PRE command deactivates the active bank indicated by BA. This command also
terminates burst read / write operation. When A10 =H at this command, both banks
are deactivated(precharge all, PREA).
Auto-Refresh(REFA) [/RAS =/CAS =L, /WE =CKE =H]
PEFA command starts auto-refresh cycle. Refresh address including bank address
are generated internally. After this command, the banks are precharged automatically.
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1,207,959,552-BIT ( 16,777,216-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Precharge All Bank
COMMAND TRUTH TABLE
MITSUBISHI LSIs
MH16S72BDFA-7, -8
COMMAND
Deselect
No Operation
Row Adress Entry &
Bank Activate
Single Bank Precharge
Column Address Entry
& Write
Column Address Entry
& Write with Auto-
Precharge
Column Address Entry
& Read
Column Address Entry
& Read with Auto
Precharge
MNEMONIC
DESEL
NOP
ACT
PRE
PREA
WRITE
WRITEA
READ
READA
CK
n-1
CK
H
H
H
H
H
H
H
H
H
/S
n
X
X
X
X
X
X
X
X
X
/RAS
H
L
L
L
L
L
L
L
L
X
H
L
L
L
LH
H
H
H
/CAS
X
H
H
H
H
H
L
L
L
/WE
X
H
H
L
L
L
L
H
H
BA
X
X
V
V
V
V
V
V
V
A10
X
X
V
L
H
L
H
L
H
A0-9
X
X
V
X
X
V
V
V
V
Auto-Refresh
Self-Refresh Entry
Self-Refresh Exit
Burst Terminate
Mode Register Set
REFA
REFS
REFSX
TERM
MRS
H
H
L
L
H
H
H
L
H
H
X
X
HL
L
L
L
LX
H
L
H
H
L
L
L
L
L
X
H
H
L
H
H
X
H
L
L
X
X
X
X
X
L
H =High Level, L = Low Level, V = Valid, X = Don't Care, n = CK cycle number
NOTE:
1.A7-9 = 0, A0-6 = Mode Address
X
X
X
X
X
L
X
X
X
X
X
V*1
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ELECTRIC
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1,207,959,552-BIT ( 16,777,216-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
FUNCTION TRUTH TABLE
MITSUBISHI LSIs
MH16S72BDFA-7, -8
Current State
IDLE
ROW ACTIVE
READ
/S
/RAS
H
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
L
L
L
/CAS
X
H
H
H
L
L
L
L
X
H
H
H
H
L
L
L
L
X
H
H
H
/WE
X
H
H
L
H
H
L
L
X
H
H
L
L
H
H
L
L
X
H
H
L
X
H
L
X
H
L
H
L
X
H
L
H
L
H
L
H
L
X
H
L
H
Address
X
X
BA
BA,CA,A10
BA,RA
BA,A10
X
Op-Code,
Mode-Add
X
X
BA
BA,CA,A10
BA,CA,A10
BA,RA
BA,A10
X
Op-Code,
Mode-Add
X
X
BA
BA,CA,A10
Command
DESEL
NOP
TBST
READ/WRITE
ACT
PRE/PREA
REFA
MRS
DESEL
NOP
TBST
READ/READA
WRITE/
WRITEA
ACT
PRE/PREA
REFA
MRS
DESEL
NOP
TBST
READ/READA
Action
NOP
NOP
ILLEGAL*2
ILLEGAL*2
Bank Active,Latch RA
NOP*4
Auto-Refresh*5
Mode Register Set*5
NOP
NOP
NOP
Begin Read,Latch CA,
Determine Auto-Precharge
Begin Write,Latch CA,
Determine Auto-Precharge
Bank Active/ILLEGAL*2
Precharge/Precharge All
ILLEGAL
ILLEGAL
NOP(Continue Burst to END)
NOP(Continue Burst to END)
Terminate Burst
Terminate Burst,Latch CA,
Begin New Read,Determine
Auto-Precharge*3
MIT-DS-0329-0.0
Terminate Burst,Latch CA,
L
L
L
L
L
H
L
L
L
L
L
H
H
L
L
L
BA,CA,A10
BA,RA
H
L
BA,A10
X
H
Op-Code,
L
Mode-Add
MITSUBISHI
WRITE/WRITEA
ACT
PRE/PREA
REFA
MRS
Begin Write,Determine AutoÂPrecharge*3
Bank Active/ILLEGAL*2
Terminate Burst,Precharge
ILLEGAL
ILLEGAL
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MITSUBISHI LSIs
FUNCTION TRUTH TABLE
MH16S72BDFA-7, -8
1,207,959,552-BIT ( 16,777,216-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
(continued)
Current State
WRITE
READ with
AUTO
PRECHARGE
WRITE with
AUTO
PRECHARGE
/S
/RAS
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
/CAS
X
H
H
H
H
L
L
L
L
X
H
H
H
H
L
L
L
L
X
H
H
H
H
L
L
L
L
/WE
X
H
H
L
L
H
H
L
L
X
H
H
L
L
H
H
L
L
X
H
H
L
L
H
H
L
L
X
H
L
H
L
H
L
H
L
X
H
L
H
L
H
L
H
L
X
H
L
H
L
H
L
H
L
Address
X
X
BA
BA,CA,A10
BA,CA,A10
BA,RA
BA,A10
X
Op-Code,
Mode-Add
X
X
BA
BA,CA,A10
BA,CA,A10
BA,RA
BA,A10
X
Op-Code,
Mode-Add
X
X
BA
BA,CA,A10
BA,CA,A10
BA,RA
BA,A10
X
Op-Code,
Mode-Add
Command
DESEL
NOP
TBST
READ/READA
WRITE/
WRITEA
ACT
PRE/PREA
REFA
MRS
DESEL
NOP
TBST
READ/READA
WRITE/
WRITEA
ACT
PRE/PREA
REFA
MRS
DESEL
NOP
TBST
READ/READA
WRITE/
WRITEA
ACT
PRE/PREA
REFA
MRS
Action
NOP(Continue Burst to END)
NOP(Continue Burst to END)
Terminate Burst
Terminate Burst,Latch CA,
Begin Read,Determine AutoÂPrecharge*3
Terminate Burst,Latch CA,
Begin Write,Determine AutoÂPrecharge*3
Bank Active/ILLEGAL*2
Terminate Burst,Precharge
ILLEGAL
ILLEGAL
NOP(Continue Burst to END)
NOP(Continue Burst to END)
ILLEGAL
ILLEGAL
ILLEGAL
Bank Active/ILLEGAL*2
ILLEGAL*2
ILLEGAL
ILLEGAL
NOP(Continue Burst to END)
NOP(Continue Burst to END)
ILLEGAL
ILLEGAL
ILLEGAL
Bank Active/ILLEGAL*2
ILLEGAL*2
ILLEGAL
ILLEGAL
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ELECTRIC
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MH16S72BDFA-7, -8
1,207,959,552-BIT ( 16,777,216-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
FUNCTION TRUTH TABLE(continued)
MITSUBISHI LSIs
Current State
PRE -
CHARGING
ROW
ACTIVATING
/S
H
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
/RAS
X
H
H
H
L
L
L
L
X
H
H
H
L
L
L
L
/CAS
X
H
H
L
H
H
L
L
X
H
H
L
H
H
L
L
/WE
X
H
L
X
H
L
H
L
X
H
L
X
H
L
H
L
Address
X
X
BA
BA,CA,A10
BA,RA
BA,A10
X
Op-Code,
Mode-Add
X
X
BA
BA,CA,A10
BA,RA
BA,A10
X
Op-Code,
Mode-Add
Command
DESEL
NOP
TBST
READ/WRITE
ACT
PRE/PREA
REFA
MRS
DESEL
NOP
TBST
READ/WRITE
ACT
PRE/PREA
REFA
MRS
Action
NOP(Idle after tRP)
NOP(Idle after tRP)
ILLEGAL*2
ILLEGAL*2
ILLEGAL*2
NOP*4(Idle after tRP)
ILLEGAL
ILLEGAL
NOP(Row Active after tRCD
NOP(Row Active after tRCD
ILLEGAL*2
ILLEGAL*2
ILLEGAL*2
ILLEGAL*2
ILLEGAL
ILLEGAL
WRITE RE-
COVERING
MIT-DS-0329-0.0
H
L
L
L
L
L
L
L
X
H
H
H
L
L
L
L
X
H
H
L
H
H
L
L
X
X
H
X
BA
L
X
BA,CA,A10
BA,RA
H
L
BA,A10
X
H
Op-Code,
L
Mode-Add
MITSUBISHI
DESEL
NOP
TBST
READ/WRITE
ACT
PRE/PREA
REFA
MRS
NOP
NOP
ILLEGAL*2
ILLEGAL*2
ILLEGAL*2
ILLEGAL*2
ILLEGAL
ILLEGAL
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MH16S72BDFA-7, -8
1. All entries assume that CKE was High during the preceding clock cycle and the current
1,207,959,552-BIT ( 16,777,216-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
FUNCTION TRUTH TABLE(continued)
MITSUBISHI LSIs
Current State
RE-
FRESHING
MODE
REGISTER
SETTING
/S
H
L
L
L
L
L
L
L
H
L
L
L
L
L
/RAS
X
H
H
H
L
L
L
L
X
H
H
H
L
L
/CAS
X
H
H
L
H
H
L
L
X
H
H
L
H
H
/WE
X
H
L
X
H
L
H
L
X
H
L
X
H
L
Address
X
X
BA
BA,CA,A10
BA,RA
BA,A10
X
Op-Code,
Mode-Add
X
X
BA
BA,CA,A10
BA,RA
BA,A10
Command
DESEL
NOPNOP(Idle after tRC)
TBST
READ/WRITE
ACT
PRE/PREA
REFA
MRS
DESEL
NOP
TBST
READ/WRITE
ACT
PRE/PREA
NOP(Idle after tRC)
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
NOP(Idle after tRSC)
NOP(Idle after tRSC)
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
Action
L
L
L
L
L
L
H
L
X
Op-Code,
Mode-Add
REFA
MRS
ILLEGAL
ILLEGAL
ABBREVIATIONS:
H = Hige Level, L = Low Level, X = Don't Care
BA = Bank Address, RA = Row Address, CA = Column Address, NOP = No Operation
NOTES:
clock cycle.
2. ILLEGAL to bank in specified state; function may be legal in the bank indicated by BA,
depending on the state of that bank.
3. Must satisfy bus contention, bus turn around, write recovery requirements.
4. NOP to bank precharging or in idle state.May precharge bank indicated by BA.
5. ILLEGAL if any bank is not idle.
ILLEGAL = Device operation and / or date-integrity are not guaranteed.
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MH16S72BDFA-7, -8
2. Power-Down and Self-Refresh can be entered only form the All banks idle State.
1,207,959,552-BIT ( 16,777,216-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
FUNCTION TRUTH TABLE FOR CKE
MITSUBISHI LSIs
Current State
SELF -
REFRESH*1
POWER
DOWN
ALL BANKS
IDLE*2
CK
n-1
CK
n
H
L
L
L
L
L
L
H
L
L
H
H
H
H
H
H
H
X
H
H
H
H
H
L
X
H
L
H
L
L
L
L
L
L
/S
X
H
L
L
L
L
X
X
X
X
X
L
H
L
L
L
L
/RAS
X
X
H
H
H
L
X
X
X
X
X
L
X
H
H
H
L
/CAS
X
X
H
H
L
X
X
X
X
X
X
L
X
H
H
L
X
/WE
X
X
H
L
X
X
X
X
X
X
X
H
X
H
L
X
X
Add
X
INVALID
Exit Self-Refresh(Idle after tRC)
X
Exit Self-Refresh(Idle after tRC)
X
ILLEGAL
X
ILLEGAL
X
ILLEGAL
X
NOP(Maintain Self-Refresh)
X
X
INVALID
Exit Power Down to Idle
X
NOP(Maintain Self-Refresh)
X
X
Refer to Function Truth Table
Enter Self-Refresh
X
Enter Power Down
X
Enter Power Down
X
ILLEGAL
X
ILLEGAL
X
ILLEGAL
X
Action
ANY STATE
other than
listed above
L
H
H
L
L
X
X
H
H
X
L
X
X
X
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Refer to Current State = Power Down
X
X
Refer to Function Truth Table
Begin CK0 Suspend at Next Cycle*3
X
X
Exit CK0 Suspend at Next Cycle*3
X
Maintain CK0 Suspend
ABBREVIATIONS:
H = High Level, L = Low Level, X = Don't Care
NOTES:
1. CKE Low to High transition will re-enable CK and other inputs asynchronously.
A minimum setup time must be satisfied before any command other than EXIT.
3. Must be legal command.
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ELECTRIC
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MITSUBISHI LSIs
POWER ON SEQUENCE
After these sequence, the SDRAM is idle state and ready for normal operation.
MODE REGISTER
LENGTH
BURST
LATENCY
MH16S72BDFA-7, -8
1,207,959,552-BIT ( 16,777,216-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Before starting normal operation, the following power on sequence is necessary to prevent
a SDRAM from damaged or malfunctioning.
1. Apply power and start clock. Attempt to maintain CKE high, DQMB high and NOP
condition at the inputs.
2. Maintain stable power, stable cock, and NOP input conditions for a minimum of 500µs.
3. Issue precharge commands for all banks. (PRE or PREA)
4. After all banks become idle state (after tRP), issue 8 or more auto-refresh commands.
5. Issue a mode register set command to initialize the mode register.
Burst Length, Burst Type and /CAS Latency can be programmed by setting the mode
register(MRS). The mode register stores these date until the next MRS command, which
may be issue when both banks are in idle state. After tRSC from a MRS command, the
SDRAM is ready for new command.
CK
/S
MODE
BA0
0
BA1
0
CL
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
A10
A11
0
0
/CAS LATENCY
A9
WM
A8
0
R
R
2
3
R
R
R
R
A7
0
A6
A5
LTMODE
A4
A3
BT
BURST
TYPE
A2
A1
BL
A0
BA0,1 A11-0
BL
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
0
1
/RAS
/CAS
/WE
BT= 0
1
2
4
8
R
R
R
FP
SEQUENTIAL
INTERLEAVED
V
BT= 1
1
2
4
8
R
R
R
R
WRITE
MODE
MIT-DS-0329-0.0
0
1
BURST
SINGLE BIT
MITSUBISHI
R:Reserved for Future Use
FP: Full Page
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MITSUBISHI LSIs
MH16S72BDFA-7, -8
1,207,959,552-BIT ( 16,777,216-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
CK
Command
Address
DQ
CL= 3
BL= 4
Initial Address BL
A2
0
0
0
0
1
A1
0
0
1
1
0
A0
0
1
0
1
8
0
Read
Y
/CAS Latency
1
0
2
1
3
2
4
3
5
4
Sequential
3
2
4
3
5
4
6
5
7
6
Q0Q1Q2Q3
Burst Length
Column Addressing
5
4
6
5
7
6
0
7
1
0
7
6
0
7
1
0
2
1
3
2
Burst Type
1
0
0
1
3
2
2
3
5
4
Write
Y
D0D1
Burst Length
Interleaved
3
2
2
3
1
0
0
1
7
6
D3
D2
5
4
4
5
7
6
6
7
1
0
7
6
6
7
5
4
4
5
3
2
0
1
1
1
-
-
-
-
-
-
MIT-DS-0329-0.0
1
0
1
1
1
0
0
0
1
0
1
1
1
0
-
-
1
6
5
7
6
0
7
1
0
2
1
4
3
2
0
3
1
0
2
1
0
0
7
1
0
2
1
3
2
0
3
1
0
1
2
2
1
3
2
3
4
MITSUBISHI
4
3
5
4
5
6
4
5
7
6
6
7
1
0
0
1
3
2
2
3
1
0
1
0
6
7
5
4
4
5
3
2
2
3
1
0
1
0
0
1
3
2
3
2
19/Jun/1999
2
3
1
0
1
0
13
ELECTRIC
Page 14
MITSUBISHI LSIs
ABSOLUTE MAXIMUM RATINGS
mA
RECOMMENDED OPERATING CONDITION
CAPACITANCE
f=1MHz
MH16S72BDFA-7, -8
1,207,959,552-BIT ( 16,777,216-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
CK High pulse width
CK Low pilse width
Transition time of CK
Input Setup time(all inputs)
Input Hold time(all inputs)
Row cycle time
Row Active time
Row Precharge time
Write Recovery time
Act to Act Deley time
Col to Col Delay time
Mode Register Set Cycle time
Self Refresh Exit time
Refresh Interval time
Min.
-7
Max.
10
10
3
3ns
110ns
2ns
0ns
70ns
20
50100000
20
10
20
10
20
10ns
64
Min.
13
10
4
4
1
2
0
70
20
50
20
10
20
10
20
10
-8
Max.
10
100000
64
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
Note:1 The timing requirements are assumed tT=1ns. If tT is longer than 1ns, (tT-1)ns
should be added to the parameter.
CK
Signal
MIT-DS-0329-0.0
MITSUBISHI
ELECTRIC
1.4V
1.4V
Any AC timing is
referenced to the input
signal crossing
through 1.4V.
19/Jun/1999
16
Page 17
BUFFER MODE
Input Setup time(all inputs)
Row to Column Delay
SWITCHING CHARACTERISTICS
tSRX
Symbol
tCLK
tCH
tCL
tT
Parameter
CK cycle time
CK High pulse width
CK Low pilse width
Transition time of CK
tIS
tIH
tRC
Input Hold time(all inputs)
Row cycle time
tRCD
tRAS
tRP
tWR
tRRD
tCCD
tRSC
Row Active time
Row Precharge time
Write Recovery time
Act to Act Deley time
Col to Col Delay time
Mode Register Set Cycle time
Self Refresh Exit time
tREF
Refresh Interval time
MITSUBISHI LSIs
MH16S72BDFA-7, -8
1,207,959,552-BIT ( 16,777,216-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Limits
CL=2
CL=3
-7
Min.
10
10
3
3ns
1
7ns
0ns
70
20
50100000
20
10
20
10
20
10ns
Max.
10
64
Min.
-8
Unit
Max.
13
10ns
4
4
1
7
0
70
20
50
20
10
20
10
20
10
10
100000
64
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
Note:1 The timing requirements are assumed tT=1ns. If tT is longer than 1ns, (tT-1)ns
should be added to the parameter.
1,207,959,552-BIT ( 16,777,216-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Burst WRITE (multi bank) with AUTO-PRECHARGEBL=4,Buffer mode(REGE="L")
CLK
/CS
/RAS
/CAS
CKE
DQM
0
1
tRRD
2
tRCD
4
3
6
5
tRC
BL-1+ tWR + tRP
7
8
10
9
BL-1+ tWR + tRP
11
tRCD
12
tRRD
13
14
15
16
tRCD
17
A0-9
A10
A11
BA0,1
REGE
DQ
X
X
X
0
ACT#0
X
X
X
1
ACT#1
Y
01
D0D0D0D0
WRITE#0 with
AutoPrecharge
YX
D1D1D1D1
ACT#0
WRITE#1 with
AutoPrecharge
Y
X
X
X
0
WRITE#0
X
X
0
1
D0D0D0D0
ACT#1
WRITE#1
Y
1
D1
MIT-DS-0329-0.0
Italic parameter indicates minimum case
MITSUBISHI
ELECTRIC
19/Jun/1999
27
Page 28
MITSUBISHI LSIs
/WE
MH16S72BDFA-7, -8
1,207,959,552-BIT ( 16,777,216-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Burst WRITE (multi bank) with AUTO-PRECHARGEBL=4,Latch mode(REGE="H")
CLK
/CS
/RAS
/CAS
CKE
DQM
0
1
tRRD
2
tRCD
4
3
6
5
tRC
BL-1+ tWR + tRP
7
8
10
9
BL-1+ tWR + tRP
11
tRCD
12
tRRD
13
14
15
16
tRCD
17
A0-9
A10
A11
BA0,1
REGE
DQ
X
X
X
0
ACT#0
X
X
X
1
ACT#1
Y
01
D0D0D0D0
WRITE#0 with
AutoPrecharge
YX
D1D1D1D1
ACT#0
WRITE#1 with
AutoPrecharge
Y
X
X
X
0
WRITE#0
X
X
0
1
D0D0D0D0
ACT#1
WRITE#1
Y
1
MIT-DS-0329-0.0
Italic parameter indicates minimum case
MITSUBISHI
ELECTRIC
19/Jun/1999
28
Page 29
MITSUBISHI LSIs
/WE
MH16S72BDFA-7, -8
1,207,959,552-BIT ( 16,777,216-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Burst READ (multi bank) with AUTO-PRECHARGEBL=4,Buffer mode(REGE="L")
CLK
/CS
/RAS
/CAS
CKE
DQM
0
1
tRRD
tRCD
2
4
3
6
5
tRC
BL+tRP
DQM read latency =2
8
7
10
9
BL+tRP
11
12
tRRD
tRCD
13
14
15
16
tRCD
17
A0-9
A10
A11
BA0,1
REGE
DQ
X
X
X
0
ACT#0
ACT#1
Y
X
X
X
0
1
CL=3
READ#0 with
Auto-Precharge
Y
1
CL=3
Q0Q0Q0Q0
READ#1 with
Auto-Precharge
X
X
X
0
Q1Q1Q1Q1
ACT#0
READ#0
Y
0
X
X
X
1
CL=3
ACT#1
Q0
Y
1
Q0
MIT-DS-0329-0.0
Italic parameter indicates minimum case
MITSUBISHI
ELECTRIC
19/Jun/1999
29
Page 30
MITSUBISHI LSIs
/WE
MH16S72BDFA-7, -8
1,207,959,552-BIT ( 16,777,216-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Burst READ (multi bank) with AUTO-PRECHARGEBL=4,Latch mode(REGE="H")
CLK
/CS
/RAS
/CAS
CKE
DQM
0
1
tRRD
tRCD
2
4
3
6
5
tRC
BL+tRP
DQM read latency =3
8
7
10
9
BL+tRP
11
12
tRRD
tRCD
13
14
15
16
tRCD
17
A0-9
A10
A11
BA0,1
REGE
DQ
X
X
X
0
ACT#0
ACT#1
Y
X
X
X
0
1
CL=3
READ#0 with
Auto-Precharge
Y
1
CL=3
Q0Q0Q0Q0
READ#1 with
Auto-Precharge
X
X
X
0
Q1Q1Q1Q1
ACT#0
READ#0
Y
0
X
X
X
1
CL=3
ACT#1
Q0
Y
1
Q0
MIT-DS-0329-0.0
Italic parameter indicates minimum case
MITSUBISHI
ELECTRIC
19/Jun/1999
30
Page 31
MITSUBISHI LSIs
/WE
MH16S72BDFA-7, -8
1,207,959,552-BIT ( 16,777,216-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
CLK
/CS
/RAS
/CAS
CKE
Page Mode Burst Write (multi bank)
1
0
tRRD
tRCD
3
2
5
4
7
6
BL=4,Buffer mode(REGE="L")
9
8
10
11
12
13
14
15
16
17
DQM
A0-9
A10
A11
BA0,1
REGE
DQ
X
X
X
0
ACT#0
Y
X
X
X
00
1
D0D0D0D0
WRITE#0
ACT#1
YY
D0D0D0D0D0D0D0
WRITE#0
Y
1
D1D1D1D1
WRITE#1
0
WRITE#0
MIT-DS-0329-0.0
MITSUBISHI
ELECTRIC
Italic parameter indicates minimum case
19/Jun/1999
31
Page 32
MITSUBISHI LSIs
/WE
MH16S72BDFA-7, -8
1,207,959,552-BIT ( 16,777,216-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
CLK
/CS
/RAS
/CAS
CKE
Page Mode Burst Write (multi bank)
1
0
tRRD
tRCD
3
2
5
4
7
6
BL=4,Latch mode(REGE="H")
9
8
10
11
12
13
14
15
16
17
DQM
A0-9
A10
A11
BA0,1
REGE
DQ
X
X
X
0
ACT#0
Y
X
X
X
00
1
D0D0D0D0
WRITE#0
ACT#1
YY
D0D0D0D0D0D0
WRITE#0
Y
1
D1D1D1D1
WRITE#0
WRITE#1
0
MIT-DS-0329-0.0
MITSUBISHI
ELECTRIC
Italic parameter indicates minimum case
19/Jun/1999
32
Page 33
MITSUBISHI LSIs
/WE
MH16S72BDFA-7, -8
1,207,959,552-BIT ( 16,777,216-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
CLK
/CS
/RAS
/CAS
CKE
DQM
Page Mode Burst Read (multi bank)
1
0
tRRD
tRCD
3
2
5
4
7
6
BL=4,Buffer mode(REGE="L")
9
8
10
11
12
13
14
15
16
17
A0-9
A10
A11
BA0,1
REGE
DQ
X
X
X
0
ACT#0
DQM read latency=2
Y
X
X
X
00
1
CL=3
READ#0
ACT#1
YY
CL=3
Q0Q0Q0
Q0
READ#0
Y
1
CL=3
Q0Q0Q0Q0
READ#1
0
Q1Q1Q1Q1
READ#0
MIT-DS-0329-0.0
MITSUBISHI
ELECTRIC
Italic parameter indicates minimum case
19/Jun/1999
33
Page 34
MITSUBISHI LSIs
/WE
MH16S72BDFA-7, -8
1,207,959,552-BIT ( 16,777,216-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
CLK
/CS
/RAS
/CAS
CKE
DQM
Page Mode Burst Read (multi bank)
1
0
tRRD
tRCD
3
2
5
4
7
6
BL=4,Latch mode(REGE="H")
9
8
10
11
12
13
14
15
16
17
A0-9
A10
A11
BA0,1
REGE
DQ
X
X
X
0
ACT#0
DQM read latency=3
Y
X
X
X
00
1
CL=3
READ#0
ACT#1
YY
CL=3
Q0Q0Q0
Q0
READ#0
Y
1
CL=3
Q0Q0Q0Q0
READ#1
0
Q1Q1Q1Q1
READ#0
MIT-DS-0329-0.0
MITSUBISHI
ELECTRIC
Italic parameter indicates minimum case
19/Jun/1999
34
Page 35
MITSUBISHI LSIs
/WE
MH16S72BDFA-7, -8
1,207,959,552-BIT ( 16,777,216-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
CLK
/CS
/RAS
/CAS
CKE
DQM
Write Interrupted by Write / Read
0
1
tRRD
2
tRCD
4
3
5
6
tCCD
7
BL=4,Buffer mode(REGE="L")
8
10
9
11
12
13
14
15
16
17
A0-9
A10
A11
BA0,1
REGE
DQ
X
X
X
0
ACT#0
Y
X
X
X
0
1
D0D0D0D0
WRITE#0
ACT#1
Burst Write can be interrupted by Write or Read of any active bank.
WRITE#0
YY
000
D0D0D1D1Q0Q0Q0
WRITE#0
Y
1
WRITE#1
Y
CL=3
Q0
READ#0
MIT-DS-0329-0.0
MITSUBISHI
ELECTRIC
Italic parameter indicates minimum case
19/Jun/1999
35
Page 36
MITSUBISHI LSIs
/WE
MH16S72BDFA-7, -8
1,207,959,552-BIT ( 16,777,216-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
CLK
/CS
/RAS
/CAS
CKE
DQM
Write Interrupted by Write / Read
0
1
tRRD
2
tRCD
4
3
5
6
tCCD
7
BL=4,Latch mode(REGE="H")
8
10
9
11
12
13
14
15
16
17
A0-9
A10
A11
BA0,1
REGE
DQ
X
X
X
0
ACT#0
Y
X
X
X
0
1
D0D0D0D0
WRITE#0
ACT#1
Burst Write can be interrupted by Write or Read of any active bank.
WRITE#0
YY
000
WRITE#0
Y
1
D0D0D1D1Q0Q0Q0
WRITE#1
Y
CL=3
Q0
READ#0
MIT-DS-0329-0.0
MITSUBISHI
ELECTRIC
Italic parameter indicates minimum case
19/Jun/1999
36
Page 37
MITSUBISHI LSIs
/WE
MH16S72BDFA-7, -8
1,207,959,552-BIT ( 16,777,216-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
CLK
/CS
/RAS
/CAS
CKE
DQM
Read Interrupted by Read / Write
1
0
tRRD
tRCD
3
2
5
4
6
BL=4,Buffer mode(REGE="L")
7
9
8
10
11
12
13
14
15
16
17
A0-9
A10
A11
BA0,1
DQ
REGE
X
X
X
0
ACT#0
X
X
X
1
ACT#1
DQM read latency=2
Y
00
READ#0
READ#0
YY
Y
0
Q0Q0Q0
Q0
READ#0
Y
1
READ#1
Y
0
Q0Q0Q1Q1
READ#0
blank to prevent bus contention
Q0D0D0
0
WRITE#0
MIT-DS-0329-0.0
Burst Read can be interrupted by Read or Write of any active bank.
Italic parameter indicates minimum case
MITSUBISHI
ELECTRIC
19/Jun/1999
37
Page 38
MITSUBISHI LSIs
/WE
MH16S72BDFA-7, -8
1,207,959,552-BIT ( 16,777,216-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
CLK
/CS
/RAS
/CAS
CKE
DQM
Read Interrupted by Read / Write
1
0
tRRD
tRCD
3
2
5
4
6
BL=4,Latch mode(REGE="H")
7
9
8
10
11
12
13
14
15
16
17
A0-9
A10
A11
BA0,1
DQ
REGE
X
X
X
0
ACT#0
X
X
X
1
ACT#1
DQM read latency=3
Y
00
READ#0
READ#0
YY
Y
0
Q0Q0Q0
Q0
READ#0
Y
1
READ#1
Y
0
Q0Q0Q1Q1
READ#0
blank to prevent bus contention
Q0D0
0
WRITE#0
MIT-DS-0329-0.0
Burst Read can be interrupted by Read or Write of any active bank.
Italic parameter indicates minimum case
MITSUBISHI
ELECTRIC
19/Jun/1999
38
Page 39
MITSUBISHI LSIs
/WE
MH16S72BDFA-7, -8
1,207,959,552-BIT ( 16,777,216-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
CLK
/CS
/RAS
/CAS
CKE
DQM
Write Interrupted by Precharge
0
1
tRRD
2
tRCD
4
3
6
5
BL=4,Buffer mode(REGE="L")
8
7
10
9
11
12
13
14
15
16
17
A0-9
A10
A11
BA0,1
DQ
REGE
X
X
X
0
ACT#0
Y
X
X
X
0
1
D0D0D0D0
WRITE#0
ACT#1
Burst Write is not interrupted
by Precharge of the other bank.
WRITE#1
Y
0
1
PRE#1
Burst Write is interrupted by
Precharge of the same bank.
11
D1D1D1D1D1
PRE#0
X
X
X
1
ACT#1
Y
WRITE#1
MIT-DS-0329-0.0
MITSUBISHI
ELECTRIC
Italic parameter indicates minimum case
19/Jun/1999
39
Page 40
MITSUBISHI LSIs
/WE
MH16S72BDFA-7, -8
1,207,959,552-BIT ( 16,777,216-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
CLK
/CS
/RAS
/CAS
CKE
DQM
Write Interrupted by Precharge
0
1
tRRD
2
tRCD
4
3
6
5
BL=4,Latch mode(REGE="H")
8
7
10
9
11
12
13
14
15
16
17
A0-9
A10
A11
BA0,1
DQ
REGE
X
X
X
0
ACT#0
Y
X
X
X
0
1
D0D0D0D0
WRITE#0
ACT#1
Burst Write is not interrupted
by Precharge of the other bank.
WRITE#1
Y
11
PRE#0
1
0
D1D1D1D1D1
PRE#1
Burst Write is interrupted by
Precharge of the same bank.
X
X
X
1
ACT#1
Y
WRITE#1
MIT-DS-0329-0.0
MITSUBISHI
ELECTRIC
Italic parameter indicates minimum case
19/Jun/1999
40
Page 41
MITSUBISHI LSIs
/WE
MH16S72BDFA-7, -8
1,207,959,552-BIT ( 16,777,216-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
CLK
/CS
/RAS
/CAS
CKE
DQM
Read Interrupted by Precharge
0
1
tRRD
tRCD
2
4
3
6
5
BL=4,Buffer mode(REGE="L")
8
7
10
9
11
tRP
12
13
14
tRCD
15
16
17
A0-9
A10
A11
BA0,1
DQ
REGE
X
X
X
0
ACT#0
DQM read latency=2
Y
X
X
X
0
1
READ#0
ACT#1
Burst Read is not interrupted
by Precharge of the other bank.
Y
1
Q0Q0Q0
Q0
READ#1
0
PRE#0
X
X
X
1
Q1Q1
PRE#1
Burst Read is interrupted
by Precharge of the same bank.
1
ACT#1
Y
1
READ#1
MIT-DS-0329-0.0
MITSUBISHI
ELECTRIC
Italic parameter indicates minimum case
19/Jun/1999
41
Page 42
MITSUBISHI LSIs
/WE
MH16S72BDFA-7, -8
1,207,959,552-BIT ( 16,777,216-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
CLK
/CS
/RAS
/CAS
CKE
DQM
Read Interrupted by Precharge
0
1
tRRD
tRCD
2
4
3
6
5
BL=4,Latch mode(REGE="H")
8
7
10
9
11
tRP
12
13
14
tRCD
15
16
17
A0-9
A10
A11
BA0,1
DQ
REGE
X
X
X
0
ACT#0
DQM read latency=3
Y
X
X
X
0
1
READ#0
ACT#1
Burst Read is not interrupted
by Precharge of the other bank.
Y
1
Q0Q0Q0
Q0
READ#1
0
PRE#0
X
X
X
1
Q1Q1
PRE#1
Burst Read is interrupted
by Precharge of the same bank.
1
ACT#1
Y
1
READ#1
MIT-DS-0329-0.0
MITSUBISHI
ELECTRIC
Italic parameter indicates minimum case
19/Jun/1999
42
Page 43
MITSUBISHI LSIs
Mode Register Setting
/WE
MH16S72BDFA-7, -8
1,207,959,552-BIT ( 16,777,216-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
CLK
/CS
/RAS
/CAS
CKE
DQM
1
0
3
2
5
4
tRC
7
6
9
8
10
tRSC
11
12
13
tRCD
14
15
16
17
A0-9
A10
A11
BA0,1
DQ
REGE
Auto-Ref (last of 8 cycles)
M
0
Mode
Register
Setting
X
X
X
0
ACT#0
Italic parameter indicates minimum case
Y
0
D0
D0D0D0
WRITE#0
MIT-DS-0329-0.0
MITSUBISHI
ELECTRIC
19/Jun/1999
43
Page 44
MITSUBISHI LSIs
Auto-Refresh @BL=4
/WE
After tRC from Auto-Refresh,
MH16S72BDFA-7, -8
1,207,959,552-BIT ( 16,777,216-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
CLK
/CS
/RAS
/CAS
CKE
DQM
1
0
3
2
5
4
tRC
7
6
9
8
10
11
tRCD
12
13
14
15
16
17
A0-9
A10
A11
BA0,1
DQ
REGE
Auto-Refresh
Before Auto-Refresh,
all banks must be idle state.
X
X
X
0
ACT#0
all banks are idle state.
Y
0
D0
D0D0D0
WRITE#0
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ELECTRIC
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MITSUBISHI LSIs
Self-Refresh
/WE
MH16S72BDFA-7, -8
1,207,959,552-BIT ( 16,777,216-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
CLK
/CS
/RAS
/CAS
CKE
DQM
1
0
CKE must be low to maintain Self-Refresh
3
2
CLK can be stopped
5
4
7
6
tSRX
9
8
10
11
12
tRC
13
14
15
16
17
A0-9
A10
A11
BA0,1
DQ
REGE
Self-Refresh Entry
Before Self-Refresh Entry,
all banks must be idle state.
Self-Refresh Exit
After tRC from Self-Refresh Exit,
all banks are idle state.
X
X
X
0
ACT#0
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ELECTRIC
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MITSUBISHI LSIs
DQM Write Mask @BL=4
/WE
MH16S72BDFA-7, -8
1,207,959,552-BIT ( 16,777,216-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
BL=4,Buffer mode(REGE="L")
CLK
/CS
/RAS
/CAS
CKE
DQM
0
1
2
tRCD
4
3
6
5
8
7
10
9
11
12
13
14
15
16
17
A0-9
A10
A11
BA0,1
DQ
REGE
X
X
X
0
ACT#0
Y
00
D0D0D0D0
WRITE#0
Y
masked
WRITE#0
Y
0
masked
D0D0D0
WRITE#0
MIT-DS-0329-0.0
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ELECTRIC
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MITSUBISHI LSIs
DQM Write Mask @BL=4
/WE
MH16S72BDFA-7, -8
1,207,959,552-BIT ( 16,777,216-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
BL=4,Latch mode(REGE="H")
CLK
/CS
/RAS
/CAS
CKE
DQM
0
1
2
tRCD
4
3
6
5
8
7
10
9
11
12
13
14
15
16
17
A0-9
A10
A11
BA0,1
DQ
REGE
X
X
X
0
ACT#0
Y
00
D0D0D0D0
WRITE#0
Y
WRITE#0
masked
Y
0
masked
D0D0D0
WRITE#0
MIT-DS-0329-0.0
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ELECTRIC
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MITSUBISHI LSIs
DQM Read Mask @BL=4 CL=3
/WE
MH16S72BDFA-7, -8
1,207,959,552-BIT ( 16,777,216-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
BL=4,Buffer mode(REGE="L")
CLK
/CS
/RAS
/CAS
CKE
DQM
0
1
2
tRCD
4
3
6
5
8
7
DQM read latency=2
10
9
11
12
13
14
15
16
17
A0-9
A10
A11
BA0,1
DQ
REGE
X
X
X
0
ACT#0
Y
00
Q0Q0Q0Q0
READ#0
Y
READ#0
Y
0
masked
READ#0
masked
Q0Q0Q0
MIT-DS-0329-0.0
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ELECTRIC
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MITSUBISHI LSIs
DQM Read Mask @BL=4 CL=3
/WE
MH16S72BDFA-7, -8
1,207,959,552-BIT ( 16,777,216-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
BL=4,Latch mode(REGE="H")
CLK
/CS
/RAS
/CAS
CKE
DQM
0
1
2
tRCD
4
3
6
5
8
7
DQM read latency=3
10
9
11
12
13
14
15
16
17
A0-9
A10
A11
BA0,1
DQ
REGE
X
X
X
0
ACT#0
Y
00
Q0Q0Q0Q0
READ#0
Y
READ#0
Y
0
masked
READ#0
masked
Q0Q0Q0
MIT-DS-0329-0.0
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ELECTRIC
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MITSUBISHI LSIs
Power Down
/WE
MH16S72BDFA-7, -8
1,207,959,552-BIT ( 16,777,216-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
CLK
/CS
/RAS
/CAS
CKE
DQM
0
2
1
4
3
Standby Power Down
6
5
8
7
CKE latency=1
9
10
11
12
14
13
Active Power Down
15
16
17
A0-9
A10
A11
BA0,1
DQ
REGE
Precharge All
X
X
X
0
ACT#0
MIT-DS-0329-0.0
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ELECTRIC
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MITSUBISHI LSIs
CLK Suspend @BL=4 CL=3
/WE
MH16S72BDFA-7, -8
1,207,959,552-BIT ( 16,777,216-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
BL=4,Buffer mode(REGE="L")
CLK
/CS
/RAS
/CAS
CKE
DQM
1
0
tRCD
CKE latency=1
3
2
5
4
7
6
9
8
CKE latency=1
10
11
12
13
14
15
16
17
A0-9
A10
A11
BA0,1
DQ
REGE
X
X
X
0
ACT#0
Y
00
D0D0D0D0
WRITE#0
CLK suspended
Y
Q0Q0Q0Q0
READ#0
CLK suspended
Italic parameter indicates minimum case
MIT-DS-0329-0.0
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ELECTRIC
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MITSUBISHI LSIs
CLK Suspend @BL=4 CL=3
/WE
MH16S72BDFA-7, -8
1,207,959,552-BIT ( 16,777,216-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
BL=4,Latch mode(REGE="H")
CLK
/CS
/RAS
/CAS
CKE
DQM
1
0
tRCD
CKE latency=2
3
2
5
4
7
6
9
8
CKE latency=2
10
11
12
13
14
15
16
17
A0-9
A10
A11
BA0,1
DQ
REGE
X
X
X
0
ACT#0
Y
00
D0D0D0D0
WRITE#0
CLK suspended
Y
Q0Q0Q0Q0
READ#0
CLK suspended
Italic parameter indicates minimum case
MIT-DS-0329-0.0
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MITSUBISHI LSIs
Serial Presence Detect Table I
SDRAM Cycletime at Max. Supported CAS Latency (CL).
ECC
Minimum Clock Delay,Back to Back Random Column Addresses
1/2/4/8/Full page
buffered,registered
Precharge All,Auto precharge
Write1/Read Burst
SDRAM Access form Clock(2nd highest CAS latency)
SDRAM Access form Clock(3rd highest CAS latency)
-8-8-7
-7
MH16S72BDFA-7, -8
1,207,959,552-BIT ( 16,777,216-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
ByteFunction describedSPD enrty dataSPD DATA(hex)
0Defines # bytes written into serial memory at module mfgr12880
1Total # bytes of SPD memory device256 Bytes08
2Fundamental memory typeSDRAM04
3# Row Addresses on this assemblyA0-A110C
4# Column Addresses on this assembly
5# Module Banks on this assembly
6Data Width of this assembly...
7... Data Width continuation000
8Voltage interface standard of this assemblyLVTTL01
9
Cycle time for CL=3
10SDRAM Access from Clock
tAC for CL=3
11DIMM Configuration type (Non-parity,Parity,ECC)
12Refresh Rate/Typeself refresh(15.625uS)80
13SDRAM width,Primary DRAM
14Error Checking SDRAM data width
15
16Burst Lengths Supported
17# Banks on Each SDRAM device4bank04
18CAS# Latency2/306
25SDRAM Cycle time(3rd highest CAS latency)N/A00
26
A0-A90A
1BANK01
x7248
10ns
6ns60
x404
x404
101
10ns
13nsD0
6ns60
7ns70
N/A00
A0
02
8F
1F
0E
A0
27Precharge to Active Minimum20ns14
28Row Active to Row Active Min.20ns14
29RAS to CAS Delay Min20ns14
30Active to Precharge Min50ns32
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MITSUBISHI LSIs
Serial Presence Detect Table II
4D483136533732424446412D372020202020
4D483136533732424446412D382020202020
-8
-7
MH16S72BDFA-7, -8
1,207,959,552-BIT ( 16,777,216-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
31Density of each bank on module
32
33Command and Address signal input hold time
34Data signal input setup time2ns
35Data signal input hold time
36-61
62SPD Revision
63Checksum for bytes 0-62
64-71Manufactures Jedec ID code per JEP-108EMITSUBISHI1CFFFFFFFFFFFFFF
72Manufacturing locationMiyoshi,Japan01
73-90Manufactures Part Number
Command and Address signal input setup time2ns20
Superset Information (may be used in future)option00
128MByte20
1ns10
1ns10
rev 1.2A12
Check sum for -73F
Check sum for -8
Tajima,Japan02
NC,USA03
Germany04
MH16S72BDFA-7
MH16S72BDFA-8
20
7F
91-92Revision CodePCB revisionrrrr
93-94Manufacturing dateyear/week codeyyww
95-98Assembly Serial Numberserial numberssssssss
99-125Manufacture Specific Dataoption00
126Intetl specification frequency
127Intel specification CAS# Latency support
128+Unused storage locationsopen00
100MHz64
CL=2/3,AP,CK0
CL=3,AP,CK0
8F
8D
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MITSUBISHI LSIs
MH16S72BDFA-7, -8
1,207,959,552-BIT ( 16,777,216-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
133.35
3
8.89
11.43
3
24.495
6.35
36.83
42.18
6.35
1.27
54.61
127.35
43.18
3.9Max
MIT-DS-0329-0.0
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ELECTRIC
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MITSUBISHI LSIs
non-flammable material or (iii) prevention against any malfunction or mishap.
1.These materials are intended as a reference to assist our customers in the
the products contained therein.
MH16S72BDFA-7, -8
1,207,959,552-BIT ( 16,777,216-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Keep safety first in your circuit designs!
Mitsubishi Electric Corporation puts the maximum effort into making
semiconductor products better and more reliable,but there is always the
possibility that trouble may occur with them. Trouble with semiconductors
consideration to safety when making your circuit designs,with appropriate
measures such as (i) placement of substitutive,auxiliary circuits,(ii) use of
Notes regarding these materials
selection of the Mitsubishi semiconductor product best suited to the
customer's application;they do not convey any license under any
intellectual property rights,or any other rights,belonging to Mitsubishi
Electric Corporation or a third party.
2.Mitsubishi Electric Corporation assumes no responsibility for any damage,
or infringement of any third-party's rights,originating in the use of any
product data,diagrams,charts or circuit application examples contained in
these materials.
3.All information contained in these materials,including product data,
diagrams and charts,represent information on products at the time of
publication of these materials,and are subject to change by Mitsubishi
Electric Corporation without notice due to product improvements or other
reasons. It is therefore recommended that customers contact Mitsubishi
Electric Corporation or an authorized Mitsubishi Semiconductor product
distributor for the latest product information before purchasing a product
listed herein.
4.Mitsubishi Electric Corporation semiconductors are not designed or
manufactured for use in a device or system that is used under
circumstances in which human life is potentially at stake. Please contact
Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor
product distributor when considering the use of a product contained herein
for special applications,such as apparatus or systems for transportation,
vehicular,medical,aerospace,nuclear,or undersea repeater use.
5.The prior written approval of Mitsubishi Electric Corporation is necessary to
reprint or reproduce in whole or in part these materials.
6.If these products or technologies are subject the Japanese export
control restrictions,they must be exported under a license from the
Japanese government and cannot be imported into a country other than
the approved destination.
Any diversion or reexport contrary to the export control laws and
regulations of Japan and/or the country of destination is prohibited.
7.Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi
Semiconductor product distributor for further details on these materials or
MIT-DS-0329-0.0
MITSUBISHI
ELECTRIC
19/Jun/1999
56
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