Page 1
MCR08B, MCR08M
Sensitive Gate
Silicon Controlled Rectifiers
Reverse Blocking Thyristors
PNPN devices designed for line powered consumer applications
such as relay and lamp drivers, small motor controls, gate drivers for
larger thyristors, and sensing and detection circuits. Supplied in
surface mount package for use in automated manufacturing.
Features
• Sensitive Gate Trigger Current
• Blocking Voltage to 600 V
• Glass Passivated Surface for Reliability and Uniformity
• Surface Mount Package
• These Devices are Pb−Free and are RoHS Compliant
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SCRs
0.8 AMPERES RMS
200 thru 600 VOLTS
G
A
K
MARKING
DIAGRAM
MAXIMUM RATINGS (T
Rating
Peak Repetitive Off−State Voltage (Note 1)
(Sine Wave, R
TJ = 25 to 110°C)
On-State Current RMS
(All Conduction Angles; T
Peak Non-repetitive Surge Current
(1/2 Cycle Sine Wave, 60 Hz, TC = 25°C)
Circuit Fusing Considerations (t = 8.3 ms) I2t 0.4 A2s
Forward Peak Gate Power
= 80°C, t = 1.0 ms)
(T
C
Average Gate Power
(T
= 80°C, t = 8.3 ms)
C
Operating Junction Temperature Range T
Storage Temperature Range T
GK
= 1 kW
= 25°C unless otherwise noted)
J
Symbol Value Unit
V
DRM,
V
RRM
MCR08B
MCR08M
I
= 80°C)
C
T(RMS)
I
TSM
P
GM
P
G(AV)
J
stg
V
200
600
0.8 A
8.0 A
0.1 W
0.01 W
−40 to +110 °C
−40 to +150 °C
THERMAL CHARACTERISTICS
Rating Symbol Value Unit
Thermal Resistance, Junction−to−Ambient
PCB Mounted per Figure 1
Thermal Resistance, Junction−to−Ta b
Measured on Anode Tab Adjacent to Epoxy
Maximum Device Temperature for Soldering Purposes (for 10 Seconds Maximum)
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. V
and V
DRM
apply for zero or negative gate voltage; however, positive gate voltage shall
not be applied concurrent with negative potential on the anode. Blocking
voltages shall not be tested with a constant source such that the voltage
ratings of the devices are exceeded.
for all types can be applied on a continuous basis. Ratings
RRM
R
q
JA
R
q
JT
T
L
156 °C/W
25 °C/W
260 °C
SOT−223
1
(Note: Microdot may be in either location)
CASE 318E
STYLE 10
CR08x = Device Code
x = B or M
A = Assembly Location
Y = Year
W = Work Week
G =Pb−Free Package
AYW
CR08x G
G
1
PIN ASSIGNMENT
1
2
3
4
Cathode
Anode
Gate
Anode
ORDERING INFORMATION
Device Package Shipping
MCR08BT1G SOT−223
(Pb−Free)
MCR08MT1G SOT−223
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
1000/Tape &Reel
1000/Tape & Reel
†
© Semiconductor Components Industries, LLC, 2013
October, 2013 − Rev. 7
1 Publication Order Number:
MCR08BT1/D
Page 2
MCR08B, MCR08M
ELECTRICAL CHARACTERISTICS (T
= 25°C unless otherwise noted)
C
Characteristic Symbol Min Typ Max Unit
OFF CHARACTERISTICS
Peak Repetitive Forward or Reverse Blocking Current (Note 3)
(V
AK
= Rated V
DRM
or V
, RGK = 1 kW
RRM
TJ = 25°C
= 110°C
T
J
ON CHARACTERISTICS
Peak Forward On-State Voltage (Note 2) (IT = 1.0 A Peak) V
Gate Trigger Current (Continuous dc) (Note 4) (VAK = 12 Vdc, RL = 100 W)
Holding Current (Note 3) (VAK = 12 Vdc, Initiating Current = 20 mA) I
Gate Trigger Voltage (Continuous dc) (Note 4) (VAK = 12 Vdc, RL = 100 W)
Turn−On Time (VAK = 12 Vdc, ITM = 5 Adc, IGT = 5 mA) t
DYNAMIC CHARACTERISTICS
Critical Rate-of-Rise of Off State Voltage
= Rated V
(V
pk
, TC = 110°C, RGK = 1 kW, Exponential Method)
DRM
2. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%.
= 1000 W is included in measurement.
3. R
GK
is not included in measurement.
4. R
GK
Voltage Current Characteristic of SCR
Symbol Parameter
V
I
DRM
V
I
RRM
V
I
H
DRM
RRM
TM
Peak Repetitive Off State Forward Voltage
Peak Forward Blocking Current
Peak Repetitive Off State Reverse Voltage
Peak Reverse Blocking Current
Peak On State Voltage
Holding Current
I
RRM
at V
on state
RRM
I
DRM
I
V
dv/dt
+ Current
GT
, I
TM
H
GT
gt
RRM
−
−
−
−
− − 1.7 V
− − 200
− − 5.0 mA
− − 0.8 V
− 1.25 −
10 − −
Anode +
V
TM
I
H
10
200
mA
mA
mA
ms
V/ms
Reverse Blocking Region
(off state)
0.079
2.0
0.091
2.3
0.15
3.8
0.091
2.3
Reverse Avalanche Region
Anode −
0.244
6.2
0.079
2.0
inches
ǒ
0.984
0.059
1.5
0.059
1.5
0.059
1.5
mm
Ǔ
25.0
0.096
2.44
0.059
1.5
0.096
2.44
0.059
1.5
0.096
2.44
BOARD MOUNTED VERTICALLY IN CINCH 8840 EDGE CONNECTOR.
BOARD THICKNESS = 65 MIL., FOIL THICKNESS = 2.5 MIL.
MATERIAL: G10 FIBERGLASS BASE EPOXY
0.472
12.0
Figure 1. PCB for Thermal Impedance and Power Testing of SOT-223
I
at V
DRM
DRM
Forward Blocking Region
(off state)
+ Voltage
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2
Page 3
MCR08B, MCR08M
, INSTANTANEOUS ON‐STATE CURRENT (AMPS)
I
, MAXIMUM ALLOWABLE
A
T
T
AMBIENT TEMPERATURE ( C)°
1.0
0.1
0.01
110
100
10
160
150
140
130
°THERMAL RESISTANCE, ( C/W)
120
110
100
90
TYPICAL
MAXIMUM
DEVICE MOUNTED ON
FIGURE 1 AREA = L
PCB WITH TAB AREA
AS SHOWN
2
L
4
1 23
L
80
70
60
TYPICAL AT TJ = 110°C
MAX AT T
MAX AT T
0
2.0 3.0
= 110°C
J
= 25°C
J
θJA
R , JUNCTION TO AMBIENT
4.01.0
MINIMUM
50
FOOTPRINT = 0.076 cm
40
30
2.00 4.0 6.0 8.0 10
1.0 3.0 5.0 7.0 9.0
2
FOIL AREA (cm2)vT, INSTANTANEOUS ON‐STATE VOLTAGE (VOLTS)
Figure 2. On-State Characteristics Figure 3. Junction to Ambient Thermal
Resistance versus Copper Tab Area
110
, MAXIMUM ALLOWABLE
A
T
100
90
80
70
60
50
40
AMBIENT TEMPERATURE ( C)°
30
20
α = 30°
α
α = CONDUCTION
ANGLE
I
T(AV)
60°
90°
, AVERAGE ON‐STATE CURRENT (AMPS)
90
50 OR 60 Hz HALFWAVE
80
70
α = CONDUCTION
dc
180°
α
ANGLE
60
50
α = 30°
40
60°
90°
120°
30
20
I
, AVERAGE ON‐STATE CURRENT (AMPS)
T(AV)
0.30.20.10
0.4
0.5
dc
1.0 cm2 FOIL, 50 OR
60 Hz HALFWAVE
180°
120°
0.40.30.20.10
0.5
, MAXIMUM ALLOWABLE
A
T
Figure 4. Current Derating, Minimum Pad Size
Reference: Ambient Temperature
110
100
90
80
70
AMBIENT TEMPERATURE ( C)°
60
50
α = 30°
60°
α
α = CONDUCTION
ANGLE
I
T(AV)
90°
, AVERAGE ON‐STATE CURRENT (AMPS)
PAD AREA = 4.0 cm2, 50
OR 60 Hz HALFWAVE
dc
180°
Figure 6. Current Derating, 2.0 cm Square Pad
Reference: Ambient Temperature
120°
0.40.30.20.10
0.5
, MAXIMUM ALLOWABLE
(tab)
T
Figure 5. Current Derating, 1.0 cm Square Pad
Reference: Ambient Temperature
110
TAB TEMPERATURE ( C)°
85
α = 30°
60°
α
α = CONDUCTION
ANGLE
I
T(AV)
dc
90°
, AVERAGE ON‐STATE CURRENT (AMPS)
50 OR 60 Hz HALFWAVE
180°
Figure 7. Current Derating
Reference: Anode Tab
120°
0.50.40.30.20.10
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3
Page 4
MCR08B, MCR08M
1.0
0.9
0.8
0.7
0.6
0.5
0.4
,DISSIPATION (WATTS)
0.3
(AV)
0.2
MAXIMUM AVERAGE POWER
P
0.1
α = CONDUCTION
0
0.7
0.6
ANGLE
α
α = 30°
60°
90°
120°
0.30.20.10
I
, AVERAGE ON‐STATE CURRENT (AMPS)
T(AV)
Figure 8. Power Dissipation
180°
0.4
VAK = 12 V
R
= 100 W
L
1.0
0.1
0.5
NORMALIZED
, TRANSIENT THERMAL RESISTANCE
T
r
0.01
0.001 0.01 1.0 10
1000.10.0001
dc
t, TIME (SECONDS)
Figure 9. Thermal Response Device
Mounted on Figure 1 Printed Circuit Board
2.0
VAK = 12 V
R
= 3.0 kW
L
, GATE TRIGGER VOLTAGE (VOLTS)
GT
V
, GATE TRIGGER VOLTAGE (VOLTS)
GT
V
0.5
0.4
0.3
0.7
0.65
0.6
0.55
0.5
0.45
0.4
0.35
0.3
8020-40 -20 0 40 60 110
TJ, JUNCTION TEMPERATURE, (°C)
Figure 10. Typical Gate Trigger Voltage
versus Junction Temperature
VAK = 12 V
R
= 100 W
L
T
= 25°C
J
1.0 100
I
, GATE TRIGGER CURRENT (mA)
GT
1.0
(NORMALIZED)
, HOLDING CURRENT
H
I
0
1000
A)
100
10
, GATE TRIGGER CURRENT ( μ
GT
I
1000100.1
1.0
8020-40 -20 0 40 60 110
T
, JUNCTION TEMPERATURE, (°C)
J
Figure 11. Typical Normalized Holding Current
versus Junction Temperature
RGK = 1000 W, RESISTOR
CURRENT INCLUDED
VAK = 12 V
R
= 100 W
L
WITHOUT GATE RESISTOR
8020-40 -20 0 40 60 110
T
, JUNCTION TEMPERATURE (°C)
J
Figure 12. Typical Range of V
versus Measured I
GT
GT
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Figure 13. Typical Gate Trigger Current
versus Junction Temperature
4
Page 5
MCR08B, MCR08M
100
1.0
HOLDING CURRENT (mA)I ,
H
0.1
10000
1000
500
100
10
IGT = 7 mA
10 100 10,000 100,000
R
, GATE‐CATHODE RESISTANCE (OHMS)
GK
10001.0
Figure 14. Holding Current Range versus
Gate-Cathode Resistance
300 V
200 V
400 V
100 V
TJ = 25°C
TJ = 110°C
50 V
IGT = 48 mA
10000
5000
1000
500
100
50
10
5.0
STATIC dv/dt (V/ S)μ
1.0
0.5
0.1
10 100 1000 10,000 100,000
RGK, GATE‐CATHODE RESISTANCE (OHMS)
125°
110 °
Vpk = 400 V
TJ = 25°
75°
Figure 15. Exponential Static dv/dt versus Junction
Temperature and Gate-Cathode Termination Resistance
10000
1000
500
100
TJ = 110°C
400 V (PEAK)
RGK = 100
50°
50
10
STATIC dv/dt (V/ S)μ
5.0
1.0
500 V
R
, GATE‐CATHODE RESISTANCE (OHMS)
GK
Figure 16. Exponential Static dv/dt versus Peak
Voltage and Gate-Cathode Termination Resistance
10000
1000
500
100
50
10
STATIC dv/dt (V/ S)μ
5.0
1.0
IGT = 5 mA
100 1000 10,000 100,00010
50
10
STATIC dv/dt (V/ S)μ
5.0
10,00010 100 1000
1.0
0.01
Figure 17. Exponential Static dv/dt versus
Gate-Cathode Capacitance and Resistance
IGT = 70 mA
IGT = 15 mA
GATE‐CATHODE RESISTANCE (OHMS)
RGK = 1.0 k
RGK = 10 k
0.1 1.0 10 100
C
, GATE‐CATHODE CAPACITANCE (nF)
GK
IGT = 35 mA
Figure 18. Exponential Static dv/dt versus
Gate-Cathode Termination Resistance and
Product Trigger Current Sensitivity
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5
Page 6
0.08 (0003)
H
e1
E
A1
D
b1
4
123
e
MCR08B, MCR08M
PACKAGE DIMENSIONS
SOT−223 (TO−261)
CASE 318E−04
ISSUE L
E
b
q
A
SOLDERING FOOTPRINT*
3.8
0.15
L1
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
DIMAMIN NOM MAX MIN
A1 0.02 0.06 0.10 0.001
b 0.60 0.75 0.89 0.024
b1 2.90 3.06 3.20 0.115
c 0.24 0.29 0.35 0.009
D 6.30 6.50 6.70 0.249
E 3.30 3.50 3.70 0.130
e 2.20 2.30 2.40 0.087
e1
L1 1.50 1.75 2.00 0.060
H
E
C
q
STYLE 10:
PIN 1. CATHODE
MILLIMETERS
1.50 1.63 1.75 0.060
0.85 0.94 1.05 0.033
6.70 7.00 7.30 0.264
0° 10° 0° 10°
− −
2. ANODE
3. GATE
4. ANODE
INCHES
NOM MAX
0.064 0.068
0.002 0.004
0.030 0.035
0.121 0.126
0.012 0.014
0.256 0.263
0.138 0.145
0.091 0.094
0.037 0.041
0.069 0.078
0.276 0.287
2.0
0.079
2.3
0.091
2.3
0.091
6.3
0.248
2.0
0.079
1.5
0.059
SCALE 6:1
ǒ
inches
mm
Ǔ
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,
copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC
reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without
limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications
and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC
does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for
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any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture
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6
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MCR08BT1/D
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