Datasheet MCP8024 Datasheet

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Page 1

MCP8024

3-Phase Brushless DC (BLDC) Motor Gate Driver

with Power Module

Features:

• Three Half-bridge Drivers Configured to Drive External High-Side NMOS and Low-Side NMOS MOSFETs:

- Independent input control for high-side

NMOS and low-side NMOS MOSFETs

- Peak output current: 0.5A @ 12V

- Shoot-through protection

- Overcurrent and short circuit protection

• Adjustable Output Buck Regulator (750 mW)

• Fixed Output Linear Regulators:

- 5V @ 20 mA

-12V @ 20 mA

• Internal Bandgap Reference

• Three Operational Amplifiers for Motor Phase Current Monitoring and Position Detection

• Overcurrent Comparator

• Two Level Translators

• Operational Voltage Range 6 - 40V

• Undervoltage Lockout (UVLO): 6V

• Overvoltage Lockout (OVLO): 28V

• Transient (100 ms) Voltage Tolerance: 48V

• Extended Temperature Range: TA -40 to +150°C

• Thermal Shutdown

Description:

The MCP8024 is a 3-Phase Brushless DC (BLDC) power module. The MCP8024 device integrates three half-bridge drivers to drive external NMOS/NMOS transistor pairs configured to drive a 3-phase BLDC motor, a comparator, a voltage regulator to provide bias to a companion microcontroller, power monitoring comparators, an overtemperature sensor, two level translators and three operational amplifiers for motor current monitoring.

The MCP8024 has three half-bridge drivers capable of delivering a peak output current of 0.5A at 12V for driving high-side and low-side NMOS MOSFET transistors. The drivers have shoot-through, overcurrent, and short-circuit protection.

The MCP8024 buck converter is capable of delivering 750 mW of power for powering a companion microcontroller. The buck regulator may be disabled if not used. The on-board 5V and 12V low dropout voltage regulators are capable of delivering 20 mA of current.

The MCP8024 operation is specified over a temperature range of -40°C to +150°C.

Package options include the 40-lead 5x5 QFN and 48lead 7x7 TQFP.

Applications:

• Automotive Fuel, Water, Ventilation Motors

• Home Appliances

• Permanent Magnet Synchronous Motor (PMSM) Control

• Hobby Aircraft, Boats, Vehicles

Related Literature:

• AN885, “Brushless DC (BLDC) Motor Fundamentals”, DS00885, Microchip Technology Inc., 2003

• AN1160, “Sensorless BLDC Control with BackEMF Filtering Using a Majority Function”, DS01160, Microchip Technology Inc., 2008

• AN1078, “Sensorless Field Oriented Control of a PMSM”, DS01078, Microchip Technology Inc., 2010

 2013 Microchip Technology Inc. DS20005228A-page 1

Page 2

MCP8024

PWM2H

5mm x 5mm QFN-40

ISENSE3-78

121314

1511171819

393837

3640343332

+12V

+5V

CAP2

PWM1L

PWM2L

PWM3H

PWM3L

DE2

CAP1

ISENSE2-

IOUT2

ISENSE3+

LV_OUT1

HV_IN1

LSC

I_SENSE1+

I_SENSE1-

LSB

LSA

GND

PWM1H

IOUT3

ISENSE2+

ILIMIT_OUT

I_OUT1

PHA

PHB

PHC

HSC

HSB

HSA

PWM1L

7mm x 7mm TQFP-48

131415

181920

434241

404438

+12V

+5V

CAP1

PWM2L

PWM3H

PWM3L

DE2

LSB

I_SENSE1+

I_SENSE1-

LSA

GND

PWM1H

ISENSE2+

ILIMIT_OUT

I_OUT1

PHA

PHB

PHC

HSC

HSB

HSA

CAP2

LSC

48 PWM2H

ISENSE3-

IOUT2

ISENSE3+

LV_OUT1

HV_IN1

LV_OUT2

IOUT3

ISENSE2-

HV_IN2

GND

MCP8024 MCP8024

Package Types

DS20005228A-page 2  2013 Microchip Technology Inc.

Page 3

GATE

CONTROL

LOGIC

PWM1H

PWM1L

PWM2H

PWM2L

PWM3H

PWM3L

HV_IN1

I_OUT1

PHA PHB PHC

PGND

ILIMIT_OUT

MOTOR CONTROL UNIT

COMMUNICATION PORT BIAS GENERATOR

+12V

HSA

HSB

HSC

I_SENSE1+

LSA

LSB

LSC

I_SENSE1-

VBA VBB VBC

LV_OUT1

LEVEL

TRANSLATOR

VDD

I_SENSE2+

I_SENSE2-

I_SENSE3+

I_SENSE3-

I_OUT2

I_OUT3

DRIVER

FAULT

LDO

BUCK SMPS

SUPERVISOR

LDO

CHARGE PUMP

DE2

VDD

+5V

LX FB

+12V

CAP2

CAP1

ILIMIT_REF

HV_IN2

LV_OUT2

Functional Block Diagram

MCP8024

 2013 Microchip Technology Inc. DS20005228A-page 3

Page 4

MCP8024

GATE

CONTROL

LOGIC

PWM1H

PWM1L

PWM2H

PWM2L

PWM3H

PWM3L

HV_IN1

I_OUT1

PHA

PHB

PHC

PGND

ILIMIT_OUT

MOTOR CONTROL UNIT

COMMUNICATION PORT

+12V

HSA

HSB

HSC

I_SENSE1+

LSA

LSB

LSC

I_SENSE1-

VBA

VBB

VBC

LV_OUT1

LEVEL

TRANSLATOR

VDD

I_SENSE2+

I_SENSE2-

I_SENSE3+

I_SENSE3-

I_OUT2

I_OUT3

DRIVER

FAULT

IIIII

III

OOO

+12V

DE2

BIAS GENERATOR

LDO

BUCK SMPS

SUPERVISOR

VDD

LDO

+5VLXFB

+12V

CAP2

CHARGE PUMP

VADJ

ILIMIT_REF

CAP1

HV_IN2

LV_OUT2

100 nF

Ceramic

Typical Application Circuit

DS20005228A-page 4  2013 Microchip Technology Inc.

Page 5

MCP8024

1.0 ELECTRICAL

CHARACTERISTICS

ESD and Latch-up protection: V

, HV_IN1 pins 12 kV HMM and  750V CDM

All other pins......................  4 kV HBM and  750V CDM

Latch-up protection - all pins............................... > 100 mA

Absolute Maximum Ratings †

Input Voltage, VDD........................................................+46.0V

Input Voltage, < 100 ms Transient ...............................+48.0V

Internal Power Dissipation ...........................Internally-Limited

Operating Ambient Temperature Range .......-40°C to +150°C

Operating Junction Temperature (Note 1).....-40°C to +160°C

Transient Junction Temperature* ................................+170°C

Storage temperature (Note 1) .......................-55°C to +150°C

Digital I/O .......................................................... -0.3V to 5.5V

LV Analog I/O.................................................... -0.3V to 5.5V

† Notice: Stresses above those listed under “Maximum

Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

* Notice: Transient junction temperatures should not

exceed one second in duration. Sustained junction temperatures above 170°C may impact the device reliability.

AC/DC CHARACTERISTICS

Electrical Specifications: Unless otherwise noted T

Parameters Symbol Min. Typ. Max. Units Conditions

Power Supply Input

Input Operating Voltage V

Transient Maximum Voltage V

Input Quiescent Current I

DDmax

Digital Input/Output DIGITAL

Digital Open-Drain Drive

DIGITAL

Strength

Digital Input Rising Threshold V

Digital Input Falling Threshold V

Digital Input Hysteresis V

Digital Input Current I

DIG_HI_TH

DIG_LO_TH

DIG_HYS

DIG

Analog Low-Voltage Input ANALOG

Analog Low-Voltage Output ANALOG

VOUT

BIAS GENERATOR +12V Regulated Charge Pump

Charge Pump Current I

Charge Pump Voltage V

Charge Pump Start CP

START

Note 1: The maximum allowable power dissipation is a function of ambient temperature, the maximum allowable

junction temperature and the thermal resistance from junction to air (i.e., T maximum allowable power dissipation may cause the device operating junction temperature to exceed the maximum 160°C rating. Sustained junction temperatures above 150°C can impact the device reliability and OTP data retention.

2: 1000 hour cumulative maximum for OTP data retention (typical).

= -40°C to +150°C.

6.0

— —

28.0 40

V Operating

— — 48 V < 100 ms

I/O

IOL

— — — — — —

0—5.5V

—1—mAVDS < 50 mV

— 171 197 200 200 900

—

220

— —

500

—

AVDD = 13V,

1.26 — — V

——0.54V

— 500 — mV

VIN

— —

0 — 5.5 V Excludes high voltage

0—V

0.2

100

—

OUT5

µA V

V Excludes high voltage

20——mAVDD = 9.0V

+10 2 * V

—VVDD = 9.0V, ICP = 20 mA

11.0 11.5 — V VDD falling

Shutdown

disabled, CE = 0V, T disabled, CE = 0V, T disabled, CE = 0V, T disabled, CE = 0V, T active, CE > V

= 3.0V

DIG

=0V

DIG

, TJ, JA). Exceeding the

DIG_HI_TH

= 25°C = 85°C = 130°C = 150°C

 2013 Microchip Technology Inc. DS20005228A-page 5

Page 6

MCP8024

AC/DC CHARACTERISTICS (CONTINUED)

Electrical Specifications: Unless otherwise noted T

Parameters Symbol Min. Typ. Max. Units Conditions

= -40°C to +150°C.

Charge Pump Stop CP

Charge Pump Frequency

(50% charging /

STOP

FSW

— 12.0 12.5 V VDD rising

——76.800—

—

kHz VDD = 9.0V

= 12.5V (stopped)

50% discharging)

Charge Pump Switch Resistance

Output Voltage V

Output Voltage Tolerance |TOLV

Output Current I

Output Current Limit I

Output Voltage Temperature

TCV

RDSON

OUT12

OUT

LIMIT

OUT12

—14— Ω RDSON sum of high side and

low side

10 12 — V VDD = V

|— — 4.0 %VDD = V

OUT12

+ 1V, I

20 — — mA Average current

30 40 — mA Average current

—50—ppm/°C

OUT

= 1 mA

Coefficient Line Regulation |V

OUT

Load Regulation |V

Dropout Voltage V

OUT/VOUT

DD-VOUT12

OUT

XVDD)|

— 0.1 0.5 %/V 13V < V

|— 0.2 0.5 % I

— 380 — mV I

OUT

< 19V, I

OUT

= 0.1 mA to 15 mA

= 20 mA,

= 20 mA

measurement taken when output voltage drops 2% from no-load value.

Power Supply Rejection Ratio PSRR — 60 — dB f = 1 kHz, I

OUT

= 10 mA

+5V Linear Regulator

Output Voltage V

OUT5

Output Voltage Tolerance |TOLV

Output Current I

Output Current Limit I

Output Voltage Temperature

OUT

LIMIT

|TCV

—5— VVDD = V

|— — 4.0 %

OUT5

20 — — mA Average current

30 40 — mA Average current

|—50—ppm/°C

OUT5

+ 1V, I

OUT

= 1 mA

Coefficient Line Regulation |V

OUT

Load Regulation |V

Dropout Voltage V

OUT

XVDD)|

OUT/VOUT

DD-VOUT5

— 0.1 0.5 %/V 6V < V

|— 0.2 0.5 % I

— 180 350 mV I

OUT

< 19V, I

OUT

= 0.1 mA to 15 mA

= 20 mA,

= 20 mA

measurement taken when output voltage drops 2% from no-load value.

Power Supply Rejection Ratio PSRR — 60 — dB f = 1 kHz, I

OUT

= 10 mA

Buck Regulator

Feedback Voltage V

Feedback Voltage Tolerance TOLV

1.19 1.25 1.31 V

 ——5.0 %IFB = 1 µA

Note 1: The maximum allowable power dissipation is a function of ambient temperature, the maximum allowable

junction temperature and the thermal resistance from junction to air (i.e., T

, TJ, JA). Exceeding the

maximum allowable power dissipation may cause the device operating junction temperature to exceed the maximum 160°C rating. Sustained junction temperatures above 150°C can impact the device reliability and OTP data retention.

2: 1000 hour cumulative maximum for OTP data retention (typical).

DS20005228A-page 6  2013 Microchip Technology Inc.

Page 7

AC/DC CHARACTERISTICS (CONTINUED)

Electrical Specifications: Unless otherwise noted T

Parameters Symbol Min. Typ. Max. Units Conditions

= -40°C to +150°C.

MCP8024

Feedback Voltage Line Regulation

Feedback Voltage Load

VFB/VFB) /

V

VFB / VFB|— 0.10.5 %I

— 0.1 0.5 %/V V

OUT

= 6V to 28V

= 5 mA to 150 mA

Regulation

Feedback Input Bias Current I

Switching Frequency f

Duty Cycle Range DC

PMOS Switch On Resistance R

PMOS Switch Current Limit I

P(MAX)

Ground Current – PWM Mode I

Quiescent Current – PFM

MAX

DSON

GND

-100 — +100 nA Sink/Source

— 461 — kHz

3—96%

—0.6— Ω VDD = 13V, TJ=25°C

—2.5— A

— 1.5 2.5 mA Switching — 150 200 AI

OUT

= 0mA

Mode

Output Voltage Adjust Range V

Output Current I

OUT

2.0 — 5.0 V

150——mA5v

250 — — 3v

Output Power P

OUT

— 750 — mW P = I

OUT

* V

OUT

V oltage Supervisor

Undervoltage Lockout Start UVLO

Undervoltage Lockout Stop UVLO

Undervoltage Lockout

UVLO

STRT

STOP

HYS

—6.06.25 VVDD rising

5.1 5.5 — V VDD falling

0.35 0.5 0.65 V

Hysteresis

Overvoltage Lockout All

OVLO

STOP

— 32.0 33.0 V VDD rising

Functions Disabled

Overvoltage Lockout All

OVLO

STRT

29.0 30.0 — V VDD falling

Functions Enabled

Overvoltage Lockout

OVLO

HYS

1.0 2.0 3.0 V

Hysteresis

Temperature Supervisor

Thermal Warning Temperature (115°C)

WARN

— 72 — % Rising temperature,

percentage of thermal shutdown temperature “MIN”

Thermal Warning Hysteresis T

Thermal Shutdown

WARN

— 15 — °C Falling temperature

160 170 — °C Rising temperature

Temperature Thermal Shutdown Hysteresis T

— 25 — °C Falling temperature

MOTOR CONTROL UNIT Output Drivers

PWMH/L Input Pull-Down R

PULLDN

32 47 62 kΩ

Note 1: The maximum allowable power dissipation is a function of ambient temperature, the maximum allowable

junction temperature and the thermal resistance from junction to air (i.e., T

, TJ, JA). Exceeding the

2: 1000 hour cumulative maximum for OTP data retention (typical).

 2013 Microchip Technology Inc. DS20005228A-page 7

Page 8

MCP8024

AC/DC CHARACTERISTICS (CONTINUED)

Electrical Specifications: Unless otherwise noted T

Parameters Symbol Min. Typ. Max. Units Conditions

= -40°C to +150°C.

Output Driver Source Current I

Output Driver Sink Current I

Output Driver Source Resistance

Output Driver Sink Resistance R

SOURCE

SINK

DSON

0.3 — — A VDD = 12V, H[A:C], L[A:C]

—17— Ω I

= 10 mA, VDD = 12V,

OUT

H[A:C], L[A:C]

—17— Ω I

= 10 mA, VDD = 12V,

OUT

H[A:C], L[A:C]

Output Driver UVLO

UVLO

7.2 8.0 — V

Threshold

Output Driver Bootstrap Voltage (w/ respect to ground)

Output Driver HS Drive Voltage

Output Driver LS Drive

BOOTSTRAP

— —

8.0

-5.5

— —

44 48

12—13.5

—

V Continuous

< 100 ms

V With respect to Phase pin

With respect to ground

8.0 12 13.5 V With respect to ground

Voltage

Output Driver Phase Pin

PHASE

-5.5V — 34 V With respect to ground

Voltage

Output Driver Short Circuit Protection Threshold

Output Driver Short Circuit Detected Propagation Delay

Output Driver Turn-off

SC_DEL

DEL_OFF

— — — — —

— — — —

—

0.250

0.500

0.750

1.000

—

430

10 —

— — — — —

— — — —

V Set by DE2 CONFIG[1:0] word

ns C

— 100 250 ns C

00 - Default 01 10 11

= 1000 pF, V

LOAD

=12V, detection after blanking detection during blanking, value is delay after blanking

= 1000 pF, V

LOAD

=12V,

Propagation Delay

Output Driver Turn-on

DEL_ON

— 100 250 ns C

= 1000 pF, V

LOAD

=12V,

Propagation Delay

Standby to Motor Operational

= 10 µF)

LOAD

CE Low to Standby State CE Fault Clearing Pulse

MOTOR

STANDBY

FAULT_ CLR

—

— —

µs

CE High-Low-High Transition < 100 µs (Fault Clearing)

— 10

—

10 — —

Standby state to Operational state

µs

Time after CE = 0V

µs

CE High-Low-High Transition Time

Current Sense Amplifier

Input Offset Voltage V

Input Offset Temperature Drift V

Input Bias Current I

Common Mode Input Range V

CMR

/T

-3.0 — +3.0 mV VCM = 0V

— 2.0 — V/°C VCM = 0V

-1 — +1 µA

-0.3 — 3.5 V

= -40°C to +150°C

Note 1: The maximum allowable power dissipation is a function of ambient temperature, the maximum allowable

junction temperature and the thermal resistance from junction to air (i.e., T

, TJ, JA). Exceeding the

2: 1000 hour cumulative maximum for OTP data retention (typical).

DS20005228A-page 8  2013 Microchip Technology Inc.

Page 9

AC/DC CHARACTERISTICS (CONTINUED)

Electrical Specifications: Unless otherwise noted T

Parameters Symbol Min. Typ. Max. Units Conditions

= -40°C to +150°C.

MCP8024

Common Mode Rejection Ratio CMRR 65 80 — dB Freq = 1 kHz, I

Maximum Output Voltage

, V

0.05 — 4.5 V I

= 200 µA

OUT

Swing Slew Rate SR — 7—V/sSymmetrical

Gain Bandwidth Product GBWP — 10.0 — MHz

Current Comparator

HYS

—10—mV

Hysteresis

Current Comparator Common

CC_CMR

1.0 — 4.5 V

Mode Input Range

Current Limit DAC

Resolution — 8 — Bits

Output Voltage Range V

Output Voltage V

Input to Output Delay T

, V

DAC

DELAY

0.991 — 4.503 V I

— — — —

—

0.991

1.872

4.503

— — — —

V Code * 13.77 mV/Bit + 0.991V

= 1 mA

OUT

Code 00H Code 40H Code FFH

— 50 — µs 5 time constants of 100 kHz filter

Integral Nonlinearity INL -0.5 — +0.5 %FSR %Full Scale Range

Differential Nonlinearity DNL -50 — +50 %LSB %LSB

ILIMIT_OUT Sink Current

OUT

—1—mAV

ILIMIT_OUT

<= 50mV

(Open-Drain)

V oltage Level Translator

High-Voltage Input Range VIN 0 — VDD V

Low-Voltage Output Range VOUT 0 — 5.0V V

Input Pull-up Resistor RPU 20 30 47 kΩ

High-Level Input Voltage VIH 0.60 — — V

Low-Level Input Voltage VIL — — 0.40 V

Input Hysteresis VHYS — — 0.30 V

VDD = 15V

Propagation Delay TLV_OUT — 3.0 6.0 µs

Maximum Communication

FMAX — — 20 kHz

Frequency

Low-Voltage Output Sink

IOL — 1 — mA V

<= 50 mV

OUT

Current (Open-Drain)

OTP Data Retention

OTP Cell High Temperature

HTOL — 1000 — Hours T

= 150°C (Note 2)

Operating Life

OTP Cell Operating Life — 10 — Years T

= 85°C

= 10 µA

Note 1: The maximum allowable power dissipation is a function of ambient temperature, the maximum allowable

junction temperature and the thermal resistance from junction to air (i.e., TA, TJ, JA). Exceeding the maximum allowable power dissipation may cause the device operating junction temperature to exceed the maximum 160°C rating. Sustained junction temperatures above 150°C can impact the device reliability and OTP data retention.

2: 1000 hour cumulative maximum for OTP data retention (typical).

 2013 Microchip Technology Inc. DS20005228A-page 9

Page 10

MCP8024

TEMPERATURE SPECIFICATIONS

Parameters Sym. Min. Typ. M ax. Units Conditions

Temperature Ranges (Notes 1)

Specified Temperature Range T

Operating Temperature Range T

Storage Temperature Range T

Thermal Package Resistance

5mm x 5mm QFN-40 

7mm x 7mm TQFP-48-EP 

Note 1: The maximum allowable power dissipation is a function of ambient temperature, the maximum allowable

junction temperature and the thermal resistance from junction to air (i.e., TA, TJ, JA). Exceeding the maximum allowable power dissipation will cause the device operating junction temperature to exceed the maximum 150°C rating. Sustained junction temperatures above 150°C can impact the device reliability.

2: 1000 hour cumulative maximum for OTP data retention (typical).



ESD, SUSCEPTIBILITY, SURGE, AND LATCH-UP TESTING

Parameter Standard and Test Condition Value

Input voltage surges ISO 16750-2 28V for 1 minute,

ESD HBM with 1.5 k / 100 pF ESD-STM5.1-2001

ESD CDM (Charged Device Model, fieldinduced method – replaces machine-model method)

Latch-up Susceptibility AEC Q100-004, 150°C >100 mA

-40 +150 °C

-55 +150 °C (Note 2)

— —

JESD22-A114E 2007 CEI/IEC 60749-26: 2006 AEC-Q100-002-Ref_D

ESD-STM5.3.1-1999 +750 V all pins

5.2

30 15

——°C/W 4-Layer JC51-7 standard board,

natural convection

——°C/W

45V for 0.5 seconds

4 kV

DS20005228A-page 10  2013 Microchip Technology Inc.

Page 11

MCP8024

0.000

0.002

0.004

0.006

0.008

0.010

-45 -30 -15 0 15 30 45 60 75 90 105 120 135 150

Temperature (°C)

OUT

= 5V

OUT

= 12V

0.00

0.05

0.10

0.15

0.20

0.25

0.30

0.35

-45 -30 -15 0 15 30 45 60 75 90 105 120 135 150

Temperature (°C)

OUT

= 5V

OUT

= 12V

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

0.01 0.10 1.00 10.00 100.00 1000.00

Frequency (kHz)

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

0.01 0.10 1.00 10.00 100.00 1000.00

Frequency (kHz)

0.0

20.0

40.0

60.0

80.0

100.0

120.0

140.0

7 1013161922252831

Voltage (V)

5V LDO

12V LDO

-100

-50

100

150

200

0 50 100 150 200 250

Volts (mV)

Time (µs)

Vin = 14V

Vin = 15V

Vout (AC)

Cin = Cout = 10 µF Iout = 20 mA

2.0 TYPICAL PERFORMANCE CURVES

Note: The graphs and tables provided following this note are a statistical summary based on a limited number of

samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range.

Note: Unless otherwise indicated: T

= +25°C; Junction Temperature (TJ) is approximated by soaking the device under

test to an ambient temperature equal to the desired junction temperature. The test time is small enough such that the rise in Junction temperature over the Ambient temperature is not significant.

PSRR (dB)

Line Reg (%/V)

FIGURE 2-1: LDO Line Regulation vs Temperature.

FIGURE 2-4: 12 V LDO Power Supply Ripple Rejection vs Frequency.

Load Reg (%)

FIGURE 2-2: LDO Load Regulation vs Temperature.

PSRR (dB)

FIGURE 2-3: 5V LDO Power Supply Ripple Rejection vs Frequency.

 2013 Microchip Technology Inc. DS20005228A-page 11

Current (mA)

FIGURE 2-5: LDO Short Circuit Current vs Input Voltage. .

Volts (V)

FIGURE 2-6: 5V LDO Dynami c Lin es tep Rising V

Page 12

MCP8024

-180

-120

-60

120

180

0 50 100 150 200 250

Volts (mV)

Time (µs)

Vin = 15V

Vin = 14V

Vout (AC)

Cin = Cout = 10 µF Iout = 20 mA

-140

-70

140

210

280

0 50 100 150 200 250

Volts (mV)

Time (µs)

Vin = 14V Vin = 15V

Vout (AC)

Cin = Cout = 10 µF Iout = 20 mA

-180

-120

-60

120

180

0 50 100 150 200 250

Volts (mV)

Time (µs)

Vin = 15V

Vin = 14V

Vout (AC)

Cin = Cout = 10 µF Iout = 20 mA

-40

-30

-20

-10

0 5 10 15 20 25

Time (ms)

Vout (AC)

Vin = 14V Vout = 5V Cin = Cout = 10 µF Iout = 1 mA to 20 mA Step

-40

-30

-20

-10

0 5 10 15 20 25

Time (ms)

Vout (AC)

Vin = 14V Vout = 5V Cin = Cout = 10 µF Iout = 20 mA to 1 mA Step

-40

-30

-20

-10

0 5 10 15 20 25

Time (ms)

Vout (AC)

Vin = 14V Vout = 12V Cin = Cout = 10 µF Iout = 1 mA to 20 mA Step

Note: Unless otherwise indicated: T

= +25°C; Junction Temperature (TJ) is approximated by soaking the device under

test to an ambient temperature equal to the desired junction temperature. The test time is small enough such that the rise in Junction temperature over the Ambient temperature is not significant.

Volts (V)

FIGURE 2-7: 5V LDO Dynamic Linestep Falling V

Vout (mV)

FIGURE 2-10: 5V LDO Dynamic Loadstep Rising Current.

Volts (V)

FIGURE 2-8: 12V LDO Dynamic Linestep Rising V

Volts (V)

FIGURE 2-9: 12V LDO Dynamic Linestep Falling V

DS20005228A-page 12  2013 Microchip Technology Inc.

Vout (mV)

FIGURE 2-11: 5V LDO Dynamic Loadstep Falling Current.

Vout (mV)

FIGURE 2-12: 12V LDO Dynamic Loadstep Rising Current.

Page 13

MCP8024

-40

-30

-20

-10

0 5 10 15 20 25

Time (ms)

Vout (AC)

Vin = 14V Vout = 12V Cin = Cout = 10 µF Iout = 20 mA to 1 mA Step

10.0

10.5

11.0

11.5

12.0

12.5

13.0

0 5 10 15 20 25 30

Vin (V)

Vout = 12V Cin = Cout = 10 µF Iout = 20 mA

Charge Pump

Hysteresis

200

400

600

800

1000

1200

-45 -20 5 30 55 80 105 130 155

Temperature (°C)

CE Low

CE High

0.0 0.5 1.0 1.5 2.0 2.5

Time ( ms)

PHA

PHB

PHC

0 102030405060

Time (µs)

Dead Time

PWMxH

PWMxL

0.10 0.12 0.14 0.16 0.18 0.20

Time (µs)

SnubberNo Snubber

Switch ON

Note: Unless otherwise indicated: T

= +25°C; Junction Temperature (TJ) is approximated by soaking the device under

test to an ambient temperature equal to the desired junction temperature. The test time is small enough such that the rise in Junction temperature over the Ambient temperature is not significant.

Vout (mV)

FIGURE 2-13: 12V LDO Dynamic Loadstep -

BEMF

FIGURE 2-16: Trapezoidal Back EMF.

Falling Current.

Vout (V)

FIGURE 2-14: 12V LDO Output Voltage vs Rising Input Voltage.

Quiescent Current (µA)

FIGURE 2-15: Quiescent Current vs Temperature.

 2013 Microchip Technology Inc. DS20005228A-page 13

FIGURE 2-17: PWM Deadtime.

(V)

FIGURE 2-18: Buck Snubber Turn On.

Page 14

MCP8024

-4

0.06 0.08 0.10 0.12 0.14 0.16 0.18

Time (µs)

Snubber

No Snubber

Switch Off

0.00

5.00

10.00

15.00

20.00

25.00

30.00

-40 -15 10 35 60 85 110 135 160

RDSON (

)

Temperature (°C)

Hx Lowside MOSFET

Lx Lowside MOSFET

Lx Highside MOSFET

Note: Unless otherwise indicated: T

= +25°C; Junction Temperature (TJ) is approximated by soaking the device under

test to an ambient temperature equal to the desired junction temperature. The test time is small enough such that the rise in Junction temperature over the Ambient temperature is not significant.

(V)

FIGURE 2-19: Buck Snubber Turn Off.

Hx Highside MOSFET

FIGURE 2-20: Gate Driver RDS Temperature.

DS20005228A-page 14  2013 Microchip Technology Inc.

Page 15

3.0 PIN DESCRIPT IONS

3.1 Functional Pin Descriptions

MCP8024

Pin No.

QFN

1 48 PWM2H I Digital input, phase B high-side control, 47K pulldown 2 1 PWM1L I Digital input, phase A low-side control, 47K pulldown 3 2 PWM1H I Digital input, phase A high-side control, 47K pulldown 4 3 CE I Digital input, device enable, 47K pulldown

- 4 LV_OUT2 O Digital logic level translated output interface, open drain

- 5 HV_IN2 I High-voltage input interface, 30K pullup via Configuration register 0 bit 6 5 6 HV_IN1 I High-voltage input interface, 30K pullup via Configuration register 0 bit 6

- 7 PGND Power Power 0V reference 6 8 LV_OUT1 O Digital logic level translated output interface, open drain 7 9 I_OUT3 O Motor phase current sense amplifier output 8 10 ISENSE3- I Motor phase current sense amplifier inverting input 9 11 ISENSE3+ I Motor phase current sense amplifier non-inverting input 10 12 I_OUT2 O Motor phase current sense amplifier output 11 13 ISENSE2- I Motor phase current sense amplifier inverting input 12 14 ISENSE2+ I Motor phase current sense amplifier non-inverting input 13 15 /ILIMIT_OUT O Current limit comparator, MOSFET driver fault output, open drain 14 16 I_OUT1 O Motor current sense amplifier output 15 17 ISENSE1- I Motor current sense amplifier inverting input 16 18 ISENSE1+ I Motor current sense amplifier non-inverting input 17 19,20 PGND Power Power 0V reference 18 21 LA O Phase A low-side N-Channel MOSFET driver, active-high 19 22 LB O Phase B low-side N-Channel MOSFET driver, active-high 20 23 LC O Phase C low-side N-Channel MOSFET driver, active-high

- 24 PGND Power Power 0V reference 21 25 HC O Phase C high-side N-Channel MOSFET driver, active-high 22 26 HB O Phase B high-side N-Channel MOSFET driver, active-high 23 27 HA O Phase A high-side N-Channel MOSFET driver, active-high 24 28 PHC I/O Phase C high-side MOSFET driver reference, back EMF sense input 25 29 PHB I/O Phase B high-side MOSFET driver reference, back EMF sense input 26 30 PHA I/O Phase A high-side MOSFET driver reference, back EMF sense input 27 31 VBC Power Phase C high-side MOSFET driver bias 28 32 VBB Power Phase B high-side MOSFET driver bias 29 33 VBA Power Phase A high-side MOSFET driver bias 30 34 +12V Power Analog circuitry and low-side gate drive bias

- 35,36 PGND Power Power 0V reference 31 37 LX Power Buck regulator switch node, external inductor connection 32 38, 39 VDD Power Input supply 33 40 FB I Buck regulator feedback node 34 41 +5V Power Internal circuitry bias 35 42 CAP2 Power Charge pump flying capacitor input 36 43 CAP1 Power Charge pump flying capacitor input 37 44 DE2 O Voltage and temperature supervisor output, open drain 38 45 PWM3L I Digital input, phase C low-side control, 47K pulldown 39 46 PWM3H I Digital input, phase C high-side control, 47K pulldown 40 47 PWM2L I Digital input, phase B low-side control, 47K pulldown EP EP PGND Power Exposed Pad, Connect to Power 0V reference

Pin No.

TQFP

Symbol I/O Description

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MCP8024

3.2 V

Connect VDD to the main supply voltage. This voltage must not exceed the maximum operating limits of the device. Connect a bulk capacitor close to this pin for good load step performance and transient protection.

The type of capacitor used can be ceramic, tantalum or aluminum electrolytic. The low ESR characteristics of the ceramic will yield better noise and PSRR performance at high frequency.

3.3 PGND, Exposed Pad (EP)

Device ground. The PCB ground traces should be short, wide, and form a STAR pattern to the power source. The Exposed Pad (EP) PCB area should be a copper pour with thermal vias to help transfer heat away from the device.

3.4 +12V

+12 volt Low Dropout (LDO) voltage regulator output. The +12V LDO may be used to power external devices such as Hall-effect sensors or amplifiers. The LDO requires an output capacitor for stability. The positive side of the output capacitor should be physically located as close to the +12V pin as is practical. For most applications, 4.7 µF of capacitance will ensure stable operation of the LDO circuit.

The type of capacitor used can be ceramic, tantalum or aluminum electrolytic. The low ESR characteristics of the ceramic will yield better noise and PSRR performance at high frequency.

3.5 +5V

+5 volt Low Dropout (LDO) voltage regulator output. The +5V LDO may be used to power external devices such as Hall-effect sensors or amplifiers. The LDO requires an output capacitor for stability. The positive side of the output capacitor should be physically located as close to the +5V pin as is practical. For most applications, 4.7 µF of capacitance will ensure stable operation of the LDO circuit.

The type of capacitor used can be ceramic, tantalum or aluminum electrolytic. The low ESR characteristics of the ceramic will yield better noise and PSRR performance at high frequency.

3.6 LX

Buck regulator switch node external inductor connection. Connect this pin to the external inductor chosen for the buck regulator.

3.7 FB

Buck regulator feedback node that is compared with internal 1.25V reference voltage. Connect this pin to a resistor divider that sets the buck regulator output

voltage. Connecting this pin to the +5V LDO output disables the buck regulator.

3.8 CAP1, CAP2

Charge pump flying capacitor inputs. Connect the charge pump capacitor across these two pins.

3.9 CE

Chip Enable input used to enable/disable the output driver and on-board functions. When CE is high, all device functions are enabled. When CE is low, the device operates in Reduced mode. The H-Bridge, current amplifiers and 12V LDO are disabled. The buck regulator, 5V LDO, DE2, voltage and temperature sensor functions are not affected.

The CE is also used to clear any hardware faults. When a fault occurs, the CE input may be used to clear the fault by setting the pin low and then high again. The fault is cleared by the rising edge of the CE signal if the hardware fault is no longer active.

The CE pin has an internal 47K pulldown.

3.10 I_OUT1, I_OUT2, I_OUT3

Current sense amplifier output. May be used with feedback resistors to set the current sense gain.

3.1 1 ISENSE1, ISENSE2, ISENSE3 +/-

Current sense amplifier inverting and non-inverting inputs. Used in conjunction with I_OUTx pins to set current sense gain.

3.12 /ILIMIT_OUT

Current limit output signal. The open-drain output goes low when the current sensed by current sense amplifier 1 exceeds the value set by the internal current reference DAC. The DAC has an offset of 0.991V (typical) which represents zero current flow. The open-drain output will also go low while a motor fault is active.

3.13 PWM1H, PWM2H, PWM3H

Digital PWM inputs for high-side driver control. Each input has a 47K pulldown to ground. The PWM signals may contain dead-time timing or the system may use the Configuration register 2 to set the dead time.

3.14 PWM1L, PWM2L, PWM3L

Digital PWM inputs for low-side driver control. Each input has a 47K pulldown to ground. The PWM signals may contain dead-time timing or the system may use the Configuration register 2 to set the dead time.

DS20005228A-page 16  2013 Microchip Technology Inc.

Page 17

3.15 LA, LB, LC

Low-side N-channel MOSFET drive signal. Connect to the gate of the external MOSFETs. A low-impedance resistor may be used between these pins and the MOSFET gates to limit current and slew rate.

3.16 HA, HB, HC

High-side N-channel MOSFET drive signal. Connect to the gate of the external MOSFETs. A low-impedance resistor may be used between these pins and the MOSFET gates to limit current and slew rate.

3.17 PHA, PHB, PHC

Phase signals from motor. Provides high-side Nchannel MOSFET driver reference and Back EMF sense input. The phase signals are also used with the bootstrap capacitors to provide high-side gate drive via the VBx inputs.

3.18 VBA, VBB, VBC

MCP8024

High-side MOSFET driver bias. Connect these pins between the bootstrap charge pump diode cathode and bootstrap charge pump capacitor. The 12V LDO output is used to provide 12V at the diode anodes. The phase signals are connected to the other side of the bootstrap charge pump capacitors.

3.19 DE2

Open-drain communications node. The DE2 communications is a half-duplex 9600 baud, 8-bit, no parity communications link. The open-drain DE2 pin must be pulled high by an external pull-up resistor.

3.20 HV_IN1, HV_IN2, LV_OUT1,LV_OUT2

Unidirectional digital level translators. Translates digital input signal on the HV_INx pin to a low-level digital output signal on the LV_OUTx pin. The HV_INx pins have internal 30K pullups to V Configuration register 0 bit 6. The Configuration register 0 bit 6 is only sampled during CE = 0. The HV_IN1 pin has higher ESD protection than the HV_IN2 pin. The higher ESD protection makes the HV_IN1 pin better suited for connection to external switches.

LV_OUT1 and LV_OUT2 are open-drain outputs. An external pull-up resistor to the low-voltage logic supply is required.

that are controlled by

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Page 18

MCP8024

OUTPUT

CONTROL

LOGIC

VIN

CURRENT_REF

VDD-12V

BANDGAP

REFERENCE

4.0 DETAILED DESCRIPTION

4.1 BIAS GENERATOR

The internal bias generator controls three voltage rails. Two fixed-output low-dropout linear regulators, an adjustable buck switch-mode power converter, and an unregulated charge pump are controlled through the bias generator. In addition, the bias generator performs supervisory functions.

4.1.1 +12V LOW-DROPOUT LINEAR REGULATOR (LDO)

The +12V rail is used for bias of the 3-phase power MOSFET bridge.

The regulator is capable of supplying 20mA of external load current. The regulator has a minimum overcurrent limit of 30 mA.

The low-dropout regulators require an output capacitor connected from VOUT control loop. A minimum of 4.7F ceramic output capacitance is required for the 12V LDO.

to GND to stabilize the internal

4.1.2 +5V LOW-DROPOUT LINEAR REGULATOR (LDO)

The +5V LDO is used for bias of an external microcontroller, the internal current sense amplifier and the gate control logic.

The +5V LDO is capable of supplying 20mA of external load current. The regulator has a minimum overcurrent limit of 30 mA. If additional external current is required, the buck switch-mode power converter should be utilized.

A minimum of 4.7F ceramic output capacitance is required for the 5V LDO.

4.1.3 BUCK SWITCH-MODE POWER

The SMPS is a high-efficiency, fixed-frequency, stepdown DC-DC converter. The SMPS provides all the active functions for local DC-DC conversion with fast transient response and accurate regulation.

During normal operation of the buck power stage, Q1 is repeatedly switched on and off with the on and off times governed by the control circuit. This switching action causes a train of pulses at the LX node which are filtered by the L/C output filter to produce a DC output voltage, V block diagram of the SMPS.

CONVERTER (SMPS)

. Figure 4-1 depicts the functional

FIGURE 4-1: SMPS Functional Block Diagram.

The SMPS is designed to operate in Discontinuous Conduction Mode (DCM) with Voltage mode control and current limit protection. The SMPS is capable of supplying 5V, 150mA to an external load at a fixed switching frequency of 460 kHz with an input voltage of 6V. The output of the SMPS is power limited. Therefore, for a programmed output voltage of 3V, the SMPS will be capable of supplying 250mA to an external load. An external diode is required between the LX pin and ground. The diode will be required to handle the inductor current when the switch is off. The diode is external to the device to reduce substrate currents and power dissipation caused by the switcher. The external diode carries the current during the switch off time, eliminating the current path back through the device.

At light loads the SMPS enters Pulse Frequency Modulation (PFM), improving efficiency at the expense of higher output voltage ripple. The PFM circuitry provides a means to disable the SMPS as well. If the SMPS is not utilized in the application, connecting the feedback pin (FB) to an external 2.5V-to-5.0V supply will force the SMPS to a shutdown state.

DS20005228A-page 18  2013 Microchip Technology Inc.

Page 19

MCP8024

MAX

VO1

--------–





T

2 I

OCRIT



----------------------------------------------

The maximum inductor value for operation in Discontinuous Conduction mode can be determined by the following equation.

EQUATION 4-1: L

Using the L

inductor value calculated using

MAX

SIMPLIFIED

MAX

Equation 4-1 will ensure Discontinuous Conduction

mode operation for output load currents below the critical current level, I

. For example, with an output

O(CRIT)

voltage of +5V, a standard inductor value of 4.7H will ensure Discontinuous Conduction mode operation with an input voltage of 6V, a switching frequency of 468 kHz, and a critical load current of 150 mA.

The output voltage is set by using a resistor divider network. The resistor divider is connected between the inductor output and ground. The divider common point is connected to the FB pin which is then compared to an internal 1.25V reference voltage.

The Buck regulator will set a Status bit and send a status message to the host whenever the input switching current exceeds two amperes peak (typical). The bit will be cleared when the peak input switching current drops back below the two ampere (typical) limit.

The Buck regulator will set a Status bit and send a status message to the host whenever the output voltage drops below 90% of the rated output voltage. The bit will be cleared when the output voltage returns to 94% of rated value.

If the Buck regulator output voltage falls below 80% of rated output voltage, the system will shutdown with a “Brown-out Error”. This will notify the Host of a power failure and subsequent loss of configuration.

The Voltage Supervisor is designed to shutdown the buck regulator when V

rises above OVLO

STOP

When shutting down the buck regulator is not desirable, the user should add a voltage suppression device to the V rising above OVLO

input in order to prevent VDD from

STOP

The Voltage Supervisor is also designed to shutdown the buck regulator when V

falls below UVLO

STOP

4.1.4 CHARGE PUMP

An unregulated charge pump is utilized to boost the input to the +12V LDO during low-input conditions. When the input bias to the device (V

, the charge pump is activated. When activated,

START

2 x V

is presented to the input of the +12V LDO,

which maintains a minimum +10V at its output.

The typical charge pump flying capacitor is a 0.1 µF to

1.0 µF ceramic capacitor.

) drops below

4.1.5 SUPERVISOR

The bias generator incorporates a voltage supervisor and a temperature supervisor.

4.1.5.1 Voltage Supervisor

The voltage supervisor protects the device, external power MOSFETs, and the external microcontroller from damage due to overvoltage or undervoltage of the input supply, VDD.

In the event of an undervoltage condition, V

< +5.5V, the motor drivers are switched off. The bias generator, communication port, and the remainder of the motor control unit remain active. The failure state is flagged on the DE2 pin with a status message. In extreme overvoltage conditions, V

> +32V, all func-

tions are turned off.

4.1.5.2 Temperature Supervisor

An integrated temperature sensor self protects the device circuitry. If the temperature rises above the overtemperature shutdown threshold, all functions are turned off. Active operation resumes when the temperature has cooled down below a set hysteresis value and the fault has been cleared by toggling CE.

It is desirable to signal the microcontroller with a warning message before the overtemperature threshold is reached. The microcontroller should take appropriate actions to reduce the temperature rise. The method to signal the microcontroller is through the DE2 pin.

4.2 MOTOR CONTROL UNIT

The motor control unit is comprised of the following:

• External Drive for a 3-Phase Bridge with NMOS/

NMOS MOSFET pairs

• Three Motor Current Sense Amplifiers

• Motor Overcurrent Comparator

4.2.1 MOTOR CURRENT SENSE

CIRCUITRY

The internal motor current sense circuitry consists of an operational amplifier and comparator. The amplifier output is presented to the inverting comparator input and as an output to the microcontroller. The noninverting comparator input is connected to an internally programmable 8-bit DAC. A selectable motor current limit threshold may be set with a SET_ILIMIT message from the host to the MCP8024 via the DE2 communications link. The 8-bit DAC is powered by the 5V supply. The DAC output voltage range is 0.991V to

4.503V. The DAC has a bit value of (4.503V - 0.991V) / (2^8 - 1) = 13.77 mV/bit. A DAC input of 00H yields a DAC output voltage of 0.991V. The default power-up DAC value is 40H (1.872V). The DAC uses a 100 kHz filter. Input code to output voltage delay is

 2013 Microchip Technology Inc. DS20005228A-page 19

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MCP8024

approximately five time constants ~= 50 µs. The desired current sense gain is established with an external resistor network.

Note: The motor current limit comparator output

is internally ‘OR’d with the DRIVER FAULT output of the driver logic block. The microcontroller should monitor the comparator output and take appropriate actions. The motor current limit comparator circuitry does not disable the motor drivers when an overcurrent situation occurs. Only one current limit comparator is provided. The MCP8024 provides three current sense amplifiers which can be used for implementation of advanced control algorithms such as Field Oriented Control (FOC).

The comparator output may be employed as a current limit. Alternatively, the current sense output can be employed in a chop-chop PWM speed loop for any situations where the motor is being accelerated, either positively or negatively. An analog chop-chop speed loop can be implemented by hysteretic control or fixed off-time of the motor current. This makes for a very robust controller as the motor current is always in instantaneous control.

A sense resistor in series with the bridge ground return provides a current signal for both feedback and current limiting. This resistor should be non-inductive to minimize ringing from high di/dt. Any inductance in the power circuit represents potential problems in the form of additional voltage stress and ringing, as well as increasing switching times. While impractical to eliminate, careful layout and bypassing will minimize these effects. The output stage should be as compact as heat sinking will allow, with wide, short traces carrying all pulsed currents. Each half-bridge should be separately bypassed with a low ESR/ESL capacitor, decoupling it from the rest of the circuit. Some layouts will allow the input filter capacitor to be split into three smaller values, and serve double duty as the halfbridge bypass capacitors.

Note: With a chop-chop control, motor current

always flows through the sense resistor. When the PWM is off, however, the flyback diodes, or synchronous rectifiers, conduct, causing the current to reverse polarity through the sense resistor.

The current sense resistor is chosen to establish the peak current limit threshold, which is typically set 20% higher than the maximum current command level to provide overcurrent protection during abnormal conditions. Under normal circumstances with a properly compensated current loop, peak current limit will not be exercised.

4.2.2 MOTOR CONTROL

The commutation loop of a BLDC motor control is a Phase-Locked Loop (PLL) which locks to the rotor’s position. Note that this inner loop does not attempt to modify the position of the rotor, but modifies the commutation times to match whatever position the rotor has. An outer speed loop changes the rotor velocity, and the commutation loop locks to the rotor’s position to commutate the phases at the correct times.

4.2.2.1 Sensorless Motor Control

Many control algorithms can be implemented with the MCP8024 in conjunction with a microcontroller. The following discussion provides a starting point for implementing the MCP8024 in a sensorless control application of a 3-phase motor. The motor is driven by energizing two windings at a time and sequencing the windings in a six step per electrical revolution method. This method leaves one winding unenergized at all times, and the voltage on that unenergized (Back EMF) winding can be monitored to determine the rotor position.

4.2.2.2 Start-Up Sequence

When the motor being driven is at rest, the back EMF is equal to zero. The motor needs to be rotating for the back EMF sensor to lock onto the rotor position and commutate the motor. The recommended start-up sequence to bring the rotor from rest up to a speed fast enough to allow back EMF sensing is comprised of three modes: Lock or Align mode, Ramp mode, and Run mode. Refer to the commutation state machine in

Table 4-1. The order in which the microcontroller steps

through the commutation state machine determines the direction the motor rotates.

4.2.2.3 Disabled Mode (CE = 0)

When the driver is disabled (CE = 0), all of the drivers are turned off.

4.2.2.4 Lock Mode

Before the motor can be started, the rotor must be in a known position. In Lock mode, the microcontroller drives phase B low and phases A and C high. This aligns the rotor 30 electrical degrees before the center of the first commutation state. Lock mode must last long enough to allow the motor and its load to settle into this position.

4.2.2.5 Ramp Mode

At the end of Lock mode, Ramp mode is entered. In Ramp mode, the microcontroller steps through the commutation state machine, increasing linearly, until a minimum speed is reached. Ramp mode is an openloop commutation. No knowledge of the rotor position is used.

DS20005228A-page 20  2013 Microchip Technology Inc.

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MCP8024

4.2.2.6 Run Mode

At the end of the Ramp mode, Run mode is entered. In Run mode, the back EMF sensor is enabled and commutation is now under the control of the phase-locked loop. Motor speed can be regulated by an outer speed control loop.

TABLE 4-1: COMMUTATION STATE MACHINE

STATE

OUTPUTS

HA HB HC LA LB LC

CE = 0 OFF OFF OFF OFF OFF OFF N/A LOCK ON OFF ON OFF ON OFF N/A 1 ON OFF OFF OFF OFF ON Phase B 2 OFF ON OFF OFF OFF ON Phase A 3 OFF ON OFF ON OFF OFF Phase C 4 OFF OFF ON ON OFF OFF Phase B 5 OFF OFF ON OFF ON OFF Phase A 6 ON OFF OFF OFF ON OFF Phase C

BEMF

SAMPLE

4.2.2.7 PWM Speed Control

The inner commutation loop is a phase-locked loop, which locks to the rotor’s position. This inner loop does not attempt to modify the position of the rotor, but modifies the commutation times to match whatever position the rotor has. The outer speed loop changes the rotor velocity and the inner commutation loop locks to the rotor’s position to commutate the phase at the correct times.

The outer speed loop pulse width modulates (PWMs) the motor drive inverter to produce the desired wave shape and voltage at the motor. The inductance of the motor then integrates this PWM pattern to produce the desired average current, thus controlling the desired torque and speed of the motor. For a trapezoidal BLDC motor drive with six-step commutation, the PWM is used to generate the average voltage to produce the desired motor current and, hence, the motor speed.

There are two basic methods to PWM the inverter switches. The first method returns the reactive energy in the motor inductance to the source by reversing the voltage on the motor winding during the current decay period. This method is referred to as fast decay or chop-chop. The second method circulates the reactive current in the motor with minimal voltage applied to the inductance. This method is referred to as slow decay or chop-coast.

The preferred control method employs a chop-chop PWM for any situations where the motor is being accelerated, either positively or negatively. For improved efficiency, chop-coast PWM is employed during steady-state conditions. The chop-chop speed loop is implemented by hysteretic control, fixed offtime control, or average Current mode control of the motor current. This makes for a very robust controller

as the motor current is always in instantaneous control. The motor speed presented to the chop-chop loop is reduced by approximately 9%. A fixed-frequency PWM that only modulates the high-side switches implements the chop-coast loop. The chop-coast loop is presented with the full motor speed, so if it is able to control the speed, the chop-chop loop will never be satisfied and will remain saturated. The chop-chop remains able to assume full control if the motor torque is exceeded, either through a load change or a change in speed that produces acceleration torque. The chopcoast loop will remain saturated, with the chop-chop loop in full control, during start-up and acceleration to full speed. The bandwidth of the chop-coast loop is set to be slower than the chop-chop loop so that any transients will be handled by the chop-chop loop and the chop-coast loop will only be active in steady-state operation.

4.2.3 EXTERNAL DRIVE FOR A 3-PHASE BRIDGE WITH NMOS/NMOS MOSFET PAIRS

Each motor phase is driven with external NMOS/ NMOS MOSFET pairs. These are controlled by a lowside and a high-side gate driver. The gate drivers are controlled directly by the digital input pins PWM[1:3]H/ L. A logic High turns the associated gate driver ON, and a logic Low turns the associated gate driver OFF. The PWM[1:3]H/L digital inputs are equipped with internal pull-down resistors.

The low-side gate drivers are biased by the +12V LDO output, referenced to ground. The high-side gate drivers are a floating drive biased by a bootstrap capacitor circuit. The bootstrap capacitor is charged by the +12V LDO whenever the accompanying low-side MOSFET is turned on.

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MCP8024

4.2.3.1 External Driver Protection Features

Each driver is equipped with Undervoltage Lock Out (UVLO) and short circuit protection features.

4.2.3.1.1 Driver Undervoltage Lock Out (UVLO)

At anytime the driver bias voltage is below the Driver

Undervoltage Lock Out threshold ( not turn ON when commanded ON. A driver fault will be indicated to the host microcontroller on the ILIMIT_OUT, open-drain output pin and also via a DE2

communications Status 1 message. This is a latched

fault. Clearing the fault requires either removal of device power or disabling and re-enabling the device via the device enable input (CE). Bit 3 of the Configuration 0 register is used to enable or disable the Driver Undervoltage Lockout feature. This protection feature prevents the external MOSFETs from being controlled with a gate voltage not suitable to fully enhance the device.

4.2.3.1.2 External MOSFET Short Circuit Current

Short circuit protection monitors the voltage across the external MOSFETs during an ON condition. If the voltage rises above a user configurable threshold, all drivers will be turned OFF. A driver fault will be indicated to the host microcontroller on the open-drain ILIMIT_OUT output pin and also via a DE2 communications Status 1 message. This is a latched fault. Clearing the fault requires either removal of device power or disabling and re-enabling the device via the device enable input (CE). This protection feature helps detect internal motor failures such as winding to case shorts.

Note: The driver short-circuit protection is

dependent on application parameters. A configuration message is provided for a set number of threshold levels. In addition, Driver UVLO and/or short-circuit protection has the option to be disabled.

The short-circuit voltage may be set via a DE2

Set_Cfg_0 message. Bits 0 and 1 are used to select the

voltage level for the short circuit comparison. If the voltage across the MOSFET drain-source exceeds the selected voltage level, a fault will be triggered. The selectable voltage levels are 250 mV, 500 mV, 750 mV, and 1000 mV. Bit 2 of the Configuration 0 register is used to enable or disable the short-circuit detection.

), the driver will

UVLO

4.2.3.2 Gate Control Logic

The gate control logic provides level shifting of the digital inputs, polarity control, and cross conduction protection. Cross conduction protection is performed in two ways.

4.2.3.2.1 Cross Conduction Protection

First, logic prevents switching ON one power MOSFET while the opposite one in the same half-bridge is already switched ON. If both MOSFETs in the same half-bridge are commanded on simultaneously by the digital inputs, both will be turned OFF.

4.2.3.2.2 Programmable Dead Time

Second, the gate control logic employs a breakbefore-make dead-time delay that is programmable. A configuration message is provided to configure the driver dead time. The allowable dead times are 250 ns, 500 ns, 1 µs and 2 µs.

4.2.3.2.3 Programmable Blanking Time

A configuration message is provided to configure the driver current limit blanking time. The blanking time allows the system to ignore any current spikes that may occur when switching outputs. The allowable blanking times are 500 ns, 1 µs, 2µs, and 4µs (default). The blanking time will start after the dead time circuitry has timed out.

4.3 CHIP ENABLE (CE)

The Chip Enable (CE) pin allows the device to be disabled by external control. When the Chip Enable pin is not active, the following subsystems are disabled:

• high side gate drives (HA, HB, HC)

• low side gate drives (LA, LB, LC)

• 12V LDO

• 30K pull-up resistor connected to the level translator is switched out of the circuit to minimize current consumption (configurable).

The 5V LDO and Buck Regulator stay enabled. The DE2 communications port remains active but the port may only respond to commands. When CE is inactive, the DE2 port is prevented from initiating communications in order to conserve power.

The total current consumption of the device when CE is inactive (device disabled) stays within the “input quiescent current” limits specified in the device characteristics table.

4.4 COMMUNICATION PORTS

The communication ports provide a means of communicating to the host system.

4.4.1 DE2 COMMUNICATIONS PORT

A half-duplex 9600 baud UART interface is available to communicate with an external host. The port is used to configure the MCP8024 and also for status and fault messages.

DS20005228A-page 22  2013 Microchip Technology Inc.

Page 23

MCP8024

4.4.2 LEVEL TRANSLATOR

The level translator is an interface between the companion microcontrollers logic levels and the input voltage levels from the system. Typically, the input is driven from the Engine Control Unit (ECU). The level translator is a unidirectional translator. Signals on the high-voltage input are translated to low-voltage signals on the low-voltage outputs. The high-voltage HV_INx inputs have a configurable 30K pullup. The pullup is configured via a SET_CFG_0 message. Bit 6 of the register controls the state of the pullup. The bit may only be changed when the CE pin is active. The lowvoltage LV_OUTx outputs are open-drain outputs.

Note: The TQFP package has two level translators.

The second level translator typically interfaces to an Ignition Key ON/OFF signal.

4.5 HOST COMMUNICATIONS

4.5.1 DE2 COMMUNICATIONS

A single-wire, half-duplex, 9600 baud, 8-bit bidirectional communications interface is implemented using the open-drain DE2 pin. The interface consists of eight data bits, one Stop bit, and one Start bit. The implementation of the interface is described in the following sections. A 2K resistor should typically be used between the host transmit pin and the MCP8024 DE2 pin to allow the MCP8024 to drive the DE2 line when the host TX pin is at an idle high level.

The DE2 communications is active when CE = 0 with the constraint that the MCP8024 will not initiate any messages. The host processor may initiate messages regardless of the state of the CE pin. The MCP8024 will respond to host commands when the CE pin is low.

4.5.3 PACKET TIMING

While no data is being transmitted, a logic ‘1’ must be placed on the open-drain DE2 line by an external pullup resistor. A data packet is composed of one Start bit, which is always a logic ‘0’, followed by eight data bits, and a Stop bit. The Stop bit must always be a logic ‘1’. It takes 10 bits to transmit a byte of data.

The device detects the Start bit by detecting the transition from logic 1 to logic 0 (note that while the data line is idle, the logic level is high). Once the Start bit is detected, the next data bit’s “center” can be assured to be 24 ticks minus 2 (worst case synchronizer uncertainty) later. From then on, every next data bit center is

16 clock ticks later. Figure 4-3 illustrates this point.

4.5.2 PACKET FORMAT

Every internal status change will provide a communication to the microcontroller. The interface uses a standard UART baud rate of 9600 bits per second.

In the DE2 protocol, the transmitter and the receiver do not share a clock signal. A clock signal does not emanate from one transmitter to the other receiver. Due to this reason the protocol is asynchronous. The protocol uses only one line to communicate, so the transmit/ receive packet must be done in Half-Duplex mode. A new transmit message is allowed only when a complete packet has been transmitted.

The Host must listen to the DE2 line in order to check for contentions. In case of contention, the host must release the line and wait for at least three packet-length times before initiating a new transfer.

Figure 4-2 illustrates a basic DE2 data packet.

 2013 Microchip Technology Inc. DS20005228A-page 23

Page 24

MCP8024

STOP

STARTDE2

Message Format

STOP

START

= 1.5T – uncertainty on start

Detection (worse case: 2x T

)

= T/16 (oversampled bit-cell period)

Receiver samples the incoming data

using x16 baud rate clock

Sample incoming data at the bit-cell center

START

T = 1/Baud Rate (bit-cell period)

Detect start bit by sensing transition from logic 1 to logic 0

(worst

FIGURE 4-2: DE2 PACKET FORMAT.

FIGURE 4-3: DE2 PACKET TIMING.

4.5.4 MESSAGING INTERFACE

A command byte will always have the most significant bit 7 (msb) set to ‘1’. Bits 6 and 5 are reserved for future use and should be set to ‘0’. Bits 4:0 are used for commands. That allows for 32 possible commands.

4.5.4.1 Host to MCP8024

Messages sent from the host to the MCP8024 device consist of either one or two eight-bit bytes. The first byte transmitted is the command byte. The second byte transmitted, if required, is the data for the command.

4.5.4.2 MCP8024 to Host

A solicited response byte from the MCP8024 device will always echo the command byte with bit 7 set to ‘0’ (Response) and with bit 6 set to ‘1’ for Acknowledged (ACK) or ‘0’ for Not Acknowledged (NACK). The second byte, if required, will be the data for the host command. Any command that causes an error or is not supported will receive a NACK response.

The MCP8024 may send unsolicited command messages to the host controller. All messages to the host controller do not require a response from the host controller.

4.5.4.3 Messages

4.5.4.3.1 SET_CFG_0

There is a SET_CFG_0 message that is sent by the host to the MCP8024 device to configure the device. The SET_CFG_0 message may be sent to the device at any time. The host is responsible for making sure the system is in a state that will not be compromised by sending the SET_CFG_0 message. The SET_CF- G_0 message format is indicated in Tab le 4 -2. The response is indicated in Tab l e 4 -3 .

4.5.4.3.2 GET_CFG_0

There is a GET_CFG_0 message that is sent by the host to the MCP8024 device to retrieve the device configuration register. The GET_CFG_0 message format is indicated in Ta bl e 4 - 2 . The response is indicated in Table 4-3.

4.5.4.3.3 STATUS_0/1

There is a STATUS_0/1 message that is sent by the host to the MCP8024 device to retrieve the device STATUS register. The STATUS_0/1 message may also be sent to the host by the MCP8024 device to inform the host of status changes. The STATUS_0/1 message format is indicated in Table 4-2. The response is indicated in Tab l e 4 -3 .

DS20005228A-page 24  2013 Microchip Technology Inc.

Page 25

The Brown-out Reset – Config Lost bit 4 of status message 1 will be set every time the device restarts due to a brown-out event or a normal start-up. When the bit is set, an unsolicited message will be sent to the host indicating a Reset has taken place and that the configuration data may have been lost. The flag is reset by a “Status 1 Ack” (01000110 (46H)) from the device in response to a Host Status Request command.

4.5.4.3.4 SET_CFG_1 There is a SET_CFG_1 message that is sent by the

host to the MCP8024 device to configure the motor current limit reference DAC. The SET_CFG_1 message may be sent to the device at any time. The host is responsible for making sure the system is in a state that will not be compromised by sending the SET_CF- G_1 message. The SET_CFG_1 message format is indicated in Tab le 4 -2. The response is indicated in

Table 4-3.

4.5.4.3.5 GET_CFG_1 There is a GET_CFG_1 message that is sent by the

host to the MCP8024 device to retrieve the motor current limit reference DAC Configuration register. The GET_CFG_1 message format is indicated in Table 4-2. The response is indicated in Tab le 4 -3 .

MCP8024

4.5.4.3.6 SET_CFG_2 There is a SET_CFG_2 message that is sent by the

host to the MCP8024 device to configure the driver current limit blanking time. The SET_CFG_2 message may be sent to the device at any time. The host is responsible for making sure the system is in a state that will not be compromised by sending the SET_CF- G_2 message. The SET_CFG_2 message format is indicated in Tab le 4 -2. The response is indicated in

Table 4-3.

4.5.4.3.7 GET_CFG_2 There is a GET_CFG_2 message that is sent by the

host to the MCP8024 device to retrieve the device Configuration register #2. The GET_CFG_2 message format is indicated in Tab l e 4 -2. The response is indicated in Table 4-3.

 2013 Microchip Technology Inc. DS20005228A-page 25

Page 26

MCP8024

TABLE 4-2: DE2 COMMUNICATIONS COMMANDS TO MCP8024 FROM HOST

COMMAND BYTE BIT VALUE DESCRIPTION

SET_CFG_0 1 10000001 (81H) Set Configuration Register 0

270 Unused (Start-up Default)

6 0

5 0 Unused 4 0 Reserved 3 0

2 0

1:0 00

01 10 11

GET_CFG_0 1 10000010 (82H) Get Configuration Register 0 STATUS_0 1 10000101 (85H) Get Status Register 0 STATUS_1 1 10000110 (86H) Get Status Register 1 SET_CFG_1 1 10000011 (83H) Set Configuration Register 1

2 7:0 00H - FFH Select DAC Current Reference value.

GET_CFG_1 1 10000100 (84H) Get Configuration register 1

SET_CFG_2 1 10000111 (87H) Set Configuration register 2

Disable Disconnect of 30K Level Translator Pullup when CE = 0 (Default) Enable Disconnect of 30K Level Translator Pullup when CE = 0

Enable Undervoltage Lockout (Start-up Default) Disable Undervoltage Lockout

Enable External MOSFET Short Circuit Detection (Start-up Default) Disable External MOSFET Short Circuit Detection

Set External MOSFET Overcurrent Limit to 0.250V (Start-up Default) Set External MOSFET Overcurrent Limit to 0.500V Set External MOSFET Overcurrent Limit to 0.750V Set External MOSFET Overcurrent Limit to 1.000V

DAC Motor Current Limit Reference Voltage

(4.503V - 0.991V)/ 255 = 13.77 mV / bit 00H = 0.991 Volts 40H = 1.872 Volts (40H * 0.1377mV/Bit + 0.991V) (Start-up Default) FFH = 4.503 Volts (FFH * 0.1377mV/Bit + 0.991V)

Get DAC Motor Current Limit reference voltage

2 7:4 00H Unused (Start-up Default)

3:2 ---

00 01 10 11

1:0 ---

00 01 10 11

GET_CFG_2 1 10001000 (88H) Get Configuration Register 2

DS20005228A-page 26  2013 Microchip Technology Inc.

Driver Dead Time (For PWMH /PWML inputs) 2 µs (Default) 1 µs 500 ns 250 ns

Driver Blanking Time (Ignore Switching Current Spikes) 4 µs (Start-up Default) 2 µs 1 µs 500 ns

Page 27

TABLE 4-3: DE2 COMMUNICATIONS MESSAGES FROM MCP8024 TO HOST

MESSAGE BYTE BIT VALUE DESCRIPTION

STATUS_0 17:000000101 (05H)

01000101 (45H) 10000101 (85H)

27:000000000 Normal Operation

00000001 Temperature Warning (TJ > 125°C (Default Warning Level)) 00000010 Over Temperature (TJ > 160°C) 00000100 Input Undervoltage (VDD < 5.5V) 00001000 Reserved 00010000 Input Overvoltage (V 00100000 Buck Regulator Overcurrent 01000000 Buck Regulator Output Undervoltage Warning 10000000 Buck Regulator Output Undervoltage (< 80%,brown-out error)

STATUS_1 17:000000110 (06H)

01000110 (46H) 10000110 (86H)

27:000000000 Normal Operation

00000001 5V LDO Overcurrent 00000010 12V LDO Overcurrent 00000100 External MOSFET Undervoltage Lock Out (UVLO) 00001000 External MOSFET Overcurrent Detection 00010000 Brown-out Reset – Config Lost (Start-up default = 1) 00100000 Not Used 01000000 Not Used 10000000 Not Used

SET_CFG_0 17:000000001 (01H)

01000001 (41H)

270 Unused (Start-up Default)

6 0

5 0 Unused 4 0 Reserved 3 0

2 0

1:0 00

01 10 11

GET_CFG_0 17:000000010 (02H)

01000010 (42H)

270 Unused (Start-up Default)

6 0

5 0 Unused 4 0 Reserved

Status Register 0 Response Not Acknowledged (Response) Status Register 0 Response Acknowledged (Response) Status Register 0 Command To Host (Unsolicited)

> 32V)

STATUS Register 1 Response Not Acknowledged (Response) STATUS Register 1 Response Acknowledged (Response) STATUS Register 1 Command To Host (Unsolicited)

Set Configuration Register 0 Not Acknowledged (Response) Set Configuration Register 0 Acknowledged (Response)

Disable Disconnection of 30K Level Translator Pullup when CE = 0 (Default) Enable Disconnection of 30K Level Translator Pullup when CE = 0

Undervoltage Lockout Enabled (Default) Undervoltage Lockout Disabled

External MOSFET Overcurrent Detection Enabled (Default) External MOSFET Overcurrent Detection Disabled

0.250V External MOSFET Overcurrent Limit (Default)

0.500V External MOSFET Overcurrent Limit

0.750V External MOSFET Overcurrent Limit

1.000V External MOSFET Overcurrent Limit Get Configuration Register 0 Response Not Acknowledged

(Response) Get Configuration Register 0 Response Acknowledged (Response)

Disable Disconnection of 30K Level Translator Pullup when CE = 0 (Default) Enable Disconnection of 30K Level Translator Pullup when CE = 0

MCP8024

 2013 Microchip Technology Inc. DS20005228A-page 27

Page 28

MCP8024

TABLE 4-3: DE2 COMMUNICATIONS MESSAGES FROM MCP8024 TO HOST (CONTINUED)

MESSAGE BYTE BIT VALUE DESCRIPTION

3 0

2 0

1:0 00

01 10 11

SET_CFG_1 1 00000011 (03H)

01000011 (43H)

2 7:0 00H - FFH Current DAC Current Reference value 13.77 mV / bit + 0.991V

GET_CFG_1 1 00000100 (04H)

01000100 (44H)

2 7:0 00H - FFH Current DAC Current Reference value 13.77 mV / bit + 0.991V

SET_CFG_2 1 00000111 (07H)

01000111 (47H)

2 7:4 00H Unused (Default)

3:2 ---

00 01 10 11

1:0 ---

00 01 10 11

GET_CFG_2 1 00001000 (08H)

01001000 (48H)

2 7:4 00H Unused (Default)

3:2 ---

00 01 10 11

1:0 ---

00 01 10 11

Undervoltage Lockout Enabled (Default) Undervoltage Lockout Disabled

External MOSFET Overcurrent Detection Enabled (Default) External MOSFET Overcurrent Detection Disabled

0.250V External MOSFET Overcurrent Limit (Default)

0.500V External MOSFET Overcurrent Limit

0.750V External MOSFET Overcurrent Limit

1.000V External MOSFET Overcurrent Limit

Set DAC Motor Current Limit Reference Voltage Not Acknowledged (Response) Set DAC Motor Current Limit Reference Voltage Acknowledged (Response)

Get DAC Motor Current Limit Reference Voltage Not Acknowledged (Response) Get DAC Motor Current Limit Reference Voltage Acknowledged (Response)

Set Configuration Register 2 Not Acknowledged (Response) Set Configuration Register 2 Acknowledged (Response)

Driver Dead Time (For PWMH /PWML inputs) 2 µs (Default) 1 µs 500 ns 250 ns

Driver Blanking Time (Ignore Switching Current Spikes) 4 µs (Default) 2 µs 1 µs 500 ns

Get Configuration Register 2 Response Not Acknowledged (Response) Get Configuration Register 2 Response Acknowledged (Response)

Driver Dead Time (For PWMH /PWML inputs) 2 µs (Default) 1 µs 500 ns 250 ns

Driver Blanking Time (Ignore Switching Current Spikes) 4 µs (Default) 2 µs 1 µs 500 ns

DS20005228A-page 28  2013 Microchip Technology Inc.

Page 29

MCP8024

Transfer

Charge

5.0 APPLICATION INFORMATION

5.1 Component Calculations

5.1.1 CHARGE PUMP CAPACITORS

FIGURE 5-1: Charge Pump.

Let:

• Iout = 20 mA

• Fcp = 75 kHz (charge/discharge in one cycle)

• 50% duty cycle

•VDD = 6V (worst case)

• RDSON = 7.5  (R

•Vout = 2 x V

•C

= 20 m (ceramic capacitors)

ESR

(ideal)

• Vdrop = 100 mV (Vout ripple)

•Tchg= Tdchg = 0.5 * 1/75 kHz = 6.67 µs

5.1.1.1 Flying Capacitor

The flying capacitor should be chosen to charge to a minimum of 95% (3 ) of V switching cycle.

3 * = Tchg  = Tchg/3

RC = Tchg/3

C = Tchg/(R * 3) C = 6.67 µs/([7.5 + 3.5 + 0.02] * 3)

C = 202 nF

Choose a 180 nF capacitor.

5.1.1.2 Charge Pump Output Capacitor

Solve for the charge pump output capacitance, connected between V12P and ground, that will supply the 20 mA load for one switch cycle. The 12VLDO pin on the MCP8024 is the "V12P" pin referenced in the calculations.

C = Iout * dt/dV

C = Iout * 13.3 µs/(Vdrop + Iout * C C = 20 mA * 13.3 µs/(0.1V + 20 mA * 20 m)

C >= 2.65 µF

PMOS

), 3.5  (R

NMOS

within one half of a

)

ESR

)

5.1.1.3 Charging Path (Flying Capacitor across CAP1 and CAP2)

= VDD (1 - e

CAP

= 6V (1 - e

CAP

= 5.79V available for transfer

CAP

-T/t

)

-[6.67 µs / ([7.5 + 3.5 + 20 m] * 180 nF)]

5.1.1.4 Transfer Path (Flying and Output Capacitors)

= VDD + V

12P

= 6V + 5.79V - (20 mA * 6.67 µs / 180 nF)

12P

= 11.049V

12P

CAP

- I

OUT

* dt / C

5.1.1.5 Calculate the Flying Capacitor Voltage Drop in One Cycle While Supplying 20 mA

dv = Iout * dt / C dv = 20 mA * 6.67 µs / 180 nF dv = 0.741V @ 20 mA

The second and subsequent transfer cycles will have a higher voltage available for transfer since the capacitor is not completely depleted with each cycle. V then be V

- dV) times the RC constant. This repeats for

CAP

- dV after the first transfer, plus VDD -

CAP

will

each subsequent cycle, allowing a larger charge pump capacitor to be used if the system will tolerate several charge transfers before requiring full-output voltage and current.

Repeating section 5.1.1.3 for the second cycle (and subsequent by re-calculating for each new value of

after each transfer):

CAP

= (V

CAP

= (5.79V - 0.741V) + (6V - (5.79V - 0.741V) *

CAP

-[6.67 μs/([7.5Ω + 3.5Ω + 20 mΩ] * 180 nF)]

(1 - e

= 5.049V + 0.951V * 0.96535

CAP

= 5.967V available for transfer on second cycle

CAP

- dV) + (V

CAP

- (V

- dV)) (1 - e

CAP

-T/t

)

5.1.1.6 Charge Pump Results

The maximum charge pump flying capacitor value is 202 nF to maintain a 95% voltage transfer ratio on the first charge pump cycle. Larger capacitor values may be used but they will require more cycles to charge to maximum voltage. The minimum required output capacitor value is 2.65 µF to supply 20 mA for 13.3 µs with a 100 mV drop. A larger output capacitor may be used to cover losses due to capacitor tolerance over temperature, capacitor dielectric and PCB losses.

These are approximate calculations. The actual voltages may vary due to incomplete charging or discharging of capacitors per cycle due to load changes. The charge pump calculations assume the charge pump is able to charge up the external boot cap within a few cycles.

)

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Page 30

MCP8024

OUTPUT

CONTROL

LOGIC

VDD

CURRENT_REF

VDD-12V

BANDGAP

REFERENCE

D1 Sc hottky

5.1.2 BOOTSTRAP CAPACITOR

The high-side driver bootstrap capacitor needs to power the high-side driver and gate for 1/3 of the motor electrical period for a 3-phase BLDC motor.

Let:

• MOSFET driver current: 300 mA

• PWM period: 50 µs (20 kHz) to 50 ms (20Hz)

• Minimum duty cycle: 1% (500 ns to 500 µs)

• Maximum duty cycle: 99% (49.5 µs to 49.5 ms) = 12V

•V

• Minimum gate drive voltage: 8V (VGS)

• Total gate charge: 130 nC (80A MOSFET)

•Allowable V

• Switch RDSON: 100 m

• Driver bias current: 20 µA (I

• Switching transition time (tSW): 40 ns

Solve for the smallest capacitance that can supply:

- 130 nC of charge to the MOSFET gate

- 1 Megohm Gate-Source resistor current

- Driver bias current and switching losses

MOSFET

RESISTOR

= (I

DRIVER

= 49.5 ms (99% DC) for worst case.

RESISTOR

= 20 µA * 49.5 ms + 300 mA * 40 ns

DRIVER

= 1.002 µC

DRIVER

Sum all of the energy requirements:

C = (Q

MOSFET

C = (130 nC + 594 nC + 1.002 µC) / 3V

C = 575 nF

Choose a bootstrap capacitor value that is larger than 575 nF.

drop (V

): 3V (12V - 3V = 9V)

DROP

)

BIAS

= 130 nC

= [(VGS/R) * TON]

BIAS

* TON + I

DRIVER

* tSW)

= (12V/1 Megohm) * 49.5 ms

= 594 nC

+ Q

RESISTOR

+ Q

DRIVER

)/V

DROP

 7.05 µH

MAX

Choose an inductor  7.05 µH to ensure Discontinuous Conduction mode.

Table 5-1 shows the various maximum inductance val-

ues for a worst case input voltage of 6V and various output voltages.

5.1.3.2 Determine the Peak Switch Current for the Calculated Inductor

Ipeak = (Vs - Vo) * D * T/L

Ipeak = (6V - 3.3V) * (3.3V/6.0V) * 2.137 µs / 7.05 µH

Ipeak = 450 mA

5.1.3.3 Setting the Buck Output Voltage

The buck output voltage is set by a resistor voltage divider from the inductor output to ground. The divider center tap is fed back to the MCP8024 FB pin. The FB pin is compared to an internal 1.25V reference voltage. When the FB pin voltage drops below the reference voltage, the Buck duty cycle increases. When the FB pin rises above the reference voltage, the Buck duty cycle decreases.

5.1.3 BUCK SWITCHER

FIGURE 5-2: Typical Buck Application.

Start with an R2 value of 10K to 51K to minimize current

5.1.3.1 Calculate the Buck Inductor for

through the divider.

Discontinuous Mode Operation

= 1.25V * (R1 + R2) / R2

Let:

Vin = 6V (worse case)

Vout = 3.3V

Iout = 225 mA

Switching Frequency (F

 Vout * (1 - Vout / Vin) * TSW / (2 * Iout)

MAX

 3.3V * (1 - 3.3V/6.0V) * 2.137 µs / (2 * 225 mA)

MAX

DS20005228A-page 30  2013 Microchip Technology Inc.

): 468 kHz (TSW = 2.137 µs)

BUCK

Page 31

MCP8024

TABLE 5-1: MAX INDUCTANCE FOR BUCK DISCONTINUOUS MODE OPERATION

Vin

(worst case)

6 3V 250 mA 7.12 µH

6 3.3V 225 mA 7.05 µH

6 5.0V 150 mA 5.94 µH

5.2 Device Overvoltage Protection

When a motor shaft is rotating and power is removed, the magnetism of the motor components will cause the motor to act like a generator. The current that was flowing into the motor will now flow out of the motor. As the motor magnetic field decays, the generator output will also decay. The voltage across the generator terminals will be proportional to the generator current and circuit impedance of the generator circuit. If the power supply is part of the return path for the current and the power supply is disconnected, then the voltage at the generator terminals will increase until the current flows. This voltage increase must be handled external to the driver. A voltage suppression device must be used to clamp the motor terminal voltage to a level that will not exceed the maximum motor operating voltage. A voltage suppressor should be connected from ground to each motor terminal. The PCB traces must be capable of carrying the motor current with minimum voltage and temperature rise.

An additional method is to inactivate the high-side drivers and to activate the low-side drivers. This allows current to flow through the low-side external MOSFETs and prevent the voltage increases at the power supply terminals.

Vout Iout Max. Inductance

 2013 Microchip Technology Inc. DS20005228A-page 31

Page 32

MCP8024

6.0 ERRATA

6.1 5V and 12V Regulator Overcurrent Messages

The MCP8024 may send an 0x86 0x01, 0x86 0x02 or 0x86 0x03 message when accelerating a high-current motor. The messages are overcurrent warnings for the 5V and 12V regulators. The warnings have no effect on the actual regulator operation, they are only indicators of the status of the regulator. The overcurrent warnings are due to the large initial current caused by the acceleration rates of high current motors. The messages may be ignored.

DS20005228A-page 32  2013 Microchip Technology Inc.

Page 33

7.0 PACKAGING INFORMATION

Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn)

* This package is Pb-free. The Pb-free JEDEC designator ( )

can be found on the outer packaging for this package.

Note: In the event the full Microchip part number cannot be marked on one line, it will

be carried over to the next line, thus limiting the number of available characters for customer-specific information.

40-Lead QFN (5x5x0.85 mm) Example

PIN 1 PIN 1

MCP8024

H/MP ^^

YYWWNNN

48-Lead TQFP (7x7) Example

XXXXXXXXXX

YYWWNNN

XXXXXXXXXX

MCP8024

H/PT YYWW

NNN

7.1 Package Marking Information

MCP8024

 2013 Microchip Technology Inc. DS20005228A-page 33

Page 34

MCP8024

0.20 C

(DATUM B)

(DATUM A)

SEATING

PLANE

1 2

TOP VIEW

SIDE VIEW

For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging

Note:

NOTE 1

0.10 C A B

0.08

Microchip Technology Drawing C04-047-002A Sheet 1 of 2

40-Lead Plastic Quad Flat, No Lead Package (MP) - 5x5 mm Body [QFN]

40X b

0.07 C A B

0.05 C

(A3)

With 3.7x3.7 mm Exposed Pad

0.10 C

DS20005228A-page 34  2013 Microchip Technology Inc.

Page 35

Microchip Technology Drawing C04-047-002A Sheet 2 of 2

For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging

Note:

Number of Terminals

Overall Height

Terminal Width

Overall Width

Overall Length

Terminal Length

Exposed Pad Width

Exposed Pad Length

Terminal Thickness

Pitch

Standoff

Units

Dimension Limits

0.40 BSC

0.20 REF

0.30

0.15

0.80

0.00

0.20

5.00 BSC

0.40

3.70 BSC

0.85

0.02

5.00 BSC

MILLIMETERS

MIN

NOM

0.50

0.25

0.90

0.05

MAX

K-0.20 -

REF: Reference Dimension, usually without tolerance, for information purposes only.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

Notes:

Pin 1 visual index feature may vary, but must be located within the hatched area. Package is saw singulated

Dimensioning and tolerancing per ASME Y14.5M

Terminal-to-Exposed-Pad

40-Lead Plastic Quad Flat, No Lead Package (MP) - 5x5 mm Body [QFN] With 3.7x3.7 mm Exposed Pad

MCP8024

 2013 Microchip Technology Inc. DS20005228A-page 35

Page 36

MCP8024

RECOMMENDED LAND PATTERN

For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging

Note:

SILK SCREEN

Dimension Limits

Units

Optional Center Pad Width

Contact Pad Spacing

Optional Center Pad Length

Contact Pitch

3.80

MILLIMETERS

0.40 BSC

MIN

MAX

5.00

Contact Pad Length (X40)

Contact Pad Width (X40)

0.80

0.20

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

Notes:

1. Dimensioning and tolerancing per ASME Y14.5M

Microchip Technology Drawing C04-2047-002A

NOM

40-Lead Plastic Quad Flat, No Lead Package (MP) - 5x5 mm Body [QFN] With 3.7x3.7 mm Exposed Pad

C2Contact Pad Spacing 5.00

DS20005228A-page 36  2013 Microchip Technology Inc.

Page 37

SEATING

PLANE

For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging

Note:

NOTE 1

Microchip Technology Drawing C04-183A Sheet 1 of 2

48-Lead Thin Quad Flatpack (PT) - 7x7x1.0 mm Body [TQFP] With Exposed Pad

TOP VIEW

EE1

0.20

H A-B D

D1/2

0.10

0.08

SIDE VIEW

0.20 C A-B D

48X TIPS

0.20

H A-B D

0.20

E1/4

D1/4

TOP VIEW

E1/2

e 48x b

0.08 C A-B D

e/2

MCP8024

 2013 Microchip Technology Inc. DS20005228A-page 37

Page 38

MCP8024

Microchip Technology Drawing C04-183A Sheet 2 of 2

For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging

Note:

48-Lead Thin Quad Flatpack (PT) - 7x7x1.0 mm Body [TQFP] With Exposed Pad

(L1)

SECTION A-A

4. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only.

protrusions shall not exceed 0.25mm per side.

Mold Draft Angle Bottom

Molded Package Thickness

Dimension Limits

Mold Draft Angle Top

Notes:

Foot Length

Lead Width

Lead Thickness

Molded Package Length

Molded Package Width

Overall Length

Overall Width

Foot Angle

Footprint

Standoff

Overall Height

Lead Pitch

Number of Leads

12°

11° 13°

0.750.600.45L

12°

0.22

7.00 BSC

9.00 BSC

3.5°

1.00 REF

0.09

0.17 11°

0°

13°

0.27

0.16-

7°

1.00

0.50 BSC

NOM

MILLIMETERS

A1 A2

0.05

0.95

Units

MIN

1.05

0.15

1.20

MAX

Chamfers at corners are optional; size may vary.

Pin 1 visual index feature may vary, but must be located within the hatched area.

Dimensioning and tolerancing per ASME Y14.5M

Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or

Exposed Pad Length

Exposed Pad Width

E2 3.50 BSC

3.50 BSC

DS20005228A-page 38  2013 Microchip Technology Inc.

Page 39

RECOMMENDED LAND PATTERN

For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging

Note:

Dimension Limits

Units

Optional Center Tab Width

Contact Pad Spacing Contact Pad Spacing

Optional Center Tab Length

Contact Pitch

3.50

MILLIMETERS

0.50 BSC

MIN

MAX

8.40

Contact Pad Length (X48)

Contact Pad Width (X48)

1.50

0.30

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

Notes:

1. Dimensioning and tolerancing per ASME Y14.5M

Microchip Technology Drawing No. C04-2183A

NOM

48-Lead Thin Quad Flatpack (PT) - 7x7x1.0 mm Body [TQFP] With Thermal Tab

MCP8024

 2013 Microchip Technology Inc. DS20005228A-page 39

Page 40

MCP8024

NOTES:

DS20005228A-page 40  2013 Microchip Technology Inc.

Page 41

APPENDIX A: REVISION HISTORY

Revision A (September 2013)

• Original Release of this Document.

MCP8024

 2013 Microchip Technology Inc. DS20005228A-page 41

Page 42

MCP8024

NOTES:

DS20005228A-page 42  2013 Microchip Technology Inc.

Page 43

PRODUCT IDENTIFICATION SYSTEM

PART NO. -X /XX

PackageTemperature

Range

Device

Device: MCP8024: 3-Phase Brushless DC (BLDC) Motor Gate

Driver with Power Module

MCP8024T:3-Phase Brushless DC (BLDC) Motor Gate

Driver with Power Module (Tape and Reel)

Temperature Range:

H = -40°C to +150°C (High)

Package: MP = Plastic Quad Flat, No Lead Package with Exposed

Pad - 5x5 mm body, 40-lead

PT = Plastic Thin Quad Flatpack with Exposed Pad -

7x7 mm body, 48-lead, Thermally Enhanced (EP)

Examples:

a) MCP8024-H/MP: High Temperature,

40LD 5x5 QFN package

b) MCP8024T-H/PT: Tape and Reel,

High Temperature, 48LD TQFP-EP package

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

MCP8024

 2013 Microchip Technology Inc. DS20005228A-page 43

Page 44

MCP8024

NOTES:

DS20005228A-page 44  2013 Microchip Technology Inc.

Page 45

Note the following details of the code protection feature on Microchip devices:

YSTEM

CERTIFIED BY DNV

== ISO/TS 16949 ==

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, dsPIC, FlashFlex, K PICSTART, PIC and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MTP, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A.

Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries.

Analog-for-the-Digital Age, Application Maestro, BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O, Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA and Z-Scale are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.

GestIC and ULPP are registered trademarks of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries.

All other trademarks mentioned herein are property of their respective companies.

Printed on recycled paper.

ISBN: 978-1-62077-502-8

EELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,

logo, rfPIC, SST, SST Logo, SuperFlash

QUALITY MANAGEMENT S

 2013 Microchip Technology Inc. DS20005228A-page 45

Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.

MCUs and dsPIC® DSCs, KEELOQ

code hopping

Page 46

Worldwide Sales and Service

AMERICAS

Corporate Office

2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support:

http://www.microchip.com/ support

Web Address:

www.microchip.com

Atlanta

Duluth, GA Tel: 678-957-9614 Fax: 678-957-1455

Boston

Westborough, MA Tel: 774-760-0087 Fax: 774-760-0088

Chicago

Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075

Cleveland

Independence, OH Tel: 216-447-0464 Fax: 216-447-0643

Dallas

Addison, TX Tel: 972-818-7423 Fax: 972-818-2924

Detroit

Farmington Hills, MI Tel: 248-538-2250 Fax: 248-538-2260

Indianapolis

Noblesville, IN Tel: 317-773-8323 Fax: 317-773-5453

Los Angeles

Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608

Santa Clara

Santa Clara, CA Tel: 408-961-6444 Fax: 408-961-6445

Toronto

Mississauga, Ontario, Canada Tel: 905-673-0699 Fax: 905-673-6509

ASIA/PACIFIC

Asia Pacific Office

Suites 3707-14, 37th Floor Tower 6, The Gateway Harbour City, Kowloon Hong Kong Tel: 852-2401-1200 Fax: 852-2401-3431

Australia - Sydney

Tel: 61-2-9868-6733 Fax: 61-2-9868-6755

China - Beijing

Tel: 86-10-8569-7000 Fax: 86-10-8528-2104

China - Chengdu

Tel: 86-28-8665-5511 Fax: 86-28-8665-7889

China - Chongqing

Tel: 86-23-8980-9588 Fax: 86-23-8980-9500

China - Hangzhou

Tel: 86-571-2819-3187 Fax: 86-571-2819-3189

China - Hong Kong SAR

Tel: 852-2943-5100 Fax: 852-2401-3431

China - Nanjing

Tel: 86-25-8473-2460 Fax: 86-25-8473-2470

China - Qingdao

Tel: 86-532-8502-7355 Fax: 86-532-8502-7205

China - Shanghai

Tel: 86-21-5407-5533 Fax: 86-21-5407-5066

China - Shenyang

Tel: 86-24-2334-2829 Fax: 86-24-2334-2393

China - Shenzhen

Tel: 86-755-8864-2200 Fax: 86-755-8203-1760

China - Wuhan

Tel: 86-27-5980-5300 Fax: 86-27-5980-5118

China - Xian

Tel: 86-29-8833-7252 Fax: 86-29-8833-7256

China - Xiamen

Tel: 86-592-2388138 Fax: 86-592-2388130

China - Zhuhai

Tel: 86-756-3210040 Fax: 86-756-3210049

ASIA/PACIFIC

India - Bangalore

Tel: 91-80-3090-4444 Fax: 91-80-3090-4123

India - New Delhi

Tel: 91-11-4160-8631 Fax: 91-11-4160-8632

India - Pune

Tel: 91-20-3019-1500

Japan - Osaka

Tel: 81-6-6152-7160 Fax: 81-6-6152-9310

Japan - Tokyo

Tel: 81-3-6880- 3770 Fax: 81-3-6880-3771

Korea - Daegu

Tel: 82-53-744-4301 Fax: 82-53-744-4302

Korea - Seoul

Tel: 82-2-554-7200 Fax: 82-2-558-5932 or 82-2-558-5934

Malaysia - Kuala Lumpur

Tel: 60-3-6201-9857 Fax: 60-3-6201-9859

Malaysia - Penang

Tel: 60-4-227-8870 Fax: 60-4-227-4068

Philippines - Manila

Tel: 63-2-634-9065 Fax: 63-2-634-9069

Singapore

Tel: 65-6334-8870 Fax: 65-6334-8850

Tai wan - Hsin Chu

Tel: 886-3-5778-366 Fax: 886-3-5770-955

Taiwan - Kaohsiung

Tel: 886-7-213-7828 Fax: 886-7-330-9305

Taiwan - Taipei

Tel: 886-2-2508-8600 Fax: 886-2-2508-0102

Thailand - Bangkok

Tel: 66-2-694-1351 Fax: 66-2-694-1350

EUROPE

Austria - Wels

Tel: 43-7242-2244-39 Fax: 43-7242-2244-393

Denmark - Copenhagen

Tel: 45-4450-2828 Fax: 45-4485-2829

France - Paris

Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79

Germany - Munich

Tel: 49-89-627-144-0 Fax: 49-89-627-144-44

Italy - Milan

Tel: 39-0331-742611 Fax: 39-0331-466781

Netherlands - Drunen

Tel: 31-416-690399 Fax: 31-416-690340

Spain - Madrid

Tel: 34-91-708-08-90 Fax: 34-91-708-08-91

UK - Wokingham

Tel: 44-118-921-5869 Fax: 44-118-921-5820

08/20/13

DS20005228A-page 46  2013 Microchip Technology Inc.

Datasheet MCP8024 Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

Package Types

Functional Block Diagram

Typical Application Circuit

AC/DC CHARACTERISTICS

TEMPERATURE SPECIFICATIONS

ESD, SUSCEPTIBILITY, SURGE, AND LATCH-UP TESTING

2.0 TYPICAL PERFORMANCE CURVES

FIGURE 2-1: LDO Line Regulation vs Temperature.

FIGURE 2-4: 12 V LDO Power Supply Ripple Rejection vs Frequency.

FIGURE 2-2: LDO Load Regulation vs Temperature.

FIGURE 2-3: 5V LDO Power Supply Ripple Rejection vs Frequency.

FIGURE 2-16: Trapezoidal Back EMF.

FIGURE 2-14: 12V LDO Output Voltage vs Rising Input Voltage.

FIGURE 2-15: Quiescent Current vs Temperature.

FIGURE 2-17: PWM Deadtime.

FIGURE 2-18: Buck Snubber Turn On.

FIGURE 2-19: Buck Snubber Turn Off.

3.0 PIN DESCRIPT IONS

3.1 Functional Pin Descriptions

3.3 PGND, Exposed Pad (EP)

3.4 +12V

3.5 +5V

3.6 LX

3.7 FB

3.8 CAP1, CAP2

3.9 CE

3.10 I_OUT1, I_OUT2, I_OUT3

3.1 1 ISENSE1, ISENSE2, ISENSE3 +/-

3.12 /ILIMIT_OUT

3.13 PWM1H, PWM2H, PWM3H

3.14 PWM1L, PWM2L, PWM3L

3.15 LA, LB, LC

3.16 HA, HB, HC

3.17 PHA, PHB, PHC

3.18 VBA, VBB, VBC

3.19 DE2

3.20 HV_IN1, HV_IN2, LV_OUT1,LV_OUT2

4.0 DETAILED DESCRIPTION

4.1 BIAS GENERATOR

FIGURE 4-1: SMPS Functional Block Diagram.

4.2 MOTOR CONTROL UNIT

TABLE 4-1: COMMUTATION STATE MACHINE

4.3 CHIP ENABLE (CE)

4.4 COMMUNICATION PORTS

4.5 HOST COMMUNICATIONS

TABLE 4-2: DE2 COMMUNICATIONS COMMANDS TO MCP8024 FROM HOST

TABLE 4-3: DE2 COMMUNICATIONS MESSAGES FROM MCP8024 TO HOST

5.0 APPLICATION INFORMATION

5.1 Component Calculations

FIGURE 5-1: Charge Pump.

FIGURE 5-2: Typical Buck Application.

TABLE 5-1: MAX INDUCTANCE FOR BUCK DISCONTINUOUS MODE OPERATION

5.2 Device Overvoltage Protection

6.0 ERRATA

6.1 5V and 12V Regulator Overcurrent Messages

7.0 PACKAGING INFORMATION

7.1 Package Marking Information

APPENDIX A: REVISION HISTORY

PRODUCT IDENTIFICATION SYSTEM

Trademarks

Worldwide Sales and Service