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MCP6V51
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Datasheet MCP6V51 Datasheet

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MCP6V51
VIN+
V
SS
VIN–
1
2 3
5
4
V
DD
V
OUT
MCP6V51
SOT-23-5
VIN+
VIN–
V
SS
1
2
3
4
8
7
6
5
NC
NC
V
DD
V
OUT
NC
MCP6V51
MSOP-8
R
F
8.2 nF
V
OUT
40V
DD
R
SHUNT
R
G
0.05
20 k
100
U
1
MCP6V51
+
-
40V
DD
C
F
Load
I
L

45V, 2 MHz Zero-Drift Op Amp with EMI Filtering

Features

• High DC Precision:
-V
Drift: 36 nV/°C (max.)
OS
-VOS: 15 µV (max.)
- PSRR: 134 dB (min.)
- CMRR: 135 dB (min.)
•Low Noise:
- 10.2 nV/Hz at 1 kHz
-E
: 0.21 µV
ni
•Low Power:
-I
: 470 µA/amplifier (typ.)
Q
- Wide Supply Voltage Range: 4.5V to 45V
•Easy to Use:
- Input Range incl. Negative Rail
- Rail-to-Rail Output
- EMI Filtered Inputs
- Gain Bandwidth Product: 2 MHz
- Slew Rate 1.2V/µs
- Unity Gain Stable
• Small Packages: 5-Lead SOT23, 8-Lead MSOP
• Extended Temperature Range: -40°C to +125°C
, f = 0.1 Hz to 10 Hz
P-P

General Description

The Microchip Technology Inc. MCP6V51 operational amplifier employs dynamic offset correction for very low offset and offset drift. The device has a gain bandwidth product of 2 MHz (typical). It is unity-gain stable, has virtually no 1/f noise and excellent Power Supply Rejection Ratio (PSRR) and Common Mode Rejection Ratio (CMRR). The product operates with a single supply voltage that can range from 4.5V to 45V, (±2.25V to ±22.5V), while drawing 470 µA (typical) of quiescent current.
The MCP6V51 op amp is offered as a single-channel amplifier and is designed using an advanced CMOS process.

Package Types

Typical Applications

• Industrial Instrumentation, PLC
• Process Control
• Power Control Loops

Typical Application Circuit

• Sensor Conditioning
• Electronic Weight Scales
• Medical Instrumentation
• Automotive Monitors
• Low-side Current Sensing

Design Aids

• Microchip Advanced Part Selector (MAPS)
• Application Notes

Related Parts

• MCP6V71/1U/2/4: Zero-Drift, 2 MHz, 1.8V to 5V
• MCP6V81/1U/2/4: Zero-Drift, 5 MHz, 1.8V to 5V
2018 Microchip Technology Inc. DS20006136A-page 1
MCP6V51
-8
-6
-4
-2
0
2
4
6
8
-50 -25 0 25 50 75 100 125
Input Offset Voltage (μV)
Ambient Temperature (°C)
22 Samples V
DD
= 4.5V
-8
-6
-4
-2
0
2
4
6
8
-50-250 255075100125
Input Offset Voltage (μV)
Ambient Temperature (°C)
22 Samples V
DD
= 45V
Figure 1 and Figure 2 show input offset voltage versus
ambient temperature for different power supply voltages.
FIGURE 1: Input Offset Voltage vs. Ambient Temperature with V
DD
=4.5V.
As seen in Figure 1 and Figure 2, the MCP6V51 op amps have excellent performance across temperature.
The input offset voltage temperature drift (TC
) shown
1
is well within the specified maximum values of 31 nV/°C at VDD= 4.5V and 36 nV/°C at VDD=45V.
This performance supports applications with stringent DC precision requirements. In many cases, it will not be necessary to correct for temperature effects (i.e., calibrate) in a design. In the other cases, the correction will be small.
FIGURE 2: Input Offset Voltage vs. Ambient Temperature with V
DS20006136A-page 2 2018 Microchip Technology Inc.
DD
= 45V.
MCP6V51

1.0 ELECTRICAL CHARACTERISTICS

1.1 Absolute Maximum Ratings †
VDD-VSS ................................................................................................................................................................ 49.5V
Current at Input Pins ............................................................................................................................................±10 mA
Analog Inputs (V
All Other Inputs and Outputs .................................................................................................... V
Difference Input Voltage .............................................................................................................................................±1V
Output Short Circuit Current ........................................................................................................................... Continuous
Current at Output and Supply Pins ......................................................................................................................±50 mA
Storage Temperature .............................................................................................................................-65°C to +150°C
Maximum Junction Temperature .......................................................................................................................... +150°C
ESD protection on all pins (HBM, CDM, MM)   2 kV, 750V, 200V
†Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
Note 1: See Section 4.2.1, Input Protection.
+ and VIN-) (Note 1)..................................................................................... VSS- 1.0V to VDD+1.0V
IN
- 0.3V to VDD+0.3V
SS

1.2 Electrical Specifications

DC ELECTRICAL SPECIFICATIONS

Electrical Characteristics: Unless otherwise indicated, TA= +25°C, VDD= +4.5V to +45V, VSS= GND,
V
CM=VDD
/3, V
OUT=VDD
Parameters Sym. Min. Typ. Max. Units Conditions
Input Offset
Input Offset Voltage V
Input Offset Voltage Drift with Temperature (Linear Temp. Co.)
Input Offset Voltage Quadratic Te m p . C o.
Input Offset Voltage Aging V
Power Supply Rejection Ratio PSRR 134 160 — dB
Input Bias Current and Impedance
Input Bias Current I
Note 1: Not production tested. Limits set by characterization and/or simulation and provided as design guidance
only.
2: Figure 2-17 shows how V
/2, VL=VDD/2, RL=10k to VL and CL= 100 pF (refer to Figure 1-4 and Figure 1-5).
-15 ±2.4 +15 µV TA=+25°C
-31 ±5 +31 nV/°C TA= -40 to +125°C, =4.5V (Note 1)
V
DD
-36 ±7 +36 nV/°C TA= -40 to +125°C, = 45V
V
DD
TC
TC
OS
1
1
(Note 1)
TC
TC
OS
2
2
—±42—nV/
—±38—nV/
— ±2 — µV 408 hours Life Test at
TA= -40 to +125°C
2
°C
V
DD
TA= -40 to +125°C
2
°C
V
DD
=4.5V
= 45V
+150°C, measured at +25°C
B
CML
124 138 — dB T
-250 ±60 +250 pA VDD= 45V
and V
changed across temperature for the first production lot.
CMH
= -40°C to +125°C
A
V
= 45V (Note 1)
DD
2018 Microchip Technology Inc. DS20006136A-page 3
MCP6V51
DC ELECTRICAL SPECIFICATIONS (CONTINUED)
Electrical Characteristics: Unless otherwise indicated, TA= +25°C, VDD= +4.5V to +45V, VSS= GND,
V
CM=VDD
Input Bias Current across Temperature
Input Offset Current I
Input Offset Current across Temperature
Common Mode Input Impedance Z
Differential Input Impedance Z
Common Mode
Common Mode Input Voltage Range Low
Common Mode Input Voltage Range High
Common Mode Rejection Ratio CMRR 110 125 — dB V
Open-Loop Gain
DC Open-Loop Gain A
Output
Minimum Output Voltage Swing V
Note 1: Not production tested. Limits set by characterization and/or simulation and provided as design guidance
/3, V
OUT=VDD
/2, VL=VDD/2, RL=10k to VL and CL= 100 pF (refer to Figure 1-4 and Figure 1-5).
Parameters Sym. Min. Typ. Max. Units Conditions
I
B
I
B
OS
I
OS
I
OS
CM
DIFF
V
CML
V
CMHVDD
—±80—pAT
=+85°C
A
-4 ±1.4 +4 nA TA= +125°C (Note 1)
-1 ±0.28 +1 nA VDD= 45V
— ±0.32 — nA TA=+85°C
-8 ±0.45 +8 nA TA= +125°C (Note 1)
— 120G||3 — ||pF —2.5M||5.2 —||pF
——V
-0.3 V (Note 2)
SS
-2.1 — — V (Note 2)
=4.5V,
DD
= -0.3V to 2.4V
V
CM
(Note 2)
106 116 — dB V
=4.5V
DD
= -40°C to +125°C,
T
A
(Note 1)
CMRR 135 150 — dB V
= 45V,
DD
= -0.3V to 42.9V
V
CM
(Note 2)
128 140 — dB V
= 45V
DD
= -40°C to +125°C,
T
A
(Note 1)
OL
124 142 — dB VDD=4.5V,
V
= 0.3V to 4.2V
OUT
120 139 — dB VDD=4.5V
= -40°C to +125°C,
T
A
(Note 1)
A
OL
140 164 — dB VDD= 45V,
= 0.3V to 44.7V
V
OUT
134 160 — dB V
= 45V
DD
= -40°C to +125°C,
T
A
(Note 1)
OL
—VSS+45 VSS+60 mV RL=1k, VDD = 4.5V
—V
—V
+ 500 VSS+1000 RL=1k, VDD = 45V
SS
+6 VSS+20 RL=10k, VDD = 4.5V
SS
—VSS+50 VSS+70 RL=10k, VDD = 45V
only.
2: Figure 2-17 shows how V
CML
and V
changed across temperature for the first production lot.
CMH
DS20006136A-page 4 2018 Microchip Technology Inc.
MCP6V51
DC ELECTRICAL SPECIFICATIONS (CONTINUED)
Electrical Characteristics: Unless otherwise indicated, TA= +25°C, VDD= +4.5V to +45V, VSS= GND,
V
CM=VDD
Maximum Output Voltage Swing V
Output Short Circuit Current I
Closed-loop Output Resistance R
Capacitive Load Drive C
Power Supply
Supply Voltage V
Quiescent Current per Amplifier I
Power-on Reset (POR) Trip Voltage
Note 1: Not production tested. Limits set by characterization and/or simulation and provided as design guidance
/3, V
OUT=VDD
/2, VL=VDD/2, RL=10k to VL and CL= 100 pF (refer to Figure 1-4 and Figure 1-5).
Parameters Sym. Min. Typ. Max. Units Conditions
VDD-150 VDD- 100 — mV RL=1k, VDD = 4.5V
OH
V
- 2500 VDD-1500 — RL=1k, VDD = 45V
DD
-20 VDD-12 — RL=10k, VDD = 4.5V
V
DD
VDD-200 VDD- 100 — RL=10k, VDD = 45V
+ —46—mA
SC
- —36—mA
I
SC
OUT
—16 — f=0.1MHz, IO=0,
G=1
L
DD
Q
—100—pFG=1
4.5 — 45 V
310 460 590 µA VDD= 4.5V, IO=0
310 470 590 µA VDD= 45V, IO=0
— 540 670 µA IO=0,
T
= -40 to +125°C
A
(Note 1) (Figure 2-22)
V
POR
—2.3—V
only.
2: Figure 2-17 shows how V
CML
and V
changed across temperature for the first production lot.
CMH

AC ELECTRICAL SPECIFICATIONS

Electrical Characteristics: Unless otherwise indicated, TA= +25°C, VDD= +4.5V to +45V, VSS= GND,
V
CM=VDD
/3, V
OUT=VDD
Parameters Sym. Min. Typ. Max. Units Conditions
Amplifier AC Response
Gain Bandwidth Product GBWP — 1.8 — MHz V
Slew Rate SR — 1.2 — V/µs (Figure 2-44)
Phase Margin PM — 66 — deg. V
Amplifier Noise Response
Input Noise Voltage E
Input Noise Voltage Density e
Input Noise Current Density i
Amplifier Step Response
Start-Up Time t
Offset Correction Settling Time t
Note 1: Behavior may vary with different gains; see Section 4.3.3 “Offset at Power-Up”.
2: t
STL
and t
/2, VL=VDD/2, RL=10k to VL and CL= 100 pF (refer to Figure 1-4 and Figure 1-5).
= 4.5V, VIN= 10 mVpp, Gain = 100
DD
—2—MHzV
—0.1—µV
ni
E
ni
STR
STL
include some uncertainty due to clock edge timing.
ODR
—0.21—µV
ni
—10.2—nV/Hz f = 1 kHz
ni
—4—fA/Hz
— 200 — µs G = +1, 1% V
—45— µsG=+1, VIN step of 2V,
P-P
P-P
= 45V, VIN=10mVpp, Gain=100
DD
= 45V
DD
f=0.01Hz to 1Hz
f = 0.1 Hz to 10 Hz
settling (Note 1)
OUT
within ±100 µV of its final value
V
OS
2018 Microchip Technology Inc. DS20006136A-page 5
MCP6V51
AC ELECTRICAL SPECIFICATIONS (CONTINUED)
Electrical Characteristics: Unless otherwise indicated, TA= +25°C, VDD= +4.5V to +45V, VSS= GND,
V
CM=VDD
Output Overdrive Recovery Time t
EMI Protection
EMI Rejection Ratio EMIRR — 80 — dB V
Note 1: Behavior may vary with different gains; see Section 4.3.3 “Offset at Power-Up”.

TEMPERATURE SPECIFICATIONS

Electrical Characteristics: Unless otherwise indicated, all limits are specified for: VDD= +4.5V to +45V, VSS= GND.
Temperature Ranges
Specified Temperature Range T
Operating Temperature Range T
Storage Temperature Range T
Thermal Package Resistances
Thermal Resistance, 8LD-MSOP
Thermal Resistance, 5LD-SOT-23
Note 1: Operation must not cause T
/3, V
OUT=VDD
/2, VL=VDD/2, RL=10k to VL and CL= 100 pF (refer to Figure 1-4 and Figure 1-5).
Parameters Sym. Min. Typ. Max. Units Conditions
ODR
— 65 — µs G = -10, ±0.5V input overdrive to VDD/2,
50% point to V
V
IN
=0.1VPK, f = 400 MHz, VDD= 45V
IN
—95— VIN=0.1VPK, f = 900 MHz, VDD= 45V
—108— V
=0.1VPK, f = 1800 MHz, VDD=45V
IN
—109— VIN=0.1VPK, f = 2400 MHz, VDD=45V
—109— VIN=0.1VPK, f = 5600 MHz, VDD=45V
2: t
STL
and t
include some uncertainty due to clock edge timing.
ODR
Parameters Sym. Min. Typ. Max. Units Conditions
A
A
A
JA
JA
to exceed Maximum Junction Temperature specification (+150°C).
J
-40 — +125 °C
-40 — +125 °C (Note 1)
-65 — +150 °C
—206 — °C/W
—115 — °C/W
90% point (Note 2)
OUT
DS20006136A-page 6 2018 Microchip Technology Inc.
MCP6V51
V
DD
V
OUT
1.01(VDD/3)
0.99(V
DD
/3)
t
STR
0V
V
DD
2.3V
V
IN
V
OS
VOS+100µV
VOS–100µV
t
STL
V
IN
V
OUT
V
DD
V
SS
t
ODR
t
ODR
VDD/2
V
DD
R
G
R
F
R
N
V
OUT
V
IN
VDD/3
1µF
C
L
R
L
V
L
100 nF
R
ISO
MCP6V51
+
-
V
DD
R
G
R
F
R
N
V
OUT
VDD/3
V
IN
1µF
C
L
R
L
V
L
100 nF
R
ISO
MCP6V51
+
-
V
DD
V
OUT
1µF
C
L
V
L
R
ISO
1.1 k
249
1.1 k 500
V
IN
V
REF=VDD
/3
0.1%
0.1% 25 turn
10 k
10 k
0.1%
0.1%
R
L
0
100 pF open
100 nF
1%
MCP6V51

1.3 Timing Diagrams

The Timing Diagrams provide a depiction of the Amplifier Step Response specifications listed under the
AC Electrical Specifications table.
FIGURE 1-1: Amplifier Start-Up.
FIGURE 1-2: Offset Correction Settling
Time.

1.4 Test Circuits

The circuits used for most DC and AC tests are shown in Figure 1-4 and Figure 1-5. Lay the bypass capacitors out as discussed in Section 4.3.10 “Supply
Bypassing and Filtering”. R
combination of R
and RG to minimize bias current
F
effects.
FIGURE 1-4: AC and DC Test Circuit for Most Noninverting Gain Conditions.
is equal to the parallel
N
FIGURE 1-5: AC and DC Test Circuit for Most Inverting Gain Conditions.
The circuit in Figure 1-6 tests the input’s dynamic behavior (i.e., t balances the resistor network (V
FIGURE 1-3: Output Overdrive Recovery.
at DC). The op amp’s Common Mode Input Voltage is V
CM=VIN
V
OUT
/3. The error at the input (V
with a noise gain of approx. 10 V/V.
2018 Microchip Technology Inc. DS20006136A-page 7
FIGURE 1-6: Test Circuit for Dynamic Input Behavior.
STR
, t
STL
and t
). The potentiometer
ODR
should equal V
OUT
) appears at
ERR
REF
MCP6V51
NOTES:
DS20006136A-page 8 2018 Microchip Technology Inc.
MCP6V51
0%
5%
10%
15%
20%
25%
30%
35%
-10-8-6-4-20246810
Percentage of Occurences
Input Offset Voltage (μV)
7611 Samples
TA= 25ºC
VDD= 4.5V
VDD= 45V
0%
5%
10%
15%
20%
25%
30%
35%
40%
-18-15-12-9-6-30369121518
Percentage of Occurances
Input Offset Voltage Drift; TC1(nV/°C)
22 Samples T
A
= -40°C to +125°C
VDD= 4.5V
VDD= 45V
-20
-15
-10
-5
0
5
10
15
20
0 5 10 15 20 25 30 35 40 45
Input Offset Voltage (μV)
Power Supply Voltage (V)
TA= +85°C T
A
= +125°C
TA= +25°C
TA= -40°C
-8
-6
-4
-2
0
2
4
6
8
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
Input Offset Voltage (μV)
Output Voltage (V)
Representative Part
VDD= 4.5V
TA= +125°C T
A
= +85°C
T
A
= +25°C
T
A
= - 40°C
-8
-6
-4
-2
0
2
4
6
8
-1 4 9 14 19 24 29 34 39 44
Input Offset Voltage (μV)
Output Voltage (V)
Representative Part
VDD= 45V
TA= +125°C T
A
= +85°C
T
A
= +25°C
T
A
= - 40°C
-8.0
-6.0
-4.0
-2.0
0.0
2.0
4.0
6.0
8.0
-0.3 0.0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4
Input Offset Voltage (μV)
Common Mode Input Voltage (V)
TA= +125°C TA= +85°C TA= +25°C TA= - 40°C
VDD= 4.5V Representative Part

2.0 TYPICAL PERFORMANCE CURVES

Note: The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note: Unless otherwise indicated, TA=+25°C, VDD= +4.5V to +45V, VSS= GND, VCM=VDD/3, V V
L=VDD
/2, RL=10k to VL and CL= 100 pF.

2.1 DC Input Precision

FIGURE 2-1: Input Offset Voltage.

FIGURE 2-4: Input Offset Voltage vs.
Output Voltage with V
DD
=4.5V.
OUT=VDD
/2,

FIGURE 2-2: Input Offset Voltage Drift.

FIGURE 2-3: Input Offset Voltage vs.
Power Supply Voltage.
2018 Microchip Technology Inc. DS20006136A-page 9
FIGURE 2-5: Input Offset Voltage vs. Output Voltage with V
DD
=45V.
FIGURE 2-6: Input Offset Voltage vs. Common Mode Voltage with V
DD
=4.5V
MCP6V51
-8.0
-6.0
-4.0
-2.0
0.0
2.0
4.0
6.0
8.0
-1 4 9 14 19 24 29 34 39 44
Input Offset Voltage (μV)
Common Mode Input Voltage (V)
TA= +125°C T
A
= +85°C
T
A
= +25°C
T
A
= - 40°C
VDD= 45V Representative Part
0%
10%
20%
30%
40%
50%
60%
70%
80%
90%
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
Percentage of Occurrences
1/CMRR (μV/V)
488 Samples
TA= +25ºC
VDD= 4.5V
VDD= 45V
0%
5%
10%
15%
20%
25%
30%
35%
-0.1
-0.08
-0.06
-0.04
-0.02
0
0.02
0.04
0.06
0.08
0.1
Percentage of Occurrences
1/PSRR (μV/V)
488 Samples
TA= +25ºC
0%
10%
20%
30%
40%
50%
60%
-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
Percentage of Occurrences
1/AOL(μV/V)
474 Samples
TA= +25ºC
VDD= 45V
VDD= 4.5V
110
120
130
140
150
160
-50-250 255075100125
CMRR, PSRR (dB)
Ambient Temperature (°C)
PSRR
CMRR @ VDD= 45V
@ V
DD
= 4.5V
120
130
140
150
160
170
-50 -25 0 25 50 75 100 125
DC Open-Loop Gain (dB)
Ambient Temperature (°C)
VDD= 4.5V
VDD= 45V
FIGURE 2-7: Input Offset Voltage vs. Common Mode Voltage with V
DD
= 45V.

FIGURE 2-8: CMRR.

FIGURE 2-10: DC Open-Loop Gain.

FIGURE 2-11: CMRR and PSRR vs.
Ambient Temperature.

FIGURE 2-9: PSRR.

DS20006136A-page 10 2018 Microchip Technology Inc.

FIGURE 2-12: DC Open-Loop Gain vs. Ambient Temperature.

MCP6V51
-500
-400
-300
-200
-100
0
100
200
300
400
500
Input Bias, Offset Currents (pA)
Input Common Mode Voltage (V)
Input Bias Current
Input Offset Current
VDD= 45V
TA= +85 ºC
0 5 10 15 20 25 30 35 40 45
-1000
-500
0
500
1000
1500
2000
Input Bias, Offset Currents (pA)
Input Common Mode Voltage (V)
Input Bias Current
Input Offset Current
VDD= 45V
TA= +125 ºC
0 5 10 15 20 25 30 35 40 45
25
35
45
55
65
75
85
95
105
115
125
Input Bias, Offset Currents (A)
Ambient Temperature (°C)
10n
100
p
10
p
1
p
1n
I
B
I
OS
4.5V
45V
-1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0
Input Current Magnitude (A)
Input Voltage (V)
1m
10μ
100n
10n
1n
TA= +125°C T
A
= +85°C
T
A
= +25°C
T
A
= -40°C
100μ
1μ
100p
FIGURE 2-13: Input Bias and Offset Currents vs. Common Mode Input Voltage with T
= +85°C.
A
FIGURE 2-14: Input Bias and Offset Currents vs. Common Mode Input Voltage with T
= +125°C.
A
FIGURE 2-16: Input Bias Current vs. Input Voltage (Below V
SS
).
FIGURE 2-15: Input Bias and Offset Currents vs. Ambient Temperature with
= 45V.
V
DD
2018 Microchip Technology Inc. DS20006136A-page 11
MCP6V51
-0.5
0
0.5
1
1.5
2
2.5
-50 -25 0 25 50 75 100 125
Input Common Mode Voltage
Headroom (V)
Ambient Temperature (°C)
Upper (VDD-V
CMH
)
Lower (V
CML-VSS
)
1
10
100
1000
0.1 1 10
Output Voltage Headroom
(mV)
Output Current Magnitude (mA)
VDD= 45V
VDD= 4.5V
VDD-V
OH
VOL-V
SS
0
500
1000
1500
2000
-50 -25 0 25 50 75 100 125
Output Voltage Headroom (mV)
Ambient Temperature (°C)
VDD-V
OH
VDD= 45V
VOL-V
SS
VDD= 4.5V
RL= 1 kȍ
0
50
100
150
200
-50-25 0 255075100125
Output Voltage Headroom (mV)
Ambient Temperature (°C)
VOL-V
SS
VDD-V
OH
VDD= 45V
VDD= 4.5V
RL= 10 kȍ
-60
-40
-20
0
20
40
60
80
0 5 10 15 20 25 30 35 40 45
Output Short Circuit Current
(mA)
Power Supply Voltage (V)
TA= +125°C T
A
= +85°C
T
A
= +25°C
T
A
= -40°C
0
100
200
300
400
500
600
700
0 1020304050
Quiescent Current
(μA/Amplifier)
Power Supply Voltage (V)
TA= +125°C T
A
= +85°C
T
A
= +25°C
T
= -40°C
Note: Unless otherwise indicated, TA=+25°C, VDD= +4.5V to +45V, VSS= GND, VCM=VDD/3, V V
L=VDD
/2, RL=10k to VL and CL= 100 pF.

2.2 Other DC Voltages and Currents

FIGURE 2-17: Input Common Mode Voltage Headroom (Range) vs. Ambient Temperature.

FIGURE 2-20: Output Voltage Headroom vs Temperature RL = 10 k
.
OUT=VDD
/2,

FIGURE 2-18: Output Voltage Headroom vs. Output Current.

FIGURE 2-19: Output Voltage Headroom vs. Ambient Temperature.

DS20006136A-page 12 2018 Microchip Technology Inc.

FIGURE 2-21: Output Short Circuit Current vs. Power Supply Voltage.

A

FIGURE 2-22: Supply Current vs. Power Supply Voltage.

MCP6V51
0
20
40
60
80
100
120
140
160
180
CMRR, PSRR (dB)
Frequency (Hz)
1 10 100 1k 10k 100k 1M 10M
CMRR
PSRR+
PSRR-
VDD= 45V
-270
-240
-210
-180
-150
-120
-90
-60
-30
-20
0
20
40
60
80
100
120
140
1 10 100 1,000 10,000100,0001,000,00010,000,000
Frequency (Hz)
Open-Loop Phase (°)
Open-Loop Gain (dB)
Gain
Phase
GBWP = 1.8 MHz V
DD
= 4.5V RL= 10 kΩ CL= 100 pF
'RP3ROHP+]
10k
100k
1M 10M
1k
100
10
1
-270
-240
-210
-180
-150
-120
-90
-60
-30
-20
0
20
40
60
80
100
120
140
1 10 100 1,000 10,000100,0001,000,00010,000,000
Frequency (Hz)
Open-Loop Phase (°)
Open-Loop Gain (dB)
Gain
Phase
GBWP = 2 MHz V
DD
= 45V RL= 10 kΩ CL= 100 pF
'RP3ROHP+]
10k
100k
1M 10M
1k
100
10
1
10
20
30
40
50
60
70
80
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
-50 -25 0 25 50 75 100 125
Gain Bandwidth Product (MHz)
Ambient Temperature (°C)
GBWP
PM
VDD= 4.5V
Phase Margin
VDD= 45V
40
50
60
70
80
90
0
1
2
3
4
5
0 5 10 15 20 25 30 35 40 45
Phase Margin (º)
Gain Bandwidth Product (MHz)
Common Mode Input Voltage (V)
VDD= 45V
PM
GBWP
0.0001
0.001
0.01
0.1
1
10
100
1000
Closed Loop Output
Impedance (:)
Frequency (Hz)
GN: 101 V/V
11 V/V
1 V/V
VDD= 4.5V
1 10 100 1k 10k 100k 1M 10M 100M
Note: Unless otherwise indicated, TA=+25°C, VDD= +4.5V to +45V, VSS= GND, VCM=VDD/3, V V
L=VDD
/2, RL=10k to VL and CL= 100 pF.

2.3 Frequency Response

FIGURE 2-23: CMRR and PSRR vs. Frequency.

FIGURE 2-26: Gain Bandwidth Product and Phase Margin vs. Ambient Temperature.

OUT=VDD
/2,
FIGURE 2-24: Open-Loop Gain vs. Frequency with V
FIGURE 2-25: Open-Loop Gain vs. Frequency with V
2018 Microchip Technology Inc. DS20006136A-page 13
DD
DD
=4.5V.
=45V.

FIGURE 2-27: Gain Bandwidth Product and Phase Margin vs. Common Mode Input Voltage.

FIGURE 2-28: Closed-Loop Output Impedance vs. Frequency with V
DD
=4.5V.
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