Datasheet MCP6V31, MCP6V31U Datasheet

MCP6V31/1U

23 µA, 300 kHz Zero-Drift Op Amps

Features

• High DC Precision:

-V

Drift: ±50 nV/°C (maximum)

OS

-VOS: ±8 µV (maximum)

-AOL: 120 dB (minimum, VDD=5.5V)

- PSRR: 120 dB (minimum, V

- CMRR: 120 dB (minimum, VDD=5.5V)
: 1.0 µV

-E

ni

-E

: 0.33 µV

ni

• Low Power and Supply Voltages:

-IQ: 23 µA/amplifier (typical)

- Wide Supply Voltage Range: 1.8V to 5.5V

• Small Packages

- Singles in SC70, SOT-23

•Easy to Use:

- Rail-to-Rail Input/Output

- Gain Bandwidth Product: 300 kHz (typical)

- Unity Gain Stable

• Extended Temperature Range: -40°C to +125°C

(typical), f = 0.1 Hz to 10 Hz

P-P

(typical), f = 0.01 Hz to 1 Hz

P-P

DD

=5.5V)

Typical Applications

• Portable Instrumentation

• Sensor Conditioning

• Temperature Measurement

• DC Offset Correction

• Medical Instrumentation

Design Aids

• SPICE Macro Models

•FilterLab

• Microchip Advanced Part Selector (MAPS)

• Analog Demonstration and Evaluation Boards

• Application Notes

®

Software

Description

The Microchip Technology Inc. MCP6V31/1U family of
operational amplifiers provides input offset voltage
correction for very low offset and offset drift. These are
low power devices, with a gain bandwidth product of
300 kHz (typical). They are unity gain stable, have no
1/f noise, and have good Power Supply Rejection Ratio
(PSRR) and Common Mode Rejection Ratio (CMRR).
These products operate with a single supply voltage as
low as 1.8V, while drawing 23 µA/amplifier (typical) of
quiescent current.

The Microchip Technology Inc. MCP6V31/1U op amps
are offered in single (MCP6V31 and MCP6V31U)
packages. They were designed using an advanced
CMOS process.

Package Types

V

OUT

V

VIN+

MCP6V31

1

2

SS

3

SOT-23

5

4

V

DD

VIN–

MCP6V31U

SC70, SOT-23

VIN+

1

V

2

SS

V

–

3

IN

V

5

DD

V

4

OUT

Typical Application Circuit

R

V

IN

VDD/2

1

R

2

C

R

2

Offset Voltage Correction for Power Driver

2

U

2

MCP6V31

R

4

R

5

R

VDD/2

3

V

U

1

MCP6XXX

OUT

Related Parts

• MCP6V01/2/3: Auto-Zeroed, Spread Clock

• MCP6V06/7/8: Auto-Zeroed

• MCP6V26/7/8: Auto-Zeroed, Low Noise

• MCP6V11/1U: Zero-Drift, Low Power

© 2012 Microchip Technology Inc. DS25127A-page 1

MCP6V31/1U

NOTES:

DS25127A-page 2 © 2012 Microchip Technology Inc.

MCP6V31/1U

1.0 ELECTRICAL CHARACTERISTICS

1.1 Absolute Maximum Ratings †

VDD–VSS .................................................................................................................................................................6.5V

Current at Input Pins ..............................................................................................................................................±2 mA

Analog Inputs (V

+ and V

IN

All other Inputs and Outputs .......................................................................................................V

Difference Input voltage .................................................................................................................................|V

Output Short Circuit Current ...........................................................................................................................Continuous

Current at Output and Supply Pins ......................................................................................................................±30 mA

Storage Temperature .............................................................................................................................-65°C to +150°C

Maximum Junction Temperature .......................................................................................................................... +150°C

ESD protection on all pins (HBM, CDM, MM) ...........................................................................................≥ 2kV,1.5kV,400V

Note 1: See Section 4.2.1, Rail-to-Rail Inputs.

†Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the

device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.

–) (Note 1) .....................................................................................V

IN

– 1.0V to VDD+1.0V

SS

– 0.3V to VDD+0.3V

SS

DD–VSS

|

1.2 Specifications

TABLE 1-1: DC ELECTRICAL SPECIFICATIONS

Electrica l Characteristics: Unless otherwise indicated, T

V

CM

= VDD/3,V

OUT=VDD

/2, VL=VDD/2, RL = 100 kΩ to VL and CL = 20 pF (refer to Figure 1-4 and Figure 1-5).

Parameters Sym. Min. Typ. Max. Units Conditions

Input Offset

Input Offset Voltage V

Input Offset Voltage Drift with

TC

OS

1

Temperature (Linear Temp. Co.)

Input Offset Voltage Quadratic

TC

2

Te m p. Co .

Power Supply Rejection PSRR 120 135 — dB

Input Bias Current and Impedance

Input Bias Current I

Input Bias Current across Temperature I

Input Offset Current I

Input Offset Current across Temperature I

Common Mode Input Impedance Z

Differential Input Impedance Z

B

B

I

B

OS

OS

I

OS

CM

DIFF

Note 1: For Design Guidance only; not tested.

2: Figure 2-18 shows how V

CML

and V

changed across temperature for the first production lot.

CMH

= +25°C, VDD = +1.8V to +5.5V, VSS = GND,

A

-8 — +8 µV TA = +25°C

-50 — +50 nV/°C TA = -40 to +125°C

—±0.08 —nV/°C

—+5 —pA

—+20 —pAT

0+2.9+5nAT

—±130 —pA

—±140 —pAT

-1 ±0.4 +1 nA TA = +125°C

—10

—10

13

||6 — Ω||pF

13

||6 — Ω||pF

(Note 1)

2

TA = -40 to +125°C

= +85°C

A

= +125°C

A

= +85°C

A

© 2012 Microchip Technology Inc. DS25127A-page 3

MCP6V31/1U

TABLE 1-1: DC ELECTRICAL SPECIFICATIONS (CONTINUED)

Electrica l Characteristics: Unless otherwise indicated, T

V

CM

= VDD/3,V

OUT=VDD

/2, VL=VDD/2, RL = 100 kΩ to VL and CL = 20 pF (refer to Figure 1-4 and Figure 1-5).

Parameters Sym. Min. Typ. Max. Units Conditions

Common Mode

Common-Mode

V

CML

Input Voltage Range Low

Common-Mode

V

CMHVDD

Input Voltage Range High

Common-Mode Rejection CMRR 110 125 — dB V

CMRR 120 135 — dB V

Open-Loop Gain

DC Open-Loop Gain (large signal) A

OL

A

OL

Output

Minimum Output Voltage Swing V

Maximum Output Voltage Swing V

Output Short Circuit Current I

OL

V

OL

OH

V

OH

SC

I

SC

Power Supply

Supply Voltage V

Quiescent Current per amplifier I

POR Trip Voltage V

DD

Q

POR

Note 1: For Design Guidance only; not tested.

2: Figure 2-18 shows how V

CML

and V

changed across temperature for the first production lot.

CMH

= +25°C, VDD = +1.8V to +5.5V, VSS = GND,

A

——V

− 0.15 V (Note 2)

SS

+0.2 — — V (Note 2)

103 125 — dB VDD=1.8V,

120 135 — dB VDD=5.5V,

V

VSS+14 VSS+45 mV RL=10kΩ, G = +2,

SS

—VSS+1.4 — mV RL=100kΩ, G = +2,

VDD–45 VDD–14 V

DD

mV RL=10kΩ, G = +2,

—VDD–1.4 — mV RL=100kΩ, G = +2,

—±6 —mAV

—±21 —mAV

1.8 — 5.5 V

12 23 34 µA IO = 0

0.9 — 1.6 V

= 1.8V,

DD

V

= -0.15V to 2.0V

CM

(Note 2)

= 5.5V,

DD

V

= -0.15V to 5.7V

CM

(Note 2)

= 0.3V to 1.6V

V

OUT

V

= 0.3V to 5.3V

OUT

0.5V input overdrive

0.5V input overdrive

0.5V input overdrive

0.5V input overdrive

=1.8V

DD

=5.5V

DD

DS25127A-page 4 © 2012 Microchip Technology Inc.

MCP6V31/1U

TABLE 1-2: AC ELECTRICAL SPECIFICATIONS

Electrica l Characteristics: Unless otherwise indicated, T

= VDD/3, V

V

CM

OUT=VDD

/2, VL=VDD/2, RL=100kΩ to VL and CL= 20 pF (refer to Figure 1-4 and Figure 1-5).

Parameters Sym. Min. Typ. Max. Units Conditions

Amplifier AC Response

Gain Bandwidth Product GBWP — 300 — kHz

Slew Rate SR — 0.13 — V/µs

Phase Margin PM — 70 — ° G = +1

Amplifier Noise Response

Input Noise Voltage E

E

Input Noise Voltage Density e

Input Noise Current Density i

—0.33—µV

ni

—1.0—µV

ni

—50—nV/√Hz f < 2 kHz

ni

—5—fA/√Hz

ni

Amplifier Distortion (Note 1)

Intermodulation Distortion (AC) IMD — 52 — µV

Amplifier Step Response

Start Up Time t

Offset Correction Settling Time t

Output Overdrive Recovery Time t

STR

STL

ODR

— 2 — ms G = +1, 0.1% V

— 100 — µs G = +1, VIN step of 2V,

— 120 — µs G = -10, ±0.5V input overdrive to VDD/2,

Note 1: These parameters were characterized using the circuit in Figure 1-6. In Figure 2-36 and Figure 2-37,

there is an IMD tone at DC, a residual tone at 100 Hz and other IMD tones and clock tones.

2: High gains behave differently; see Section 4.3.3, Offset at Power Up.
3: t

includes some uncertainty due to clock edge timing.

ODR

= +25°C, VDD = +1.8V to +5.5V, VSS = GND,

A

f = 0.01 Hz to 1 Hz

P-P

f = 0.1 Hz to 10 Hz

P-P

PKVCM

V

OS

V

IN

tone = 50 mV

within 100 µV of its final value

50% point to V

at 100 Hz, GN = 1

PK

settling (Note 2)

OUT

90% point (Note 3)

OUT

TABLE 1-3: TEMPERATURE SPECIFICATIONS

Electrica l Characteristics: Unless otherwise indicated, all limits are specified for: V

VSS = GND.

Parameters Sym. Min. Typ. Max. Units Conditions

Temperature Ranges

Specified Temperature Range T

Operating Temperature Range T

Storage Temperature Range T

Thermal Package Resistances

Thermal Resistance, 5L-SC-70 θ

Thermal Resistance, 5L-SOT-23 θ

Note 1: Operation must not cause T

to exceed Maximum Junction Temperature specification (+150°C).

J

A

A

A

JA

JA

-40 — +125 °C

-40 — +125 °C (Note 1)

-65 — +150 °C

—331 — °C/W

—256 — °C/W

= +1.8V to +5.5V,

DD

© 2012 Microchip Technology Inc. DS25127A-page 5

MCP6V31/1U

1.3 Timing Diagrams

0V

1.8V

t

STR

V

V

DD

OUT

FIGURE 1-1: Amplifier Start Up.

V

IN

t

STL

V

OS

FIGURE 1-2: Offset Correction Settling Time.

V

IN

t

ODR

V

DD

V

OUT

VDD/2

FIGURE 1-3: Output Overdrive Recovery.

1.8V to 5.5V

1.001(VDD/3)

0.999(V

VOS+100µV

VOS–100µV

t

ODR

V

SS

DD

/3)

1.4 Test Circuits

The circuits used for most DC and AC tests are shown
in Figure 1-4 and Figure 1-5. Lay the bypass capacitors
out as discussed in Section 4.3.10, Supply Bypassing

and Filtering. R

and RG to minimize bias current effects.

R

F

V

IN

MCP6V3X

VDD/3

FIGURE 1-4: AC and DC Test Circuit for Most Non-Inverting Gain Cond iti ons.

VDD/3

MCP6V3X

V

IN

FIGURE 1-5: AC and DC Test Circuit for Most Inverting Gain Conditions.

The circuit in Figure 1-6 tests the input’s dynamic
behavior (i.e., IMD, t
potentiometer balances the resistor network (V
should equal V
mode input voltage is V
input (V
10 V/V.

ERR

is equal to the parallel combination of

N

V

DD

1µF

R

N

R

G

V

DD

R

N

R

G

at DC). The op amp’s common

REF

) appears at V

100 nF

100 nF

STR

CM=VIN

R

ISO

C

L

R

F

1µF

R

ISO

C

L

R

F

, t

and t

STL

/2. The error at the

with a noise gain of

OUT

R

R

ODR

L

V

L

V

V

OUT

L

V

OUT

L

). The

OUT

11.0 kΩ 500 Ω

V

IN

11.0 kΩ

100 kΩ

0.1% 25 turn

0.1%

V

DD

1µF

100 nF

MCP6V3X

249 Ω

1%

0.1%

100 kΩ

0.1%

V

REF=VDD

R

ISO

/3

0 Ω

V

OUT

C

L

R

L

20 pF open

V

L

FIGURE 1-6: Test Circuit for Dynamic Input Behavior.

DS25127A-page 6 © 2012 Microchip Technology Inc.

MCP6V31/1U

n

6

Representative Part

e

0

V

O

+85

C

6

p

e

0

V

O

85

C

6

e

0

V

O

I

8

2.0 TYPICAL PERFORMANCE CURVES

Note: The graphs and tables provided following this note are a statistical summary based on a limited number of

samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.

Note: Unless otherwise indicated, T

L=VDD

/2, RL=100kΩ to VL and CL = 20 pF.

V

=+25°C, VDD= +1.8V to 5.5V, VSS= GND, VCM=VDD/3, V

A

2.1 DC Input Precision

25%

42 Samples

= +25°C

T

A

= 1.8V and 5.5V

V

DD

20%

15%

10%

age of Occurrences

5%

Percent

0%

-8-7-6-5-4-3-2-1012345678

FIGURE 2-1: Input Offset Voltage.

35%

42 Samples
V

DD

30%

25%

20%

15%

age of Occurrences

10%

5%

Percent

0%

-50 -40 -30 -20 -10 0 10 20 30 40 50

FIGURE 2-2: Input Offset Voltage Drift.

Input Offset Voltage (μV)

= 1.8V and 5.5V

Input Offset Voltage Drift; TC1(nV/°C)

8

4

(μV)

2

oltag

ffset

-2

-4

Input

-6

-8

0.0

+125°C

°

+25°C

-40°C

0.5

1.0

1.5

2.0

Power Supply Voltage (V)

2.5

3.0

OUT=VDD

3.5

4.0

VCM= V

4.5

CML

5.0

/2,

5.5

FIGURE 2-4: Input Offset Voltage vs.
Power Supply Voltage with V

8

4

(μV)

2

oltag

ffset

-2

-4

Input

-6

-8

0.0

+125°C

+

°

+25°C

-40°C

0.5

1.0

1.5

2.0

Power Supply Voltage (V)

2.5

3.0

CM=VCML

VCM= V
Representative Part

3.5

4.0

4.5

CMH

5.0

.

5.5

FIGURE 2-5: Input Offset Voltage vs.
Power Supply Voltage with V

CM=VCMH

.

6.0

6.0

6.5

6.5

45%

42 Samples

= 1.8V and 5.5V

V

40%

DD

35%

30%

25%

20%

15%

tage of Occurrences

10%

5%

Perce

0%

-0.5 -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0.5
Input Offset Voltage's Quadratic Temp Co;

TC

(nV/°C2)

2

FIGURE 2-3: Input Offset Voltage Quadratic Temp. Co.

8

4

(μV)

2

oltag

ffset

nput

VDD= 1.8V

-2

-4

-6

-

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Power Supply Voltage (V)

Representative Part

VDD= 5.5V

FIGURE 2-6: Input Offset Voltage vs. Output Voltage.

© 2012 Microchip Technology Inc. DS25127A-page 7

MCP6V31/1U

6

Representative Part

e

0

V

O

+25

C

6

Representative Part

e

0

V

O

+25

C

s

35%

r

25%

a

e

s

60%

r

30%

a

e

VDD1.8V

145

135

S

CMRR

VDD=5.5V

Note: Unless otherwise indicated, T

=+25°C, VDD= +1.8V to 5.5V, VSS= GND, VCM=VDD/3, V

A

VL=VDD/2, RL=100kΩ to VL and CL = 20 pF.

8

4

(μV)

2

oltag

ffset

-2

-4

Input

-6

-8

-0.5 0.0 0.5 1.0 1.5 2.0 2.5

VDD= 1.8V

+125°C
+85°C

°

-40°C

Input Common Mode Voltage (V)

FIGURE 2-7: Input Offset Voltage vs.
Common Mode Voltage with V

8

4

(μV)

2

oltag

ffset

-2

-4

Input

-6

-8

-0.5

0.0

VDD= 5.5V

+125°C
+85°C

°

-40°C

0.5

1.0

1.5

2.0

Input Common Mode Voltage (V)

2.5

3.0

DD

3.5

=1.8V.

4.0

4.5

5.0

5.5

FIGURE 2-8: Input Offset Voltage vs.
Common Mode Voltage with V

DD

=5.5V.

6.0

OUT=VDD

50%

20 Samples

45%

40%

rence

30%

Occu

20%

ge of

15%

rcent

10%

P

= +25°C

T

A

5%

0%

-1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0
1/PSRR (μV/V)

/2,

FIGURE 2-10: PSRR.

90%

21 Samples

= +25°C

T

80%

70%

rence

1/A

OL

VDD= 5.5V

(μV/V)

50%

Occu

40%

ge of

20%

rcent
P

10%

0%

=

-0.5 -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0.5

FIGURE 2-11: DC Open-Loop Gain.

80%

21 Samples
T

= 25°C

A

70%

60%

50%

40%

30%

tage of Occurrences

20%

10%

Percen

0%

-1.6

-1.2

VDD= 5.5V

-0.8

-0.4

1/CMRR (μV/V)

FIGURE 2-9: CMRR.

0.0

0.4

VDD= 1.8V

0.8

1.2

1.6

160

155

150

B)

140

RR (d

130

RR, P

125

CM

120

115

110

-50 -25 0 25 50 75 100 125

VDD= 1.8V

Ambient Temperature (°C)

PSRR

FIGURE 2-12: CMRR and PSRR vs. Ambient Temperature.

DS25127A-page 8 © 2012 Microchip Technology Inc.

MCP6V31/1U

145

n

V

135

o

e

D

V

150

p

DD

0

e

s
u

I

OS

4000

p

VDD=5.5V

r

e

I

s

1000

u

A

r

100

e

100

s

1p

1.E

03

A

1m

M

1.E-08

u

+85

C

10n

p

p

Note: Unless otherwise indicated, T

=+25°C, VDD= +1.8V to 5.5V, VSS= GND, VCM=VDD/3, V

A

VL=VDD/2, RL=100kΩ to VL and CL = 20 pF.

160

155

150

(dB)

140

p Gai

130

n-Lo

125

C Op

120

115

110

-50 -25 0 25 50 75 100 125

VDD= 5.5V

= 1.8V

DD

Ambient Temperature (°C)

FIGURE 2-13: DC Open-Loop Gain vs. Ambient Temperature.

200

A)

100

ents (

50

t Curr

-50

, Offs

-100

t Bia

-150

Inp

-200

TA= +85°C

= 5.5V

0.0

0.5

1.0

1.5

-0.5

Common Mode Input Voltage (V)

2.0

2.5

I

B

3.0

3.5

4.0

4.5

5.0

5.5

6.0

FIGURE 2-14: Input Bias and Offset
Currents vs. Common Mode Input Voltage with
T

= +85°C.

A

OUT=VDD

10000

1n

VDD= 5.5V

)

1000

1n

ents (

t Cur

, Offs

10p

ut Bia

Inp

10

I

p

1

OS

I

B

25 35 45 55 65 75 85 95 105 115 125

Ambient Temperature (°C)

/2,

FIGURE 2-16: Input Bias and Offset
Currents vs. Ambient Temperature with
V

=+5.5V.

DD

1.E-02

10m

)

-

1.E-04

100μ

ude (

1.E-05

10μ

agnit

1.E-06

1μ

1.E-07

100n

rrent

1.E-09

1n

put C
In

1.E-10

100p

1.E-11

10

-1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0

+125°C

°

+25°C

-40°C

Input Voltage (V)

FIGURE 2-17: Input Bias Current vs. Input
Voltage (below V

SS

).

5000

TA= +125°C

A)

ents (

3000

2000

t Cur

1000

, Offs

t Bia

-

Inp

-2000

0

-0.5

B

I

OS

0.0

0.5

1.0

1.5

2.0

2.5

3.0

Common Mode Input Voltage (V)

3.5

4.0

4.5

5.0

5.5

6.0

FIGURE 2-15: Input Bias and Offset
Currents vs. Common Mode Input Voltage with
T

= +125°C.

A

© 2012 Microchip Technology Inc. DS25127A-page 9

MCP6V31/1U

0.3

g

0.0

o

m

H

p

V

r

VDDV

OH

V

V

10

V

u

4

u

o

10

C

35%

e

1 Wafer Lot

20%

f

t

5%

P

0

Note: Unless otherwise indicated, T

=+25°C, VDD= +1.8V to 5.5V, VSS= GND, VCM=VDD/3, V

A

VL=VDD/2, RL=100kΩ to VL and CL = 20 pF.

2.2 Other DC Voltages and Currents

0.4

e

Upper ( V

0.2

Vol ta

0.1

m (V)

Mode

mon

-0.1

eadro

ut Co

In

Lower (V

-0.2

-0.3

-0.4

-50 -25 0 25 50 75 100 125

)

CMH–VDD

)

CML–VSS

Ambient Temperature (°C)

FIGURE 2-18: Input Common Mode Voltage Headroom (Range) vs. Ambient Temperature.

1000

)

oom (

100

Head

oltage

tput
O

1

0.1 1 10

–

VOL–V

SS

Output Current Magnitude (V)

FIGURE 2-19: Output Voltage Headroom vs. Output Current.

1 Wafer Lot

VDD= 5.5V

= 1.8

DD

4.5

5.0

/2,

5.5

6.0

6.5

40

0.0

-40°C
+25°C
+85°C

+125°C

+125°C

+85°C
+25°C

-40°C

0.5

1.0

1.5

Power Supply Voltage (V)

30

20

10

0

-10

rt Circuit Current (mA)

-20

-30

Output Sh

-40

2.0

2.5

3.0

3.5

OUT=VDD

4.0

FIGURE 2-21: Output Short Circuit Current vs. Power Supply Voltage.

30

25

20

15

urrent (μA/amplifier)

5

Supply

0

1.5

2.0

+125°C

+85°C
+25°C

-40°C

2.5

3.0

3.5

Power Supply Voltage (V)

4.0

4.5

5.0

5.5

FIGURE 2-22: Supply Current vs. Power Supply Voltage.

12

RL= 25 k

11

10

9
8
7

VDD= 5.5V

6
5

t Headroom (mV)

3

Outp

2

VDD= 1.8V

1
0

-50 -25 0 25 50 75 100 125

VOL–V

Ambient Temperature (°C)

VDD–V

SS

OH

FIGURE 2-20: Output Voltage Headroom vs. Ambient Temperature.

40%

850 Samples

s

TA= +25°C

30%

rrenc

25%

Occu

15%

age o

10%

ercen

0%

1.101.121.141.161.181.201.221.241.261.281.3

POR Trip Voltage (V)

FIGURE 2-23: Power-on Reset Trip Voltage.

DS25127A-page 10 © 2012 Microchip Technology Inc.

MCP6V31/1U

R

Note: Unless otherwise indicated, T

=+25°C, VDD= +1.8V to 5.5V, VSS= GND, VCM=VDD/3, V

A

VL=VDD/2, RL=100kΩ to VL and CL = 20 pF.

1.6

1.4

1.2

1.0

0.8

0.6

Trip Voltage (V)

0.4

PO

0.2

0.0

-50 -25 0 25 50 75 100 125
Ambient Temperature (°C)

FIGURE 2-24: Power-on Reset Voltage vs. Ambient Temperature.

OUT=VDD

/2,

© 2012 Microchip Technology Inc. DS25127A-page 11

MCP6V31/1U

R

CMRR



180

10

n

n

O



180

10

n

n
h

d

h

h

Note: Unless otherwise indicated, T

=+25°C, VDD= +1.8V to 5.5V, VSS= GND, VCM=VDD/3, V

A

VL=VDD/2, RL=100kΩ to VL and CL = 20 pF.

2.3 Frequency Response

110

100

90

80

70

60

50

R, PSRR (dB)

40

CM

30

20

10

10 10k

1.E+01 1.E+02 1.E+03 1.E+04 1.E+05

100

Frequency (Hz)

FIGURE 2-25: CMRR and PSRR vs. Frequency.

70

60

50

40

30

20

-Loop Gain (dB)

0

Ope

-10

-20

1k 10k 1M100k

1.E+03 1.E+04 1.E+05 1.E+06

Frequency (Hz)

FIGURE 2-26: Open-Loop Gain vs.
Frequency with V

DD

=1.8V.

PSRR

| AOL|

VDD= 1.8V

= 20 pF

C

L

A

OL

0

-30

-60

-90

-120

-150

-

-210

-240

-270

100k1k

-Loop Phase (°)

Ope

OUT=VDD

700

600

500

400

300

width Product (kHz)

200

100

Gain Ban

0

-50 -25 0 25 50 75 100 125

PM

GBWP

Ambient Temperature (°C)

VDD= 5.5V

VDD= 1.8V

/2,

100

90

80

70

60

50

40

30

FIGURE 2-28: Gain Bandwidth Product and Phase Margin vs. Ambient Temperature.

5.0

5.5

100

90

80

70

60

50

40

30

6.0

700

600

500

400

300

dwidth Product (kHz)

200

100

Gain Ban

0

PM

2.0

2.5

VDD= 1.8V

3.0

GBWP

0.0

0.5

1.0

-0.5

1.5

Common Mode Input Voltage (V)

3.5

4.0

RF= 1 M

VDD= 5.5V

4.5

FIGURE 2-29: Gain Bandwidth Product and Phase Margin vs. Common Mode Input Voltage.

ase Margin (°)
P

ase Margin (°)
P

70

60

50

40

30

20

-Loop Gain (dB)

0

Ope

-10

-20

1k 10k 1M100k

1.E+03 1.E+04 1.E+05 1.E+06

Frequency (Hz)

| A

VDD= 5.5V
C

L

A

OL

|

L

= 20 pF

FIGURE 2-27: Open-Loop Gain vs.
Frequency with V

DD

=5.5V.

0

-30

-60

-90

-120

-150

-

-210

-240

-270

-Loop Phase (°)

Ope

700

600

500

400

300

dwidth Product (kHz)

200

100

Gain Ban

0

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

PM

GBWP

VDD= 1.8V

Output Voltage (V)

VDD= 5.5V

FIGURE 2-30: Gain Bandwidth Product and Phase Margin vs. Output Voltage.

100

90

80

70

60

50

40

30

ase Margin (°)
P

DS25127A-page 12 © 2012 Microchip Technology Inc.