Datasheet MCP6V31, MCP6V31U Datasheet

MCP6V31/1U

23 µA, 300 kHz Zero-Drift Op Amps

Features

• High DC Precision:

-V

Drift: ±50 nV/°C (maximum)

OS

-VOS: ±8 µV (maximum)

-AOL: 120 dB (minimum, VDD=5.5V)

- PSRR: 120 dB (minimum, V

- CMRR: 120 dB (minimum, VDD=5.5V)
: 1.0 µV

-E

ni

-E

: 0.33 µV

ni

• Low Power and Supply Voltages:

-IQ: 23 µA/amplifier (typical)

- Wide Supply Voltage Range: 1.8V to 5.5V

• Small Packages

- Singles in SC70, SOT-23

•Easy to Use:

- Rail-to-Rail Input/Output

- Gain Bandwidth Product: 300 kHz (typical)

- Unity Gain Stable

• Extended Temperature Range: -40°C to +125°C

(typical), f = 0.1 Hz to 10 Hz

P-P

(typical), f = 0.01 Hz to 1 Hz

P-P

DD

=5.5V)

Typical Applications

• Portable Instrumentation

• Sensor Conditioning

• Temperature Measurement

• DC Offset Correction

• Medical Instrumentation

Design Aids

• SPICE Macro Models

•FilterLab

• Microchip Advanced Part Selector (MAPS)

• Analog Demonstration and Evaluation Boards

• Application Notes

®

Software

Description

The Microchip Technology Inc. MCP6V31/1U family of
operational amplifiers provides input offset voltage
correction for very low offset and offset drift. These are
low power devices, with a gain bandwidth product of
300 kHz (typical). They are unity gain stable, have no
1/f noise, and have good Power Supply Rejection Ratio
(PSRR) and Common Mode Rejection Ratio (CMRR).
These products operate with a single supply voltage as
low as 1.8V, while drawing 23 µA/amplifier (typical) of
quiescent current.

The Microchip Technology Inc. MCP6V31/1U op amps
are offered in single (MCP6V31 and MCP6V31U)
packages. They were designed using an advanced
CMOS process.

Package Types

V

OUT

V

VIN+

MCP6V31

1

2

SS

3

SOT-23

5

4

V

DD

VIN–

MCP6V31U

SC70, SOT-23

VIN+

1

V

2

SS

V

–

3

IN

V

5

DD

V

4

OUT

Typical Application Circuit

R

V

IN

VDD/2

1

R

2

C

R

2

Offset Voltage Correction for Power Driver

2

U

2

MCP6V31

R

4

R

5

R

VDD/2

3

V

U

1

MCP6XXX

OUT

Related Parts

• MCP6V01/2/3: Auto-Zeroed, Spread Clock

• MCP6V06/7/8: Auto-Zeroed

• MCP6V26/7/8: Auto-Zeroed, Low Noise

• MCP6V11/1U: Zero-Drift, Low Power

© 2012 Microchip Technology Inc. DS25127A-page 1

MCP6V31/1U

NOTES:

DS25127A-page 2 © 2012 Microchip Technology Inc.

MCP6V31/1U

1.0 ELECTRICAL CHARACTERISTICS

1.1 Absolute Maximum Ratings †

VDD–VSS .................................................................................................................................................................6.5V

Current at Input Pins ..............................................................................................................................................±2 mA

Analog Inputs (V

+ and V

IN

All other Inputs and Outputs .......................................................................................................V

Difference Input voltage .................................................................................................................................|V

Output Short Circuit Current ...........................................................................................................................Continuous

Current at Output and Supply Pins ......................................................................................................................±30 mA

Storage Temperature .............................................................................................................................-65°C to +150°C

Maximum Junction Temperature .......................................................................................................................... +150°C

ESD protection on all pins (HBM, CDM, MM) ...........................................................................................≥ 2kV,1.5kV,400V

Note 1: See Section 4.2.1, Rail-to-Rail Inputs.

†Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the

device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.

–) (Note 1) .....................................................................................V

IN

– 1.0V to VDD+1.0V

SS

– 0.3V to VDD+0.3V

SS

DD–VSS

|

1.2 Specifications

TABLE 1-1: DC ELECTRICAL SPECIFICATIONS

Electrica l Characteristics: Unless otherwise indicated, T

V

CM

= VDD/3,V

OUT=VDD

/2, VL=VDD/2, RL = 100 kΩ to VL and CL = 20 pF (refer to Figure 1-4 and Figure 1-5).

Parameters Sym. Min. Typ. Max. Units Conditions

Input Offset

Input Offset Voltage V

Input Offset Voltage Drift with

TC

OS

1

Temperature (Linear Temp. Co.)

Input Offset Voltage Quadratic

TC

2

Te m p. Co .

Power Supply Rejection PSRR 120 135 — dB

Input Bias Current and Impedance

Input Bias Current I

Input Bias Current across Temperature I

Input Offset Current I

Input Offset Current across Temperature I

Common Mode Input Impedance Z

Differential Input Impedance Z

B

B

I

B

OS

OS

I

OS

CM

DIFF

Note 1: For Design Guidance only; not tested.

2: Figure 2-18 shows how V

CML

and V

changed across temperature for the first production lot.

CMH

= +25°C, VDD = +1.8V to +5.5V, VSS = GND,

A

-8 — +8 µV TA = +25°C

-50 — +50 nV/°C TA = -40 to +125°C

—±0.08 —nV/°C

—+5 —pA

—+20 —pAT

0+2.9+5nAT

—±130 —pA

—±140 —pAT

-1 ±0.4 +1 nA TA = +125°C

—10

—10

13

||6 — Ω||pF

13

||6 — Ω||pF

(Note 1)

2

TA = -40 to +125°C

= +85°C

A

= +125°C

A

= +85°C

A

© 2012 Microchip Technology Inc. DS25127A-page 3

MCP6V31/1U

TABLE 1-1: DC ELECTRICAL SPECIFICATIONS (CONTINUED)

Electrica l Characteristics: Unless otherwise indicated, T

V

CM

= VDD/3,V

OUT=VDD

/2, VL=VDD/2, RL = 100 kΩ to VL and CL = 20 pF (refer to Figure 1-4 and Figure 1-5).

Parameters Sym. Min. Typ. Max. Units Conditions

Common Mode

Common-Mode

V

CML

Input Voltage Range Low

Common-Mode

V

CMHVDD

Input Voltage Range High

Common-Mode Rejection CMRR 110 125 — dB V

CMRR 120 135 — dB V

Open-Loop Gain

DC Open-Loop Gain (large signal) A

OL

A

OL

Output

Minimum Output Voltage Swing V

Maximum Output Voltage Swing V

Output Short Circuit Current I

OL

V

OL

OH

V

OH

SC

I

SC

Power Supply

Supply Voltage V

Quiescent Current per amplifier I

POR Trip Voltage V

DD

Q

POR

Note 1: For Design Guidance only; not tested.

2: Figure 2-18 shows how V

CML

and V

changed across temperature for the first production lot.

CMH

= +25°C, VDD = +1.8V to +5.5V, VSS = GND,

A

——V

− 0.15 V (Note 2)

SS

+0.2 — — V (Note 2)

103 125 — dB VDD=1.8V,

120 135 — dB VDD=5.5V,

V

VSS+14 VSS+45 mV RL=10kΩ, G = +2,

SS

—VSS+1.4 — mV RL=100kΩ, G = +2,

VDD–45 VDD–14 V

DD

mV RL=10kΩ, G = +2,

—VDD–1.4 — mV RL=100kΩ, G = +2,

—±6 —mAV

—±21 —mAV

1.8 — 5.5 V

12 23 34 µA IO = 0

0.9 — 1.6 V

= 1.8V,

DD

V

= -0.15V to 2.0V

CM

(Note 2)

= 5.5V,

DD

V

= -0.15V to 5.7V

CM

(Note 2)

= 0.3V to 1.6V

V

OUT

V

= 0.3V to 5.3V

OUT

0.5V input overdrive

0.5V input overdrive

0.5V input overdrive

0.5V input overdrive

=1.8V

DD

=5.5V

DD

DS25127A-page 4 © 2012 Microchip Technology Inc.

MCP6V31/1U

TABLE 1-2: AC ELECTRICAL SPECIFICATIONS

Electrica l Characteristics: Unless otherwise indicated, T

= VDD/3, V

V

CM

OUT=VDD

/2, VL=VDD/2, RL=100kΩ to VL and CL= 20 pF (refer to Figure 1-4 and Figure 1-5).

Parameters Sym. Min. Typ. Max. Units Conditions

Amplifier AC Response

Gain Bandwidth Product GBWP — 300 — kHz

Slew Rate SR — 0.13 — V/µs

Phase Margin PM — 70 — ° G = +1

Amplifier Noise Response

Input Noise Voltage E

E

Input Noise Voltage Density e

Input Noise Current Density i

—0.33—µV

ni

—1.0—µV

ni

—50—nV/√Hz f < 2 kHz

ni

—5—fA/√Hz

ni

Amplifier Distortion (Note 1)

Intermodulation Distortion (AC) IMD — 52 — µV

Amplifier Step Response

Start Up Time t

Offset Correction Settling Time t

Output Overdrive Recovery Time t

STR

STL

ODR

— 2 — ms G = +1, 0.1% V

— 100 — µs G = +1, VIN step of 2V,

— 120 — µs G = -10, ±0.5V input overdrive to VDD/2,

Note 1: These parameters were characterized using the circuit in Figure 1-6. In Figure 2-36 and Figure 2-37,

there is an IMD tone at DC, a residual tone at 100 Hz and other IMD tones and clock tones.

2: High gains behave differently; see Section 4.3.3, Offset at Power Up.
3: t

includes some uncertainty due to clock edge timing.

ODR

= +25°C, VDD = +1.8V to +5.5V, VSS = GND,

A

f = 0.01 Hz to 1 Hz

P-P

f = 0.1 Hz to 10 Hz

P-P

PKVCM

V

OS

V

IN

tone = 50 mV

within 100 µV of its final value

50% point to V

at 100 Hz, GN = 1

PK

settling (Note 2)

OUT

90% point (Note 3)

OUT

TABLE 1-3: TEMPERATURE SPECIFICATIONS

Electrica l Characteristics: Unless otherwise indicated, all limits are specified for: V

VSS = GND.

Parameters Sym. Min. Typ. Max. Units Conditions

Temperature Ranges

Specified Temperature Range T

Operating Temperature Range T

Storage Temperature Range T

Thermal Package Resistances

Thermal Resistance, 5L-SC-70 θ

Thermal Resistance, 5L-SOT-23 θ

Note 1: Operation must not cause T

to exceed Maximum Junction Temperature specification (+150°C).

J

A

A

A

JA

JA

-40 — +125 °C

-40 — +125 °C (Note 1)

-65 — +150 °C

—331 — °C/W

—256 — °C/W

= +1.8V to +5.5V,

DD

© 2012 Microchip Technology Inc. DS25127A-page 5

MCP6V31/1U

1.3 Timing Diagrams

0V

1.8V

t

STR

V

V

DD

OUT

FIGURE 1-1: Amplifier Start Up.

V

IN

t

STL

V

OS

FIGURE 1-2: Offset Correction Settling Time.

V

IN

t

ODR

V

DD

V

OUT

VDD/2

FIGURE 1-3: Output Overdrive Recovery.

1.8V to 5.5V

1.001(VDD/3)

0.999(V

VOS+100µV

VOS–100µV

t

ODR

V

SS

DD

/3)

1.4 Test Circuits

The circuits used for most DC and AC tests are shown
in Figure 1-4 and Figure 1-5. Lay the bypass capacitors
out as discussed in Section 4.3.10, Supply Bypassing

and Filtering. R

and RG to minimize bias current effects.

R

F

V

IN

MCP6V3X

VDD/3

FIGURE 1-4: AC and DC Test Circuit for Most Non-Inverting Gain Cond iti ons.

VDD/3

MCP6V3X

V

IN

FIGURE 1-5: AC and DC Test Circuit for Most Inverting Gain Conditions.

The circuit in Figure 1-6 tests the input’s dynamic
behavior (i.e., IMD, t
potentiometer balances the resistor network (V
should equal V
mode input voltage is V
input (V
10 V/V.

ERR

is equal to the parallel combination of

N

V

DD

1µF

R

N

R

G

V

DD

R

N

R

G

at DC). The op amp’s common

REF

) appears at V

100 nF

100 nF

STR

CM=VIN

R

ISO

C

L

R

F

1µF

R

ISO

C

L

R

F

, t

and t

STL

/2. The error at the

with a noise gain of

OUT

R

R

ODR

L

V

L

V

V

OUT

L

V

OUT

L

). The

OUT

11.0 kΩ 500 Ω

V

IN

11.0 kΩ

100 kΩ

0.1% 25 turn

0.1%

V

DD

1µF

100 nF

MCP6V3X

249 Ω

1%

0.1%

100 kΩ

0.1%

V

REF=VDD

R

ISO

/3

0 Ω

V

OUT

C

L

R

L

20 pF open

V

L

FIGURE 1-6: Test Circuit for Dynamic Input Behavior.

DS25127A-page 6 © 2012 Microchip Technology Inc.

MCP6V31/1U

n

6

Representative Part

e

0

V

O

+85

C

6

p

e

0

V

O

85

C

6

e

0

V

O

I

8

2.0 TYPICAL PERFORMANCE CURVES

Note: The graphs and tables provided following this note are a statistical summary based on a limited number of

samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.

Note: Unless otherwise indicated, T

L=VDD

/2, RL=100kΩ to VL and CL = 20 pF.

V

=+25°C, VDD= +1.8V to 5.5V, VSS= GND, VCM=VDD/3, V

A

2.1 DC Input Precision

25%

42 Samples

= +25°C

T

A

= 1.8V and 5.5V

V

DD

20%

15%

10%

age of Occurrences

5%

Percent

0%

-8-7-6-5-4-3-2-1012345678

FIGURE 2-1: Input Offset Voltage.

35%

42 Samples
V

DD

30%

25%

20%

15%

age of Occurrences

10%

5%

Percent

0%

-50 -40 -30 -20 -10 0 10 20 30 40 50

FIGURE 2-2: Input Offset Voltage Drift.

Input Offset Voltage (μV)

= 1.8V and 5.5V

Input Offset Voltage Drift; TC1(nV/°C)

8

4

(μV)

2

oltag

ffset

-2

-4

Input

-6

-8

0.0

+125°C

°

+25°C

-40°C

0.5

1.0

1.5

2.0

Power Supply Voltage (V)

2.5

3.0

OUT=VDD

3.5

4.0

VCM= V

4.5

CML

5.0

/2,

5.5

FIGURE 2-4: Input Offset Voltage vs.
Power Supply Voltage with V

8

4

(μV)

2

oltag

ffset

-2

-4

Input

-6

-8

0.0

+125°C

+

°

+25°C

-40°C

0.5

1.0

1.5

2.0

Power Supply Voltage (V)

2.5

3.0

CM=VCML

VCM= V
Representative Part

3.5

4.0

4.5

CMH

5.0

.

5.5

FIGURE 2-5: Input Offset Voltage vs.
Power Supply Voltage with V

CM=VCMH

.

6.0

6.0

6.5

6.5

45%

42 Samples

= 1.8V and 5.5V

V

40%

DD

35%

30%

25%

20%

15%

tage of Occurrences

10%

5%

Perce

0%

-0.5 -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0.5
Input Offset Voltage's Quadratic Temp Co;

TC

(nV/°C2)

2

FIGURE 2-3: Input Offset Voltage Quadratic Temp. Co.

8

4

(μV)

2

oltag

ffset

nput

VDD= 1.8V

-2

-4

-6

-

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Power Supply Voltage (V)

Representative Part

VDD= 5.5V

FIGURE 2-6: Input Offset Voltage vs. Output Voltage.

© 2012 Microchip Technology Inc. DS25127A-page 7

MCP6V31/1U

6

Representative Part

e

0

V

O

+25

C

6

Representative Part

e

0

V

O

+25

C

s

35%

r

25%

a

e

s

60%

r

30%

a

e

VDD1.8V

145

135

S

CMRR

VDD=5.5V

Note: Unless otherwise indicated, T

=+25°C, VDD= +1.8V to 5.5V, VSS= GND, VCM=VDD/3, V

A

VL=VDD/2, RL=100kΩ to VL and CL = 20 pF.

8

4

(μV)

2

oltag

ffset

-2

-4

Input

-6

-8

-0.5 0.0 0.5 1.0 1.5 2.0 2.5

VDD= 1.8V

+125°C
+85°C

°

-40°C

Input Common Mode Voltage (V)

FIGURE 2-7: Input Offset Voltage vs.
Common Mode Voltage with V

8

4

(μV)

2

oltag

ffset

-2

-4

Input

-6

-8

-0.5

0.0

VDD= 5.5V

+125°C
+85°C

°

-40°C

0.5

1.0

1.5

2.0

Input Common Mode Voltage (V)

2.5

3.0

DD

3.5

=1.8V.

4.0

4.5

5.0

5.5

FIGURE 2-8: Input Offset Voltage vs.
Common Mode Voltage with V

DD

=5.5V.

6.0

OUT=VDD

50%

20 Samples

45%

40%

rence

30%

Occu

20%

ge of

15%

rcent

10%

P

= +25°C

T

A

5%

0%

-1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0
1/PSRR (μV/V)

/2,

FIGURE 2-10: PSRR.

90%

21 Samples

= +25°C

T

80%

70%

rence

1/A

OL

VDD= 5.5V

(μV/V)

50%

Occu

40%

ge of

20%

rcent
P

10%

0%

=

-0.5 -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0.5

FIGURE 2-11: DC Open-Loop Gain.

80%

21 Samples
T

= 25°C

A

70%

60%

50%

40%

30%

tage of Occurrences

20%

10%

Percen

0%

-1.6

-1.2

VDD= 5.5V

-0.8

-0.4

1/CMRR (μV/V)

FIGURE 2-9: CMRR.

0.0

0.4

VDD= 1.8V

0.8

1.2

1.6

160

155

150

B)

140

RR (d

130

RR, P

125

CM

120

115

110

-50 -25 0 25 50 75 100 125

VDD= 1.8V

Ambient Temperature (°C)

PSRR

FIGURE 2-12: CMRR and PSRR vs. Ambient Temperature.

DS25127A-page 8 © 2012 Microchip Technology Inc.

MCP6V31/1U

145

n

V

135

o

e

D

V

150

p

DD

0

e

s
u

I

OS

4000

p

VDD=5.5V

r

e

I

s

1000

u

A

r

100

e

100

s

1p

1.E

03

A

1m

M

1.E-08

u

+85

C

10n

p

p

Note: Unless otherwise indicated, T

=+25°C, VDD= +1.8V to 5.5V, VSS= GND, VCM=VDD/3, V

A

VL=VDD/2, RL=100kΩ to VL and CL = 20 pF.

160

155

150

(dB)

140

p Gai

130

n-Lo

125

C Op

120

115

110

-50 -25 0 25 50 75 100 125

VDD= 5.5V

= 1.8V

DD

Ambient Temperature (°C)

FIGURE 2-13: DC Open-Loop Gain vs. Ambient Temperature.

200

A)

100

ents (

50

t Curr

-50

, Offs

-100

t Bia

-150

Inp

-200

TA= +85°C

= 5.5V

0.0

0.5

1.0

1.5

-0.5

Common Mode Input Voltage (V)

2.0

2.5

I

B

3.0

3.5

4.0

4.5

5.0

5.5

6.0

FIGURE 2-14: Input Bias and Offset
Currents vs. Common Mode Input Voltage with
T

= +85°C.

A

OUT=VDD

10000

1n

VDD= 5.5V

)

1000

1n

ents (

t Cur

, Offs

10p

ut Bia

Inp

10

I

p

1

OS

I

B

25 35 45 55 65 75 85 95 105 115 125

Ambient Temperature (°C)

/2,

FIGURE 2-16: Input Bias and Offset
Currents vs. Ambient Temperature with
V

=+5.5V.

DD

1.E-02

10m

)

-

1.E-04

100μ

ude (

1.E-05

10μ

agnit

1.E-06

1μ

1.E-07

100n

rrent

1.E-09

1n

put C
In

1.E-10

100p

1.E-11

10

-1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0

+125°C

°

+25°C

-40°C

Input Voltage (V)

FIGURE 2-17: Input Bias Current vs. Input
Voltage (below V

SS

).

5000

TA= +125°C

A)

ents (

3000

2000

t Cur

1000

, Offs

t Bia

-

Inp

-2000

0

-0.5

B

I

OS

0.0

0.5

1.0

1.5

2.0

2.5

3.0

Common Mode Input Voltage (V)

3.5

4.0

4.5

5.0

5.5

6.0

FIGURE 2-15: Input Bias and Offset
Currents vs. Common Mode Input Voltage with
T

= +125°C.

A

© 2012 Microchip Technology Inc. DS25127A-page 9

MCP6V31/1U

0.3

g

0.0

o

m

H

p

V

r

VDDV

OH

V

V

10

V

u

4

u

o

10

C

35%

e

1 Wafer Lot

20%

f

t

5%

P

0

Note: Unless otherwise indicated, T

=+25°C, VDD= +1.8V to 5.5V, VSS= GND, VCM=VDD/3, V

A

VL=VDD/2, RL=100kΩ to VL and CL = 20 pF.

2.2 Other DC Voltages and Currents

0.4

e

Upper ( V

0.2

Vol ta

0.1

m (V)

Mode

mon

-0.1

eadro

ut Co

In

Lower (V

-0.2

-0.3

-0.4

-50 -25 0 25 50 75 100 125

)

CMH–VDD

)

CML–VSS

Ambient Temperature (°C)

FIGURE 2-18: Input Common Mode Voltage Headroom (Range) vs. Ambient Temperature.

1000

)

oom (

100

Head

oltage

tput
O

1

0.1 1 10

–

VOL–V

SS

Output Current Magnitude (V)

FIGURE 2-19: Output Voltage Headroom vs. Output Current.

1 Wafer Lot

VDD= 5.5V

= 1.8

DD

4.5

5.0

/2,

5.5

6.0

6.5

40

0.0

-40°C
+25°C
+85°C

+125°C

+125°C

+85°C
+25°C

-40°C

0.5

1.0

1.5

Power Supply Voltage (V)

30

20

10

0

-10

rt Circuit Current (mA)

-20

-30

Output Sh

-40

2.0

2.5

3.0

3.5

OUT=VDD

4.0

FIGURE 2-21: Output Short Circuit Current vs. Power Supply Voltage.

30

25

20

15

urrent (μA/amplifier)

5

Supply

0

1.5

2.0

+125°C

+85°C
+25°C

-40°C

2.5

3.0

3.5

Power Supply Voltage (V)

4.0

4.5

5.0

5.5

FIGURE 2-22: Supply Current vs. Power Supply Voltage.

12

RL= 25 k

11

10

9
8
7

VDD= 5.5V

6
5

t Headroom (mV)

3

Outp

2

VDD= 1.8V

1
0

-50 -25 0 25 50 75 100 125

VOL–V

Ambient Temperature (°C)

VDD–V

SS

OH

FIGURE 2-20: Output Voltage Headroom vs. Ambient Temperature.

40%

850 Samples

s

TA= +25°C

30%

rrenc

25%

Occu

15%

age o

10%

ercen

0%

1.101.121.141.161.181.201.221.241.261.281.3

POR Trip Voltage (V)

FIGURE 2-23: Power-on Reset Trip Voltage.

DS25127A-page 10 © 2012 Microchip Technology Inc.

MCP6V31/1U

R

Note: Unless otherwise indicated, T

=+25°C, VDD= +1.8V to 5.5V, VSS= GND, VCM=VDD/3, V

A

VL=VDD/2, RL=100kΩ to VL and CL = 20 pF.

1.6

1.4

1.2

1.0

0.8

0.6

Trip Voltage (V)

0.4

PO

0.2

0.0

-50 -25 0 25 50 75 100 125
Ambient Temperature (°C)

FIGURE 2-24: Power-on Reset Voltage vs. Ambient Temperature.

OUT=VDD

/2,

© 2012 Microchip Technology Inc. DS25127A-page 11

MCP6V31/1U

R

CMRR



180

10

n

n

O



180

10

n

n
h

d

h

h

Note: Unless otherwise indicated, T

=+25°C, VDD= +1.8V to 5.5V, VSS= GND, VCM=VDD/3, V

A

VL=VDD/2, RL=100kΩ to VL and CL = 20 pF.

2.3 Frequency Response

110

100

90

80

70

60

50

R, PSRR (dB)

40

CM

30

20

10

10 10k

1.E+01 1.E+02 1.E+03 1.E+04 1.E+05

100

Frequency (Hz)

FIGURE 2-25: CMRR and PSRR vs. Frequency.

70

60

50

40

30

20

-Loop Gain (dB)

0

Ope

-10

-20

1k 10k 1M100k

1.E+03 1.E+04 1.E+05 1.E+06

Frequency (Hz)

FIGURE 2-26: Open-Loop Gain vs.
Frequency with V

DD

=1.8V.

PSRR

| AOL|

VDD= 1.8V

= 20 pF

C

L

A

OL

0

-30

-60

-90

-120

-150

-

-210

-240

-270

100k1k

-Loop Phase (°)

Ope

OUT=VDD

700

600

500

400

300

width Product (kHz)

200

100

Gain Ban

0

-50 -25 0 25 50 75 100 125

PM

GBWP

Ambient Temperature (°C)

VDD= 5.5V

VDD= 1.8V

/2,

100

90

80

70

60

50

40

30

FIGURE 2-28: Gain Bandwidth Product and Phase Margin vs. Ambient Temperature.

5.0

5.5

100

90

80

70

60

50

40

30

6.0

700

600

500

400

300

dwidth Product (kHz)

200

100

Gain Ban

0

PM

2.0

2.5

VDD= 1.8V

3.0

GBWP

0.0

0.5

1.0

-0.5

1.5

Common Mode Input Voltage (V)

3.5

4.0

RF= 1 M

VDD= 5.5V

4.5

FIGURE 2-29: Gain Bandwidth Product and Phase Margin vs. Common Mode Input Voltage.

ase Margin (°)
P

ase Margin (°)
P

70

60

50

40

30

20

-Loop Gain (dB)

0

Ope

-10

-20

1k 10k 1M100k

1.E+03 1.E+04 1.E+05 1.E+06

Frequency (Hz)

| A

VDD= 5.5V
C

L

A

OL

|

L

= 20 pF

FIGURE 2-27: Open-Loop Gain vs.
Frequency with V

DD

=5.5V.

0

-30

-60

-90

-120

-150

-

-210

-240

-270

-Loop Phase (°)

Ope

700

600

500

400

300

dwidth Product (kHz)

200

100

Gain Ban

0

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

PM

GBWP

VDD= 1.8V

Output Voltage (V)

VDD= 5.5V

FIGURE 2-30: Gain Bandwidth Product and Phase Margin vs. Output Voltage.

100

90

80

70

60

50

40

30

ase Margin (°)
P

DS25127A-page 12 © 2012 Microchip Technology Inc.

MCP6V31/1U

o

o

i

g

1

t

-

x

0.1

Note: Unless otherwise indicated, T

=+25°C, VDD= +1.8V to 5.5V, VSS= GND, VCM=VDD/3, V

A

VL=VDD/2, RL=100kΩ to VL and CL = 20 pF.

1.E+05

100k

VDD= 1.8V

1.E+04

10k

1.E+03

1k

()

1.E+02

p Output Impedance

100

1.E+01

10

Closed-Lo

1.E+00

1

100 1k 10k 1M

1.E+02 1.E+03 1.E+04 1.E+05 1.E+06

G = 1 V/V
G = 11 V/V
G = 101 V/V

Frequency (Hz)

100k

FIGURE 2-31: Closed-Loop Output
Impedance vs. Frequency with V

1.E+05

100k

VDD= 5.5V

1.E+04

10k

1.E+03

1k

()

1.E+02

p Output Impedance

100

DD

=1.8V.

OUT=VDD

10

ng

e Sw

)

Vol t a

P
P

(V

Outpu

imum

Ma

VDD= 5.5V

VDD= 1.8V

1k 10k 1M100k

1.E+03 1.E+04 1.E+05 1.E+06

Frequency (Hz)

/2,

FIGURE 2-33: Maximum Output Voltage Swing vs. Frequency.

1.E+01

10

Closed-Lo

1.E+00

10

100 1k 100k 1M

1.E+02 1.E+03 1.E+04 1.E+05 1.E+06

G = 1 V/V
G = 11 V/V
G = 101 V/V

10k

Frequency (Hz)

FIGURE 2-32: Closed-Loop Output
Impedance vs. Frequency with V

DD

=5.5V.

© 2012 Microchip Technology Inc. DS25127A-page 13

MCP6V31/1U

10110

d

70

y

D

40

o

¥

o

10

n

V

CM

PK

(

10

m

p

0.1

(

10

m

p

V

5V

0.1

N

N

Note: Unless otherwise indicated, T

V

L=VDD

/2, RL=100kΩ to VL and CL = 20 pF.

=+25°C, VDD= +1.8V to 5.5V, VSS= GND, VCM=VDD/3, V

A

2.4 Input Noise and Distortion

3.5

= 1.8V

VDD= 5.5V

4.0

1000

100

1

f < 2 kHz

4.5

5.0

)

P-P

(μV

ni

E

Input Noise Voltage;

Integrate

5.5

6.0

1000

e

100

(nV/¥Hz)

ni

ise Voltage Density;

e

Input No

ni

VDD= 5.5V
V

DD

Eni(0 Hz to f)

1 10 100 1k 10k 100k

1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05

Frequency (Hz)

FIGURE 2-34: Input Noise Voltage Density and Integrated Input Noise Voltage vs. Frequency.

80

VDD= 1.8V

60

ensit

50

Hz)

ltage

(nV/

30

ise V

20

put N
I

0

0.0

0.5

1.0

1.5

2.0

2.5

-0.5

Common Mode Input Voltage (V)

3.0

FIGURE 2-35: Input Noise Voltage Density vs. Input Common Mode Voltage.

OUT=VDD

1000

GDM= 1 V/V

tone = 50 mVPK, f = 100 Hz

V

DD

)

PK

100

μV

, RTI

ectru

MD S

I

IMD tone at DC

100 Hz tone

1

VDD= 1.8V

=5.

DD

1 100 100k10k10 1k

1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05

Frequency (Hz)

FIGURE 2-37: Inter-Modulation Distortion
vs. Frequency with V

Disturbance

DD

(see Figure1-6).

VDD= 1.8V

(t)

ni

oise Voltage; e

(0.2 μV/div)

Input

0 102030405060708090100

NPBW = 10 Hz

NPBW = 1 Hz

Time (s)

FIGURE 2-38: Input Noise vs. Time with
1 Hz and 10 Hz Filters and V

DD

=1.8V.

/2,

1000

GDM= 1 V/V

)

PK

100

μV

, RTI

ectru

MD S

I

tone = 50 mV

1

1 100 100k10k10 1k

1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05

, f = 100 Hz

residual 100 Hz tone

VDD= 1.8V

= 5.5V

V

DD

Frequency (Hz)

FIGURE 2-36: Inter-Modulation Distortion
vs. Frequency with V

Disturbance (see

CM

1.4

VDD= 5.5V

1.2

1.0

(t)

ni

0.8

0.6

0.4

0.2

oise Voltage; e

0.0

(0.2 μV/div)

-0.2

-0.4

Input

-0.6

-0.8

0 102030405060708090100

NPBW = 10 Hz

NPBW = 1 Hz

Time (s)

FIGURE 2-39: Input Noise vs. Time with
1 Hz and 10 Hz Filters and V

DD

=5.5V.

Figure 1-6).

DS25127A-page 14 © 2012 Microchip Technology Inc.

MCP6V31/1U

202025

e

201015

e

V

VDD5.5V

T

O

V

OS

I

O

V

OS

O

V

t

V

Note: Unless otherwise indicated, T

=+25°C, VDD= +1.8V to 5.5V, VSS= GND, VCM=VDD/3, V

A

VL=VDD/2, RL=100kΩ to VL and CL = 20 pF.

2.5 Time Response

40

35

30

(μV)

oltag

ffset

5

0

nput

-5

-10
0 102030405060708090100

VDD= 1.8V

=

Temperature increased by
using heat gun for 5 seconds.

Time (s)

T

PCB

FIGURE 2-40: Input Offset Voltage vs. Time with Temperature Change.

6

G = 1

5

4

3

2

1

0

ffset Voltage (mV)

-1

-2

Input

-3

-4

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

POR Trip Point

Time (ms)

FIGURE 2-41: Input Offset Voltage vs. Time at Power Up.

80

60

40

0

-

-40

-60

-80

-100

-120

V

DD

/2,

VDD= 5.5V
G = 1

(°C)

rature

emp

PCB

OUT=VDD

80

70

60

50

40

oltage (10 mV/div)

30

20

Output

10

0

0 102030405060708090100

Time (μs)

FIGURE 2-43: Non-inverting Small Signal Step Response.

6

5

4

3

2

1

0

Supply Voltage (V)

-1

-2

Power

-3

-4

5.5

5.0

4.5

4.0

3.5

3.0

2.5

2.0

put Voltage (V)

1.5

Ou

1.0

0.5

0.0
0 50 100 150 200 250 300 350 400

Time (μs)

VDD= 5.5V
G = 1

FIGURE 2-44: Non-inverting Large Signal Step Response.

7

6

5

4

3

utput Voltage (V)

2

1

Input,

0

-1
012345678910

V

IN

V

OUT

Time (ms)

VDD= 5.5V
G = 1

FIGURE 2-42: The MCP6V31/1U Family Shows No Input Phase Reversal with Overdrive.

90

80

70

60

50

40

30

oltage (10 mV/div)

20

10

Output

0

-10

0 102030405060708090100

VDD= 5.5V
G = -1

Time (μs)

FIGURE 2-45: Inverting Small Signal Step Response.

© 2012 Microchip Technology Inc. DS25127A-page 15

MCP6V31/1U

t

0.10

e

2

2

p

VDD=5.5V

1.E-04

v

100μ

Note: Unless otherwise indicated, T

=+25°C, VDD= +1.8V to 5.5V, VSS= GND, VCM=VDD/3, V

A

VL=VDD/2, RL=100kΩ to VL and CL = 20 pF.

5.5

5.0

4.5

4.0

3.5

3.0

2.5

2.0

put Voltage (V)

1.5

Ou

1.0

0.5

0.0
0 50 100 150 200 250 300 350 400

VDD= 5.5V
G = -1

Time (μs)

FIGURE 2-46: Inverting Large Signal Step Response.

0.30

0.25

Falling Edge

0.20

0.15

w Rate (V/μs)

Sl

0.05

Rising Edge

0.00

-50 -25 0 25 50 75 100 125
Ambient Temperature (°C)

VDD= 5.5V

VDD= 1.8V

FIGURE 2-47: Slew Rate vs. Ambient Temperature.

OUT=VDD

7

6

ut Voltage (V)

Out

-1

5

4

3

1

0

V

OUT

G = -10 V/V

G V

0 100 200 300 400 500 600 700 800 900 10001100

0.5V Overdrive

IN

Time (100 μs/div)

G V

IN

V

/2,

7

6

5

4

3

ltage × G (1 V/div)

OUT

1

Input Vo

0

-1

FIGURE 2-48: Output Overdrive Recovery vs. Time with G = -10 V/V.

1.E-02

10m

0.5V Input Overdrive

VDD= 1.8V

1.E-03

1m

t

, high

ODR

e Recovery Time (s)

t

, low

ODR

Overdri

1.E-05

10μ

1 10 100 1000

Inverting Gain Magnitude (V/V)

VDD= 5.5V

FIGURE 2-49: Output Overdrive Recovery Time vs. Inve rting Gain.

DS25127A-page 16 © 2012 Microchip Technology Inc.

3.0 PIN DESCRIPTIONS

Descriptions of the pins are listed in Table 3-1.

TABLE 3-1: PIN FUNCTION TABLE

MCP6V31 MCP6V31U

SOT-23 SOT-23, SC-70

14V

22V

31V

43V

55V

3.1 Analog Outputs

MCP6V31/1U

Symbol Description

OUT

SS

+ Non-inverting Input (op amp A)

IN

– Inverting Input (op amp A)

IN

DD

Output (op amp A)

Negative Power Supply

Positive Power Supply

The analog output pins (V
voltage sources.

) are low-impedance

OUT

3.2 Analog Inputs

The non-inverting and inverting inputs (VIN+, VIN–, …)
are high-impedance CMOS inputs with low bias
currents.

3.3 Power Supply Pins

The positive power supply (VDD) is 1.8V to 5.5V higher
than the negative power supply (V
operation, the other pins are between V

Typically, these parts are used in a single (positive)
supply configuration. In this case, VSS is connected to
ground and V
need bypass capacitors.

is connected to the supply. VDD will

DD

). For normal

SS

and VDD.

SS

© 2012 Microchip Technology Inc. DS25127A-page 17

MCP6V31/1U

NOTES:

DS25127A-page 18 © 2012 Microchip Technology Inc.

MCP6V31/1U

4.0 APPLICATIONS

The MCP6V31/1U family of zero-drift op amps is
manufactured using Microchip’s state of the art CMOS
process. It is designed for precision applications with
requirements for small packages and low power. Its low
supply voltage and low quiescent current make the
MCP6V31/1U devices ideal for battery-powered
applications.

4.1 Overview of Zero-Drif t Operation

Figure 4-1 shows a simplified diagram of the

MCP6V31/1U zero-drift op amps. This diagram will be
used to explain how slow voltage errors are reduced in
this architecture (much better V
CMRR, PSRR, A

VIN+

VIN–

and 1/f noise).

OL

V

OUT

Main
Amp.

, ∆VOS/∆TA (TC1),

OS

Output

Buffer

NC

Low-Pass

Filter

V

REF

The Low-Pass Filter reduces high frequency content,
including harmonics of the Chopping Clock.

The Output Buffer drives external loads at the V
(V

is an internal reference voltage).

REF

The Oscillator runs at f
divided by two, to produce the Chopping Clock rate of

=100kHz.

f

CHOP

The internal POR part starts the part in a known good
state, protecting against power supply brown-outs.

The Digital Control block controls switching and POR
events.

= 200 kHz. Its output is

OSC1

OUT

pin

4.1.2 CHOPPING ACTION

Figure 4-2 shows the amplifier connections for the first

phase of the Chopping Clock and Figure 4-3 shows
them for the second phase. Its slow voltage errors
alternate in polarity, making the average error small.

VIN+

VIN–

Main

Amp.

Aux.

Amp.

NC

Low-Pass

Filter

Chopper

Input

Switches

Oscillator

Aux.

Amp.

Digital Control

Chopper

Output

Switches

POR

FIGURE 4-1: Simplified Zero-Drift Op Amp Functional Diagram.

4.1.1 BUILDING BLOCKS

The Main Amplifier is designed for high gain and
bandwidth, with a differential topology. Its main input
pair (+ and - pins at the top left) is used for the higher
frequency portion of the input signal. Its auxiliary input
pair (+ and - pins at the bottom left) is used for the low
frequency portion of the input signal and corrects the
op amp’s input offset voltage. Both inputs are added
together internally.

The Auxiliary Amplifier, Chopper Input Switches and
Chopper Output Switches provide a high DC gain to the
input signal. DC errors are modulated to higher
frequencies, while white noise is modulated to low
frequency.

FIGURE 4-2: First Chopping Clock Phase; Equivalent Amplifier Diagram.

VIN+

V

–

IN

Main

Amp.

Aux.

Amp.

NC

Low-Pass

Filter

FIGURE 4-3: Second Chopping Clock Phase; Equivalent Amplifier Diagram.

© 2012 Microchip Technology Inc. DS25127A-page 19

MCP6V31/1U

4.1.3 INTERMODULATION DISTORTION
(IMD)

These op amps will show intermodulation distortion
(IMD) products when an AC signal is present.

The signal and clock can be decomposed into sine
wave tones (Fourier series components). These tones
interact with the zero-drift circuitry’s non-linear
response to produce IMD tones at sum and difference
frequencies. Each of the square wave clock’s
harmonics has a series of IMD tones centered on it.
See Figure 2-36 and Figure 2-37.

V

DD

VIN+

V

SS

Bond

Pad

Bond

Pad

Bond

Pad

Input

Stage

Bond

Pad

VIN–

4.2 Other Functional Blocks

4.2.1 RAIL-TO-RAIL INPUTS

The input stage of the MCP6V31/1U op amps uses two
differential CMOS input stages in parallel. One
operates at low common mode input voltage (V
which is approximately equal to V
normal operation) and the other at high V
topology, the input operates with V
and down to V

– 0.15V, at +25°C (see Figure 2-18).

SS

The input offset voltage (V
V

CM=VSS

– 0.15V and VDD+ 0.2V to ensure proper

+ and VIN– in

IN

CM

up to VDD+0.2V,

CM

) is measured at

OS

operation.

The transition between the input stages occurs when

≈ VDD–0.9V (see Figure 2-7 and Figure 2-8). For

V

CM

the best distortion and gain linearity, with non-inverting
gains, avoid this region of operation.

4.2.1.1 Phase Reversal

The input devices are designed to not exhibit phase
inversion when the input pins exceed the supply
voltages. Figure 2-42 shows an input voltage
exceeding both supplies with no phase inversion.

4.2.1.2 Input Voltage Limits

In order to prevent damage and/or improper operation
of these amplifiers, the circuit must limit the voltages at
the input pins (see Section 1.1, Absolute Maximum

Ratings †). This requirement is independent of the cur-

rent limits discussed later on.

The ESD protection on the inputs can be depicted as
shown in Figure 4-4. This structure was chosen to
protect the input transistors against many (but not all)
overvoltage conditions, and to minimize input bias
current (I

).

B

CM

. With this

FIGURE 4-4: Simplified Analog Input ESD Structures.

The input ESD diodes clamp the inputs when they try
to go more than one diode drop below V

,

clamp any voltages that well above V
breakdown voltage is high enough to allow normal

. They also

SS

; their

DD

operation, but not low enough to protect against slow
overvoltage (beyond V

) events. Very fast ESD

DD

events (that meet the spec) are limited so that damage
does not occur.

In some applications, it may be necessary to prevent
excessive voltages from reaching the op amp inputs;

Figure 4-5 shows one approach to protecting these

inputs. D

and D2 may be small signal silicon diodes,

1

Schottky diodes for lower clamping voltages or diode
connected FETs for low leakage.

V

DD

U

D

1

V

1

D

2

V

2

1

MCP6V3X

V

OUT

FIGURE 4-5: Protecting the Analog Inputs Against High Voltages.

DS25127A-page 20 © 2012 Microchip Technology Inc.

MCP6V31/1U

4.2.1.3 Input Current Limits

In order to prevent damage and/or improper operation
of these amplifiers, the circuit must limit the currents
into the input pins (see Section 1.1, Absolute Maximum

Ratings †). This requirement is independent of the volt-

age limits discussed previously.

Figure 4-6 shows one approach to protecting these

inputs. The resistors R
current in or out of the input pins (and into D
The diode currents will dump onto V

D

1

V

1

R

1

V

2

R

2

min(R1,R2)>

min(R1,R2)>

and R2 limit the possible

1

.

DD

V

DD

U

1

MCP6V3X

D

2

VSS–min(V1,V2)

2mA

max(V1,V2)–V

2mA

V

DD

and D2).

1

OUT

FIGURE 4-6: Protecting the Analog Inputs Against High Currents.

It is also possible to connect the diodes to the left of
resistors R
the diodes D

and R2. In this case, the currents through

1

and D2 need to be limited by some other

1

mechanism. The resistors then serve as in-rush current
limiters; the DC current into the input pins (VIN+ and

–) should be very small.

V

IN

A significant amount of current can flow out of the
inputs (through the ESD diodes) when the common
mode voltage (V

) is below ground (VSS); see

CM

Figure 2-17.

4.2.2 RAIL-TO-RAIL OUTPUT

The output voltage range of the MCP6V31/1U zero-drift
op amps is V
(maximum) when R
and V

DD

for more information.

This op amp is designed to drive light loads; use
another amplifier to buffer the output from heavy loads.

–20mV (minimum) and VSS+20mV

DD

=10kΩ is connected to VDD/2

L

= 5.5V. Refer to Figure 2-19 and Figure 2-20

4.3 Application Tips

4.3.1 INPUT OFFSET VOLTAGE OVER
TEMPERATURE

Table 1-1 gives both the linear and quadratic

temperature coefficients (TC
voltage. The input offset voltage, at any temperature in
the specified range, can be calculated as follows:

EQUATION 4-1:

VOSTA() V

Where:

∆T=T

–25°C

A

VOS(TA) = input offset voltage at T

V

= input offset voltage at +25°C

OS

= linear temperature coefficient

TC

1

TC

= quadratic temperature coefficient

2

4.3.2 DC GAIN PLOTS

Figures 2-9 to 2-11 are histograms of the reciprocals

(in units of µV/V) of CMRR, PSRR and A
respectively. They represent the change in input offset
voltage (V
voltage (V
voltage (V

The 1/A

) with a change in common mode input

OS

), power supply voltage (VDD) and output

CM

).

OUT

histogram is centered near 0 µV/V because

OL

the measurements are dominated by the op amp’s
input noise. The negative values shown represent

noise and tester limitations, not unstable behavior.

Production tests make multiple V
which validates an op amp's stability; an unstable part
would show greater VOS variability, or the output would
stick at one of the supply rails.

4.3.3 OFFSET AT POWER UP

When these parts power up, the input offset (VOS)
starts at its uncorrected value (usually less than
±5 mV). Circuits with high DC gain can cause the
output to reach one of the two rails. In this case, the
time to a valid output is delayed by an output overdrive
time (like t

).

t

STR

It can be simple to avoid this extra startup time.
Reducing the gain is one method. Adding a capacitor
across the feedback resistor (R

), in addition to the startup time (like

ODR

and TC2) of input offset

1

TC

Δ

TTC

++=

OS

1

measurements,

OS

) is another method.

F

2

Δ

T

2

A

OL

,

© 2012 Microchip Technology Inc. DS25127A-page 21

MCP6V31/1U

m

4.3.4 SOURCE RESISTANCES

The input bias currents have two significant
components; switching glitches that dominate at room
temperature and below, and input ESD diode leakage
currents that dominate at +85°C and above.

Make the resistances seen by the inputs small and
equal. This minimizes the output offset caused by the
input bias currents.

The inputs should see a resistance on the order of 10 Ω
to 1 kΩ at high frequencies (i.e., above 1 MHz). This
helps minimize the impact of switching glitches, which
are very fast, on overall performance. In some cases, it
may be necessary to add resistors in series with the
inputs to achieve this improvement in performance.

Small input resistances may be needed for high gains.
Without them, parasitic capacitances might cause
positive feedback and instability.

4.3.5 SOURCE CAPACITANCE

The capacitances seen by the two inputs should be
small and matched. The internal switches connected to
the inputs dump charges on these capacitors; an offset
can be created if the capacitances do not match. Large
input capacitances and source resistances, together
with high gain, can lead to positive feedback and
instability.

Figure 4-8 gives recommended R

values for

ISO

different capacitive loads and gains. The x-axis is the
load capacitance (CL). The y-axis is the resistance

).

(R

ISO

is the circuit’s noise gain. For non-inverting gains,

G

N

and the Signal Gain are equal. For inverting gains,

G

N

G

is 1+|Signal Gain| (e.g., -1 V/V gives GN= +2 V/V).

N

1.E+04

10k

()

ISO

1.E+03

1k

mended R

Reco

1.E+02

100

GN= 1 GN= 10 GN= 100

10p 100p 1n 10n 100n 1μ

1.E-11 1.E-10 1.E-09 1.E-08 1.E-07 1.E-06

Capacitive Load (F)

FIGURE 4-8: Recommended R

RL||(RF+ RG)  100 k

ISO

values

for Capacitive Loads.

After selecting R
resulting frequency response peaking and step
response overshoot. Modify R
response is reasonable. Bench evaluation is helpful.

for your circuit, double check the

ISO

's value until the

ISO

4.3.6 CAPACITIVE LOADS

Driving large capacitive loads can cause stability
problems for voltage feedback op amps. As the load
capacitance increases, the feedback loop’s phase
margin decreases and the closed-loop bandwidth is
reduced. This produces gain peaking in the frequency
response, with overshoot and ringing in the step
response. These zero-drift op amps have a different
output impedance than most op amps, due to their
unique topology.

When driving a capacitive load with these op amps, a
series resistor at the output (R

in Figure 4-7)

ISO

improves the feedback loop’s phase margin (stability)
by making the output load resistive at higher
frequencies. The bandwidth will be generally lower
than the bandwidth with no capacitive load.

R

ISO

C

U

1

V

OUT

L

MCP6V3X

FIGURE 4-7: Output Resistor, R

ISO

,

Stabilizes Capacitive Loads.

4.3.7 STABILIZING OUTPUT LOADS

This family of zero-drift op amps has an output
impedance (Figure 2-31 and Figure 2-32) that has a
double zero when the gain is low. This can cause a
large phase shift in feedback networks that have low
impedance near the part’s bandwidth. This large phase
shift can cause stability problems.

Figure 4-9 shows that the load on the output is

(R

L+RISO

)||(RF+RG), where R

is before the load

ISO

(like Figure 4-7). This load needs to be large enough to
maintain performance; it should be at least 10 kΩ.

R

G

R

F

R

L

U

1

V

OUT

C

L

MCP6V3X

FIGURE 4-9: Output Load.

DS25127A-page 22 © 2012 Microchip Technology Inc.

MCP6V31/1U

4.3.8 GAIN PEAKING

Figure 4-10 shows an op amp circuit that represents

non-inverting amplifiers (V
the input) or inverting amplifiers (V
and V

is the input). The capacitances CN and CG rep-

M

is a DC voltage and VP is

M

is a DC voltage

P

resent the total capacitance at the input pins; they
include the op amp’s common mode input capacitance

), board parasitic capacitance and any capacitor

(C

CM

placed in parallel. The capacitance C

represents the

FP

parasitic capacitance coupling the output and non­inverting input pins.

C

N

R

V

N

P

C

FP

U

1

MCP6V3X

V

M

R

G

R

F

C

G

V

OUT

FIGURE 4-10: Amplifier with Parasitic Capacitance.

CG acts in parallel with RG (except for a gain of +1 V/V),
which causes an increase in gain at high frequencies.
CG also reduces the phase margin of the feedback
loop, which becomes less stable. This effect can be
reduced by either reducing C

and RN form a low-pass filter that affects the signal

C

N

at V

. This filter has a single real pole at 1/(2πRNCN).

P

The largest value of R

F

on noise gain (see G

Loads), C

approximate limit for R

and the open-loop gain’s phase shift. An

G

F

or RF||RG.

G

that should be used depends

in Section 4.3.6, Capacitive

N

is:

EQUATION 4- 2:

RF10 k

()

Ω

12 pF

--------------×G
C

Some applications may modify these values to reduce
either output loading or gain peaking (step response
overshoot).

At high gains, R

needs to be small, in order to prevent

N

positive feedback and oscillations. Large C
can also help.

2

×≤

N

G

values

N

4.3.9 REDUCING UNDESIRED NOISE
AND SIGNALS

Reduce undesired noise and signals with:

• Low bandwidth signal filters:

- Minimizes random analog noise

- Reduces interfering signals

• Good PCB layout techniques:

- Minimizes crosstalk

- Minimizes parasitic capacitances and
inductances that interact with fast switching
edges

• Good power supply design:

- Isolation from other parts

- Filtering of interference on supply line(s)

4.3.10 SUPPLY BYPASSING AND
FILTERING

With this family of operational amplifiers, the power
supply pin (V

for single supply) should have a local

DD

bypass capacitor (i.e., 0.01 µF to 0.1 µF) within 2 mm
of the pin for good high-frequency performance.

These parts also need a bulk capacitor (i.e., 1 µF or
larger) within 100 mm to provide large, slow currents.
This bulk capacitor can be shared with other low noise,
analog parts.

In some cases, high-frequency power supply noise
(e.g., switched mode power supplies) may cause
undue intermodulation distortion, with a DC offset shift;
this noise needs to be filtered. Adding a resistor into the
supply connection can be helpful.

4.3.11 PCB DESIGN FOR DC PRECISION

In order to achieve DC precision on the order of ±1 µV,
many physical errors need to be minimized. The design
of the Printed Circuit Board (PCB), the wiring, and the
thermal environment have a strong impact on the
precision achieved. A poor PCB design can easily be
more than 100 times worse than the MCP6V31/1U op
amps’ minimum and maximum specifications.

4.3.11.1 PCB Layout

Any time two dissimilar metals are joined together, a
temperature dependent voltage appears across the
junction (the Seebeck or thermojunction effect). This
effect is used in thermocouples to measure
temperature. The following are examples of
thermojunctions on a PCB:

• Components (resistors, op amps, …) soldered to

a copper pad

• Wires mechanically attached to the PCB

• Jumpers

• Solder joints

•PCB vias

© 2012 Microchip Technology Inc. DS25127A-page 23

MCP6V31/1U

Typical thermojunctions have temperature to voltage
conversion coefficients of 1 to 100 µV/°C (sometimes
higher).

Microchip’s AN1258 (“Op Amp Precision Design: PCB
Layout Techniques”) contains in-depth information on

PCB layout techniques that minimize thermojunction
effects. It also discusses other effects, such as
crosstalk, impedances, mechanical stresses and
humidity.

4.3.11.2 Crosstalk

DC crosstalk causes offsets that appear as a larger
input offset voltage. Common causes include:

• Common mode noise (remote sensors)

• Ground loops (current return paths)

• Power supply coupling

Interference from the mains (usually 50 Hz or 60 Hz),
and other AC sources, can also affect the DC
performance. Non-linear distortion can convert these
signals to multiple tones, including a DC shift in voltage.
When the signal is sampled by an ADC, these AC
signals can also be aliased to DC, causing an apparent
shift in offset.

To reduce interference:

- Keep traces and wires as short as possible

- Use shielding

- Use ground plane (at least a star ground)

- Place the input signal source near to the DUT

- Use good PCB layout techniques

- Use a separate power supply filter (bypass
capacitors) for these zero-drift op amps

4.3.11.3 Miscellaneous Effects

Keep the resistances seen by the input pins as small
and as near to equal as possible, to minimize bias­current-related offsets.

Make the (trace) capacitances seen by the input pins
small and equal. This is helpful in minimizing switching
glitch-induced offset voltages.

Bending a coax cable with a radius that is too small
causes a small voltage drop to appear on the center
conductor (the triboelectric effect). Make sure the
bending radius is large enough to keep the conductors
and insulation in full contact.

Mechanical stresses can make some capacitor types
(such as some ceramics) to output small voltages. Use
more appropriate capacitor types in the signal path and
minimize mechanical stresses and vibration.

Humidity can cause electrochemical potential voltages
to appear in a circuit. Proper PCB cleaning helps, as
does the use of encapsulants.

4.4 Typical Applications

4.4.1 WHEATSTONE BRIDGE

Many sensors are configured as Wheatstone bridges.
Strain gauges and pressure sensors are two common
examples. These signals can be small and the
common mode noise large. Amplifier designs with high
differential gain are desirable.

Figure 4-11 shows how to interface to a Wheatstone

bridge with a minimum of components. Because the
circuit is not symmetric, the ADC input is single ended,
and there is a minimum of filtering, the CMRR is good
enough for moderate common mode noise.

0.2R

0.2R

N

U

G

0.01C

2.00 MΩ

1

2.00 MΩ10.0 kΩ

100R

10 nF

R

F

R

F

10 nF

1kΩ

U

1

MCP6V31

1.00 kΩ

100 nF

ADC

V

DD

ADC

V

DD

) is

W

V

DD

RR

RR

FIGURE 4-11: Simp le Design .

4.4.2 RTD SENSOR

The ratiometric circuit in Figure 4-12 conditions a two-
wire RTD, for applications with a limited temperature
range. U1 acts a difference amplifier, with a low
frequency pole. The sensor’s wiring resistance (R
corrected in firmware. Failure (open) of the RTD is
detected by an out-of-range voltage.

V

DD

R

T

34.8 kΩ

R

W

R

RTD

100Ω

R

W

R

B

4.99 kΩ

R

10.0 kΩ

MCP6V31

R

1.0 µF

FIGURE 4-12: RTD Sensor.

DS25127A-page 24 © 2012 Microchip Technology Inc.

4.4.3 OFFSET VOLTAGE CORRECTION

Figure 4-13 shows MCP6V31 (U2) correcting the input

offset voltage of another op amp (U
integrate the offset error seen at U1’s input; the
integration needs to be slow enough to be stable (with
the feedback provided by R1 and R3). R4 and R
attenuate the integrator’s output; this shifts the
integrator pole down in frequency.

). R2 and C

1

MCP6V31/1U

2

5

V

IN

VDD/2

R

1

R

2

C

R

2

R

2

4

R

U

2

5

R

VDD/2

3

V

U

1

MCP6XXX

OUT

MCP6V31

FIGURE 4-13: Offset Correction.

4.4.4 PRECISION COMPARATOR

Use high gain before a comparator to improve the
latter’s performance. Do not use MCP6V31/1U as a
comparator by itself; the VOS correction circuitry does
not operate properly without a feedback loop.

U

1

V

IN

VDD/2

R

1

R

2

MCP6V31

R

3

R

4

R

5

V

OUT

U

2

MCP6541

FIGURE 4-14: Precision Comparator.

© 2012 Microchip Technology Inc. DS25127A-page 25

MCP6V31/1U

NOTES:

DS25127A-page 26 © 2012 Microchip Technology Inc.

MCP6V31/1U

5.0 DESIGN AIDS

Microchip provides the basic design aids needed for
the MCP6V31/1U family of op amps.

5.1 SPICE Macro Model

The latest SPICE macro model for the MCP6V31/1U
op amps is available on the Microchip web site at

www.microchip.com. This model is intended to be an

initial design tool that works well in the op amp’s linear
region of operation over the temperature range. See
the model file for information on its capabilities.

Bench testing is a very important part of any design and
cannot be replaced with simulations. Also, simulation
results using this macro model need to be validated by
comparing them to the data sheet specifications and
characteristic curves.

5.2 FilterLab® Software

Microchip’s FilterLab® software is an innovative
software tool that simplifies analog active filter (using
op amps) design. Available at no cost from the
Microchip web site at www.microchip.com/filterlab, the
FilterLab
of the filter circuit with component values. It also
outputs the filter circuit in SPICE format, which can be
used with the macro model to simulate actual filter
performance.

®

design tool provides full schematic diagrams

5.4 Analog Demonstration and Evaluation Boards

Microchip offers a broad spectrum of Analog Demon­stration and Evaluation Boards that are designed to
help customers achieve faster time to market. For a
complete listing of these boards and their correspond­ing user’s guides and technical information, visit the
Microchip web site at www.microchip.com/analog

tools.

Some boards that are especially useful are:

• MCP6V01 Thermocouple Auto-Zeroed Reference

Design (P/N MCP6V01RD-TCPL)

• MCP6XXX Amplifier Evaluation Board 1 (P/N

DS51667)

• MCP6XXX Amplifier Evaluation Board 2 (P/N

DS51668)

• MCP6XXX Amplifier Evaluation Board 3 (P/N

DS51673)

• MCP6XXX Amplifier Evaluation Board 4 (P/N

DS51681)

• Active Filter Demo Board Kit (P/N DS51614)

• 8-Pin SOIC/MSOP/TSSOP/DIP Evaluation Board

(P/N SOIC8EV)

• 14-Pin SOIC/TSSOP/DIP Evaluation Board (P/N

SOIC14EV)

5.5 Application Notes

5.3 Microchip Advanced Part Selector (MAPS)

MAPS is a software tool that helps efficiently identify
Microchip devices that fit a particular design require­ment. Available at no cost from the Microchip web site
at www.microchip.com/maps, MAPS is an overall
selection tool for Microchip’s product portfolio that
includes Analog, Memory, MCUs and DSCs. Using this
tool, a customer can define a filter to sort features for a
parametric search of devices and export side-by-side
technical comparison reports. Helpful links are also
provided for Data Sheets, Purchase and Sampling of
Microchip parts.

The following Microchip Application Notes are
available on the Microchip web site at www.microchip.

com/appnotes and are recommended as supplemental

reference resources.

ADN003: “Select the Right Operational Amplifier for
your Filtering Circuits” , DS21821

AN722: “Operational Amplifier Topologies and DC
Specifications”, DS00722

AN723: “Operational Amplifier AC Specifications and
Applications”, DS00723

AN884: “Driving Capacitive Loads With Op Amps”,

DS00884

AN990: “Analog Sensor Conditioning Circuits – An
Overview”, DS00990

AN1177: “Op Amp Precision Design: DC Errors”,

DS01177

AN1228: “Op Amp Precision Design: Random Noise”,

DS01228

AN1258: “Op Amp Precision Design: PCB Layout
Techniques”, DS01258

These application notes and others are listed in the
design guide:

“Signal Chain Design Guide”, DS21825

© 2012 Microchip Technology Inc. DS25127A-page 27

MCP6V31/1U

NOTES:

DS25127A-page 28 © 2012 Microchip Technology Inc.

6.0 PACKAGING INFORMATION

6.1 Package Marking Information

MCP6V31/1U

5-Lead SC70 (MCP6V31U)

Device Code

MCP6V31UT-E/LT DKNN

Note: Applies to 5-Lead SC-70.

5-Lead SOT-23 (MCP6V31, MCP6V31U)

MCP6V31T-E/OT 2BNN

MCP6V31UT-E/OT 2ENN

Note: Applies to 5-Lead SOT-23.

Device Code

Example

Example

:

:

DK25

2B25

Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code

3

e

Pb-free JEDEC designator for Matte Tin (Sn)

* This package is Pb-free. The Pb-free JEDEC designator ( )

can be found on the outer packaging for this package.

Note: In the event the full Microchip part number cannot be marked on one line, it will

be carried over to the next line, thus limiting the number of available
characters for customer-specific information.

© 2012 Microchip Technology Inc. DS25127A-page 29

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/HDG7KLFNQHVV F  ± 

1RWHV

 'LPHQVLRQV'DQG(GRQRWLQFOXGHPROGIODVKRUSURWUXVLRQV0ROGIODVKRUSURWUXVLRQVVKDOOQRWH[FHHGPPSHUVLGH
 'LPHQVLRQLQJDQGWROHUDQFLQJSHU$60(<0

%6& %DVLF'LPHQVLRQ7KHRUHWLFDOO\H[DFWYDOXHVKRZQZLWKRXWWROHUDQFHV

/HDG:LGWK E  ± 

0LFURFKLS 7HFKQRORJ\ 'UDZLQJ &%

DS25127A-page 32 © 2012 Microchip Technology Inc.

MCP6V31/1U

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

© 2012 Microchip Technology Inc. DS25127A-page 33

MCP6V31/1U

NOTES:

DS25127A-page 34 © 2012 Microchip Technology Inc.

APPENDIX A: REVISION HISTORY

Revision A (March 2012)

• Original Release of this Document.

MCP6V31/1U

© 2012 Microchip Technology Inc. DS25127A-page 35

MCP6V31/1U

NOTES:

DS25127A-page 36 © 2012 Microchip Technology Inc.

MCP6V31/1U

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

PART NO. –X /XX

Device

T

Tape and Reel

PackageTemperature

Range

Device: MCP6V31T Single Op Amp (Tape and Reel) (SOT-23)

Temperature Range: E = -40°C to +125°C

MCP6V31UT Single Op Amp (Tape and Reel)

(SC-70, SOT-23)

Examples:

a) MCP6V31T-E/OT: Tape and Reel,

a) MCP6V31UT-E/LT: Tape and Reel

b) MCP6V31UT-E/OT: Tape and Reel,

Extended temperature,
5LD SOT-23 package

Extended temperature,
5LD SC70 package

Extended temperature,
5LD SOT-23 package

Package: LT = Plastic Package (SC-70), 5-lead

OT = Plastic Small Outline Transistor (SOT-23), 5-lead

© 2012 Microchip Technology Inc. DS25127A-page 37

MCP6V31/1U

NOTES:

DS25127A-page 38 © 2012 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, dsPIC,
K

EELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,

32

logo, rfPIC and UNI/O are registered trademarks of

PIC
Microchip Technology Incorporated in the U.S.A. and other
countries.

FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MXDEV, MXLAB, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, chipKIT,
chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net,
dsPICworks, dsSPEAK, ECAN, ECONOMONITOR,
FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP,
Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB,
MPLINK, mTouch, Omniscient Code Generation, PICC,
PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE,
rfLAB, Select Mode, Total Endurance, TSHARC,
UniWinDriver, WiperLock and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.

SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.

All other trademarks mentioned herein are property of their
respective companies.

© 2012, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.

Printed on recycled paper.

ISBN: 978-162076-154-0

QUALITY MANAGEMENT SYSTEM

CERTIFIED BY DNV

== ISO/TS 16949 ==

Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.

®

MCUs and dsPIC® DSCs, KEELOQ

®

code hopping

© 2012 Microchip Technology Inc. DS25127A-page 39

Worldwide Sales and Service

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11/29/11

DS25127A-page 40 © 2012 Microchip Technology Inc.