Datasheet MCP6V11, MCP6V11U Datasheet

MCP6V11/1U

7.5 µA, 80 kHz Zero-Drift Op Amps

Features

• High DC Precision:

-V

Drift: ±50 nV/°C (maximum)

OS

-VOS: ±8 µV (maximum)

-AOL: 112 dB (minimum, VDD=5.5V)

- PSRR: 118 dB (minimum, V

- CMRR: 119 dB (minimum, VDD=5.5V) : 2.1 µV

-E

ni

-E

: 0.67 µV

ni

• Low Power and Supply Voltages:

-IQ: 7.5 µA/amplifier (typical)

- Wide Supply Voltage Range: 1.6V to 5.5V

• Small Packages

- Singles in SC70, SOT-23

•Easy to Use:

- Rail-to-Rail Input/Output

- Gain Bandwidth Product: 80 kHz (typical)

- Unity Gain Stable

• Extended Temperature Range: -40°C to +125°C

(typical), f = 0.1 Hz to 10 Hz

P-P

(typical), f = 0.01 Hz to 1 Hz

P-P

DD

=5.5V)

Typical Applications

• Portable Instrumentation

• Sensor Conditioning

• Temperature Measurement

• DC Offset Correction

• Medical Instrumentation

Design Aids

• SPICE Macro Models

•FilterLab

• Microchip Advanced Part Selector (MAPS)

• Analog Demonstration and Evaluation Boards

• Application Notes

®

Software

Description

The Microchip Technology Inc. MCP6V11/1U family of operational amplifiers provides input offset voltage correction for very low offset and offset drift. These are low power devices, with a gain bandwidth product of 80 kHz (typical). They are unity gain stable, have no 1/f noise, and have good Power Supply Rejection Ratio (PSRR) and Common Mode Rejection Ratio (CMRR). These products operate with a single supply voltage as low as 1.6V, while drawing 7.5 µA/amplifier (typical) of quiescent current.

The Microchip Technology Inc. MCP6V11/1U op amps are offered in single (MCP6V11 and MCP6V11U) packages. They were designed using an advanced CMOS process.

Package Types

V

OUT

V

VIN+

SS

1

2 3

MCP6V11

SOT-23

5

4

V

DD

VIN–

MCP6V11U

SC70, SOT-23

VIN+

1

V

2

SS

V

–

3

IN

V

5

DD

V

4

OUT

Typical Application Circuit

R

V

IN

VDD/2

1

R

2

C

R

2

Offset Voltage Correction for Power Driver

2

U

2

MCP6V11

R

4

R

5

R

VDD/2

3

V

U

1

MCP6XXX

OUT

Related Parts

• MCP6V01/2/3: Auto-Zeroed, Spread Clock

• MCP6V06/7/8: Auto-Zeroed

• MCP6V26/7/8: Auto-Zeroed, Low Noise

• MCP6V31/1U: Zero-Drift, Low Power

MCP6V11/1U

NOTES:

MCP6V11/1U

1.0 ELECTRICAL CHARACTERISTICS

1.1 Absolute Maximum Ratings †

VDD–VSS .................................................................................................................................................................6.5V

Current at Input Pins ..............................................................................................................................................±2 mA

Analog Inputs (V

+ and V

IN

All other Inputs and Outputs .......................................................................................................V

Difference Input voltage .................................................................................................................................|V

Output Short Circuit Current ........................................................................................................................... Continuous

Current at Output and Supply Pins ......................................................................................................................±30 mA

Storage Temperature .............................................................................................................................-65°C to +150°C

Maximum Junction Temperature .......................................................................................................................... +150°C

ESD protection on all pins (HBM, CDM, MM) ........................................................................................... ≥ 2kV,1.5kV,400V

Note 1: See Section 4.2.1, Rail-to-Rail Inputs.

†Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the

device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

–) (Note 1) .....................................................................................V

IN

– 1.0V to VDD+1.0V

SS

– 0.3V to VDD+0.3V

SS

DD–VSS

|

1.2 Specifications

TABLE 1-1: DC ELECTRICAL SPECIFICATIONS

Electrica l Character istics: Unless otherwise indicated, T

V

CM

= VDD/3,V

OUT=VDD

/2, VL=VDD/2, RL = 100 kΩ to VL and CL = 20 pF (refer to Figure 1-4 and Figure 1-5).

Parameters Sym. Min. Typ. Max. Units Conditions

Input Offset

Input Offset Voltage V

Input Offset Voltage Drift with

TC

OS

1

Temperature (Linear Temp. Co.)

Input Offset Voltage Quadratic

TC

2

Te m p . Co .

Power Supply Rejection PSRR 118 135 — dB

Input Bias Current and Impedance

Input Bias Current I

Input Bias Current across Temperature I

Input Offset Current I

Input Offset Current across Temperature I

Common Mode Input Impedance Z

Differential Input Impedance Z

B

I

B

OS

I

OS

CM

DIFF

Note 1: For Design Guidance only; not tested.

2: Figure 2-18 shows how V

CML

and V

changed across temperature for the first production lot.

CMH

= +25°C, VDD = +1.6V to +5.5V, VSS = GND,

A

-8 — +8 µV TA = +25°C

-50 — +50 nV/°C TA = -40 to +125°C

—±0.08 —nV/°C

—+5 —pA

—+17 —pAT

0+2.9+5nAT

—±50 —pA

—±80 —pAT

-1 ±0.4 +1 nA TA = +125°C

—10

13

||6 — Ω||pF

13

||6 — Ω||pF

(Note 1)

2

TA = -40 to +125°C

= +85°C

A

= +125°C

A

= +85°C

A

MCP6V11/1U

TABLE 1-1: DC ELECTRICAL SPECIFICATIONS (CONTINUED)

Electrica l Character istics: Unless otherwise indicated, T

V

CM

= VDD/3,V

OUT=VDD

/2, VL=VDD/2, RL = 100 kΩ to VL and CL = 20 pF (refer to Figure 1-4 and Figure 1-5).

Parameters Sym. Min. Typ. Max. Units Conditions

Common Mode

Common-Mode

V

CML

Input Voltage Range Low

Common-Mode

V

CMHVDD

Input Voltage Range High

Common-Mode Rejection CMRR 108 125 — dB V

CMRR 119 135 — dB V

Open-Loop Gain

DC Open-Loop Gain (large signal) A

OL

A

OL

Output

Minimum Output Voltage Swing V

Maximum Output Voltage Swing V

Output Short Circuit Current I

OL

V

OL

OH

V

OH

SC

I

SC

Power Supply

Supply Voltage V

Quiescent Current per amplifier I

POR Trip Voltage V

DD

Q

POR

Note 1: For Design Guidance only; not tested.

2: Figure 2-18 shows how V

CML

and V

changed across temperature for the first production lot.

CMH

= +25°C, VDD = +1.6V to +5.5V, VSS = GND,

A

——V

− 0.15 V (Note 2)

SS

+0.2 — — V (Note 2)

100 120 — dB VDD=1.6V,

112 135 — dB VDD=5.5V,

V

VSS+14 VSS+45 mV RL=10kΩ, G = +2,

SS

—VSS+1.4 — mV RL=100kΩ, G = +2,

VDD–45 VDD–14 V

DD

mV RL=10kΩ, G = +2,

—VDD–1.4 — mV RL=100kΩ, G = +2,

—±5 —mAV

—±17 —mAV

1.6 — 5.5 V

47.511µAI

0.9 — 1.5 V

= 1.6V,

DD

V

= -0.15V to 1.8V

CM

(Note 2)

= 5.5V,

DD

V

= -0.15V to 5.7V

CM

(Note 2)

= 0.3V to 1.4V

V

OUT

V

= 0.3V to 5.3V

OUT

0.5V input overdrive

=1.6V

DD

=5.5V

DD

= 0

O

MCP6V11/1U

TABLE 1-2: AC ELECTRICAL SPECIFICATIONS

Electrica l Character istics: Unless otherwise indicated, T

= VDD/3, V

V

CM

OUT=VDD

/2, VL=VDD/2, RL=100kΩ to VL and C

Parameters Sym. Min. Typ. Max. Units Conditions

Amplifier AC Response

Gain Bandwidth Product GBWP — 80 — kHz

Slew Rate SR — 0.03 — V/µs

Phase Margin PM — 70 — ° G = +1

Amplifier Noise Response

Input Noise Voltage E

E

Input Noise Voltage Density e

Input Noise Current Density i

—0.67— µV

ni

—2.1—µV

ni

—102—nV/√Hz f < 500 Hz

ni

—4—fA/√Hz

ni

Amplifier Distortion (Note 1)

Intermodulation Distortion (AC) IMD — 50 — µV

Amplifier Step Response

Start Up Time t

Offset Correction Settling Time t

Output Overdrive Recovery Time t

STR

STL

ODR

— 2 — ms G = +1, 0.1% V

— 300 — µs G = +1, VIN step of 2V,

— 450 — µs G = -10, ±0.5V input overdrive to VDD/2,

Note 1: These parameters were characterized using the circuit in Figure 1-6. In Figure 2-36 and Figure 2-37,

there is an IMD tone at DC, a residual tone at1 kHz and other IMD tones and clock tones.

2: High gains behave differently; see Section 4.3.3, Offset at Power Up. 3: t

includes some uncertainty due to clock edge timing.

ODR

= +25°C, VDD = +1.6V to +5.5V, VSS = GND,

A

= 20 pF (refer to Figure 1-4 and Figure 1-5).

L

f = 0.01 Hz to 1 Hz

P-P

f = 0.1 Hz to 10 Hz

P-P

PKVCM

V

OS

V

IN

tone = 50 mV

within 100 µV of its final value

50% point to V

at 100 Hz, GN = 1

PK

settling (Note 2)

OUT

90% point (Note 3)

OUT

TABLE 1-3: TEMPERATURE SPECIFICATIONS

Electrica l Character istics: Unless otherwise indicated, all limits are specified for: V

VSS = GND.

Parameters Sym. Min. Typ. Max. Units Conditions

Temperature Ranges

Specified Temperature Range T

Operating Temperature Range T

Storage Temperature Range T

Thermal Package Resistances

Thermal Resistance, 5L-SC-70 θ

Thermal Resistance, 5L-SOT-23 θ

Note 1: Operation must not cause T

to exceed Maximum Junction Temperature specification (+150°C).

J

A

JA

-40 — +125 °C

-40 — +125 °C (Note 1)

-65 — +150 °C

—331 — °C/W

—256 — °C/W

= +1.6V to +5.5V,

DD

MCP6V11/1U

1.3 Timing Diagrams

0V

1.6V

t

STR

V

DD

OUT

FIGURE 1-1: Amplifier Start Up.

V

IN

t

STL

V

OS

FIGURE 1-2: Offset Correction Settling Time.

V

IN

t

ODR

V

DD

V

OUT

VDD/2

FIGURE 1-3: Output Overdrive Recovery.

1.6V to 5.5V

1.001(VDD/3)

0.999(V

VOS+100µV

VOS–100µV

t

ODR

V

SS

DD

/3)

1.4 Test Circuits

The circuits used for most DC and AC tests are shown in Figure 1-4 and Figure 1-5. Lay the bypass capacitors out as discussed in Section 4.3.10, Supply Bypassing

and Filtering. R

and RG to minimize bias current effects.

R

F

V

IN

MCP6V1X

VDD/3

FIGURE 1-4: AC and DC Test Circuit for Most Non-Inverting Gain Cond iti ons.

VDD/3

MCP6V1X

V

IN

FIGURE 1-5: AC and DC Test Circuit for Most Inverting Gain Conditions.

The circuit in Figure 1-6 tests the input’s dynamic behavior (i.e., IMD, t potentiometer balances the resistor network (V should equal V mode input voltage is V input (V 10 V/V.

ERR

is equal to the parallel combination of

N

V

DD

1µF

R

N

R

G

V

DD

R

N

R

G

at DC). The op amp’s common

REF

) appears at V

100 nF

STR

R

ISO

C

L

R

F

1µF

R

ISO

C

L

R

F

, t

and t

STL

CM=VIN

/2. The error at the

with a noise gain of

OUT

R

ODR

L

V

L

V

OUT

L

V

OUT

L

). The

OUT

11.0 kΩ 500 Ω

V

IN

11.0 kΩ

100 kΩ

0.1% 25 turn

0.1%

V

DD

1µF

100 nF

MCP6V1X

249 Ω

1%

0.1%

100 kΩ

0.1%

V

REF=VDD

R

ISO

/3

0 Ω

V

OUT

C

L

R

L

20 pF open

V

L

FIGURE 1-6: Test Circuit for Dynamic Input Behavior.

MCP6V11/1U

10%

n

6

Representative Part

e

0

V

25

C

O

6

Representative Part

e

+25°C

0

V

O

6

e

0

V

O

I

8

2.0 TYPICAL PERFORMANCE CURVES

Note: The graphs and tables provided following this note are a statistical summary based on a limited number of

samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range.

Note: Unless otherwise indicated, T

L=VDD

/2, RL=100kΩ to VL and CL = 20 pF.

V

=+25°C, VDD= +1.6V to 5.5V, VSS= GND, VCM=VDD/3, V

A

2.1 DC Input Precision

30%

42 Samples

= +25°C

T

A

= 1.6V and 5.5V

V

25%

DD

20%

15%

age of Occurrences

5%

Percent

0%

-8 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 7 8

FIGURE 2-1: Input Offset Voltage.

30%

42 Samples V

DD

25%

20%

15%

age of Occurrences

5%

Percent

0%

-50 -40 -30 -20 -10 0 10 20 30 40 50

FIGURE 2-2: Input Offset Voltage Drift.

Input Offset Voltage (μV)

= 1.6V and 5.5V

Input Offset Voltage Drift; TC1(nV/°C)

4.5

CML

5.0

/2,

5.5

8

4

(μV)

2

oltag

ffset

-2

-4

Input

-6

-8

-40°C + +85°C

+125°C

0.0

°

0.5

1.0

1.5

2.0

Power Supply Voltage (V)

2.5

3.0

OUT=VDD

VCM= V

3.5

4.0

FIGURE 2-4: Input Offset Voltage vs. Power Supply Voltage with V

8

125°C

4

+85°C

(μV)

-40°C

2

oltag

ffset

-2

-4

Input

-6

-8

0.0

0.5

1.0

1.5

2.0

2.5

Power Supply Voltage (V)

3.0

CM=VCML

VCM= V

3.5

4.0

4.5

CMH

5.0

.

5.5

FIGURE 2-5: Input Offset Voltage vs. Power Supply Voltage with V

CM=VCMH

.

6.0

6.5

35%

42 Samples

= 1.6V and 5.5V

V

DD

30%

25%

20%

15%

tage of Occurrences

5%

Perce

0%

-0.5 -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0.5 Input Offset Voltage's Quadratic Temp Co;

TC

(nV/°C2)

2

FIGURE 2-3: Input Offset Voltage Quadratic Temp. Co.

8

4

(μV)

2

oltag

VDD= 1.6V

ffset

-2

-4

nput

-6

-

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Power Supply Voltage (V)

Representative Part

VDD= 5.5V

FIGURE 2-6: Input Offset Voltage vs. Output Voltage.

MCP6V11/1U

6

Representative Part

e

0

V

O

40°C

+125°C

6

Representative Part

e

0

V

O

40

C

+125

C

20%

s

30%

r

15%

a

e

s

30%

r

V

6V

V

5V

15%

a

e

145

135

S

CMRR

V

5V

Note: Unless otherwise indicated, T

=+25°C, VDD= +1.6V to 5.5V, VSS= GND, VCM=VDD/3, V

A

VL=VDD/2, RL=100kΩ to VL and CL = 20 pF.

8

4

(μV)

2

oltag

ffset

-2

-4

Input

-6

-8

-0.5 0.0 0.5 1.0 1.5 2.0 2.5

VDD= 1.6V

+25°C +85°C

Input Common Mode Voltage (V)

FIGURE 2-7: Input Offset Voltage vs. Common Mode Voltage with V

8

4

(μV)

2

oltag

ffset

-2

-4

Input

-6

-8

-0.5

0.0

VDD= 5.5V

°

+25°C +85°C

°

0.5

1.0

1.5

2.0

Input Common Mode Voltage (V)

2.5

3.0

DD

3.5

=1.6V.

4.0

4.5

5.0

5.5

FIGURE 2-8: Input Offset Voltage vs. Common Mode Voltage with V

DD

=5.5V.

6.0

OUT=VDD

45%

21 Samples

= +25°C

T

40%

A

35%

rence

25%

Occu

20%

ge of

10%

rcent P

5%

0%

-1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 1/PSRR (μV/V)

/2,

FIGURE 2-10: PSRR.

45%

21 Samples

= +25°C

T

40%

35%

rence

25%

Occu

20%

ge of

10%

rcent P

5%

=1.

DD

=5.

DD

0%

-0.5 -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0.5

1/A

(μV/V)

OL

FIGURE 2-11: DC Open-Loop Gain.

70%

21 Samples T

= 25°C

A

60%

50%

VDD= 5.5V

40%

30%

tage of Occurrences

10%

Percen

VDD= 1.6V

0%

-1.6

-1.2

-0.8

-0.4

1/CMRR (μV/V)

FIGURE 2-9: CMRR.

0.0

0.4

0.8

1.2

1.6

160

155

150

B)

140

RR (d

130

RR, P

125

CM

120

115

110

=5.

DD

VDD= 1.6V

-50 -25 0 25 50 75 100 125 Ambient Temperature (°C)

PSRR

FIGURE 2-12: CMRR and PSRR vs. Ambient Temperature.

MCP6V11/1U

145

n

135

o

e

D

V

150

p

DD

0

e

s u

4000

p

VDD5.5V

3000

e

s

1000

u

A

r

100

e

100

s

1p

1.E

03

A

1m

M

1.E-08

u

+85

C

10n

p

Note: Unless otherwise indicated, T

=+25°C, VDD= +1.6V to 5.5V, VSS= GND, VCM=VDD/3, V

A

VL=VDD/2, RL=100kΩ to VL and CL = 20 pF.

160

155

150

(dB)

140

p Gai

130

n-Lo

125

C Op

120

115

110

-50 -25 0 25 50 75 100 125

VDD= 5.5V

= 1.6V

V

DD

Ambient Temperature (°C)

FIGURE 2-13: DC Open-Loop Gain vs. Ambient Temperature.

200

A)

100

ents (

50

t Curr

-50

, Offs

-100

t Bia

-150

Inp

-200

TA= +85°C

= 5.5V

0.0

0.5

1.0

1.5

-0.5

Common Mode Input Voltage (V)

2.0

2.5

I

B

I

OS

3.0

3.5

4.0

4.5

5.0

5.5

6.0

FIGURE 2-14: Input Bias and Offset Currents vs. Common Mode Input Voltage with T

= +85°C.

A

OUT=VDD

10000

10n

VDD= 5.5V

)

1000

1n

ents (

t Cur

p

I

OS

, Offs

10

10p

ut Bia

Inp

1

I

B

25 35 45 55 65 75 85 95 105 115 125

Ambient Temperature (°C)

/2,

FIGURE 2-16: Input Bias and Offset Currents vs. Ambient Temperature with V

=+5.5V.

DD

1.E-02

10m

)

-

1.E-04

100μ

ude (

1.E-05

10μ

agnit

1.E-06

1μ

1.E-07

100n

rrent

1.E-09

1n

put C In

1.E-10

100p

1.E-11

10

-1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0

+125°C

°

+25°C

-40°C

Input Voltage (V)

FIGURE 2-17: Input Bias Current vs. Input Voltage (below V

SS

).

5000

TA= +125°C

A)

ents (

2000

t Curr

1000

, Offs

t Bia

-

Inp

-2000

=

I

B

0

-0.5

I

OS

0.0

0.5

1.0

1.5

2.0

2.5

3.0

Common Mode Input Voltage (V)

3.5

4.0

4.5

5.0

5.5

6.0

FIGURE 2-15: Input Bias and Offset Currents vs. Common Mode Input Voltage with T

= +125°C.

A

MCP6V11/1U

0.3

g

0.0

o

m

H

p

V

r

VDDV

OH

V

DD

10

V

u

4

u

o C

35%

e

1 Wafer Lot

u

20%

f

t

5%

P

4

Note: Unless otherwise indicated, T

=+25°C, VDD= +1.6V to 5.5V, VSS= GND, VCM=VDD/3, V

A

VL=VDD/2, RL=100kΩ to VL and CL = 20 pF.

2.2 Other DC Voltages and Currents

0.4

e

Upper ( V

0.2

Vol ta

0.1

m (V)

Mode

mon

-0.1

eadro

ut Co

In

Lower (V

-0.2

-0.3

-0.4

-50 -25 0 25 50 75 100 125

)

CMH–VDD

)

CML–VSS

Ambient Temperature (°C)

FIGURE 2-18: Input Common Mode Voltage Headroom (Range) vs. Ambient Temperature.

1000

)

oom (

100

Head

oltage

tput O

VOL–V

1

0.1 1 10

–

SS

Output Current Magnitude (V)

FIGURE 2-19: Output Voltage Headroom vs. Output Current.

1 Wafer Lot

VDD= 5.5V

= 1.6V

4.5

5.0

/2,

5.5

6.0

6.5

40

0.0

-40°C +25°C +85°C

+125°C

+85°C +25°C

-40°C

0.5

1.0

1.5

Power Supply Voltage (V)

30

20

10

0

-10

rt Circuit Current (mA)

-20

-30

Output Sh

-40

2.0

2.5

3.0

3.5

OUT=VDD

4.0

FIGURE 2-21: Output Short Circuit Current vs. Power Supply Voltage.

10

9

8

7

6

5

4

urrent (μA/amplifier)

3

2

1

Supply

0

1.5

2.0

+125°C

+85°C +25°C

-40°C

2.5

3.0

3.5

Power Supply Voltage (V)

4.0

4.5

5.0

5.5

FIGURE 2-22: Supply Current vs. Power Supply Voltage.

12

RL= 25 k

11

10

9 8 7

VDD= 5.5V

6 5

t Headroom (mV)

3

Outp

2

VDD= 1.6V

1 0

-50 -25 0 25 50 75 100 125

VOL–V

SS

Ambient Temperature (°C)

VDD–V

OH

FIGURE 2-20: Output Voltage Headroom vs. Ambient Temperature.

40%

850 Samples

s

TA= +25°C

30%

rrenc

25%

Occ

15%

age o

10%

ercen

0%

1.141.161.181.201.221.241.261.281.301.321.3

POR Trip Voltage (V)

FIGURE 2-23: Power-on Reset Trip Voltage.

MCP6V11/1U

R

Note: Unless otherwise indicated, T

=+25°C, VDD= +1.6V to 5.5V, VSS= GND, VCM=VDD/3, V

A

VL=VDD/2, RL=100kΩ to VL and CL = 20 pF.

1.6

1.4

1.2

1.0

0.8

0.6

Trip Voltage (V)

0.4

PO

0.2

0.0

-50 -25 0 25 50 75 100 125 Ambient Temperature (°C)

FIGURE 2-24: Power-on Reset Voltage vs. Ambient Temperature.

OUT=VDD

/2,

MCP6V11/1U

R



180

10

n



180

10

n

h

d

h

Note: Unless otherwise indicated, T

=+25°C, VDD= +1.6V to 5.5V, VSS= GND, VCM=VDD/3, V

A

VL=VDD/2, RL=100kΩ to VL and CL = 20 pF.

2.3 Frequency Response

100

90

80

70

60

50

40

R, PSRR (dB)

30

CM

20

10

0

10 10k

1.E+01 1.E+02 1.E+03 1.E+04 1.E+05

100

Frequency (Hz)

FIGURE 2-25: CMRR and PSRR vs. Frequency.

70

60

50

40

30

20

-Loop Gain (dB)

0

Ope

-10

-20

100 100k1k 1M10k

1.E+02 1.E+03 1.E+04 1.E+05 1.E+06

Frequency (Hz)

FIGURE 2-26: Open-Loop Gain vs. Frequency with V

DD

=1.6V.

PSRR

CMRR

VDD= 1.6V C

A

| AOL|

= 20 pF

L

OL

0

-30

-60

-90

-120

-150

-

-210

-240

-270

100k1k

-Loop Phase (°)

Ope

OUT=VDD

140

120

100

80

60

width Product (kHz)

40

20

Gain Ban

0

-50 -25 0 25 50 75 100 125

PM

VDD= 5.5V

GBWP

Ambient Temperature (°C)

VDD= 1.6V

/2,

100

90

80

70

60

50

40

30

FIGURE 2-28: Gain Bandwidth Product and Phase Margin vs. Ambient Temperature.

5.0

5.5

100

90

80

70

60

50

40

30

6.0

140

120

100

80

60

dwidth Product (kHz)

40

20

Gain Ban

0

PM

GBWP

VDD= 1.6V

0.0

0.5

1.0

1.5

2.0

2.5

-0.5

Common Mode Input Voltage (V)

3.0

VDD= 5.5V

3.5

4.0

RF= 1 M

4.5

FIGURE 2-29: Gain Bandwidth Product and Phase Margin vs. Common Mode Input Voltage.

ase Margin (°) P

140

120

100

80

60

dwidth Product (kHz)

40

20

Gain Ban

0

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Output Voltage (V)

VDD= 5.5V

GBWP

PM

VDD= 1.6V

FIGURE 2-30: Gain Bandwidth Product and Phase Margin vs. Output Voltage.

= 20 pF

OL

0

-30

-60

-90

-120

-150

-

-210

-240

-270

-Loop Phase (°)

Ope

70

60

50

40

30

20

-Loop Gain (dB)

0

Ope

-10

-20

100 100k1k 1M10k

1.E+02 1.E+03 1.E+04 1.E+05 1.E+06

Frequency (Hz)

VDD= 5.5V C

L

A

| AOL|

FIGURE 2-27: Open-Loop Gain vs. Frequency with V

DD

=5.5V.

100

90

80

70

60

50

40

30

ase Margin (°) P

Datasheet MCP6V11, MCP6V11U Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

1.0 ELECTRICAL CHARACTERISTICS

1.1 Absolute Maximum Ratings †

1.2 Specifications

TABLE 1-1: DC ELECTRICAL SPECIFICATIONS

TABLE 1-2: AC ELECTRICAL SPECIFICATIONS

TABLE 1-3: TEMPERATURE SPECIFICATIONS

1.3 Timing Diagrams

FIGURE 1-1: Amplifier Start Up.

FIGURE 1-2: Offset Correction Settling Time.

FIGURE 1-3: Output Overdrive Recovery.

1.4 Test Circuits

FIGURE 1-4: AC and DC Test Circuit for Most Non-Inverting Gain Cond iti ons.

FIGURE 1-5: AC and DC Test Circuit for Most Inverting Gain Conditions.

FIGURE 1-6: Test Circuit for Dynamic Input Behavior.

2.0 TYPICAL PERFORMANCE CURVES

2.1 DC Input Precision

FIGURE 2-1: Input Offset Voltage.

FIGURE 2-2: Input Offset Voltage Drift.

FIGURE 2-3: Input Offset Voltage Quadratic Temp. Co.

FIGURE 2-6: Input Offset Voltage vs. Output Voltage.

FIGURE 2-10: PSRR.

FIGURE 2-11: DC Open-Loop Gain.

FIGURE 2-9: CMRR.

FIGURE 2-12: CMRR and PSRR vs. Ambient Temperature.

FIGURE 2-13: DC Open-Loop Gain vs. Ambient Temperature.

2.2 Other DC Voltages and Currents

FIGURE 2-18: Input Common Mode Voltage Headroom (Range) vs. Ambient Temperature.

FIGURE 2-19: Output Voltage Headroom vs. Output Current.

FIGURE 2-21: Output Short Circuit Current vs. Power Supply Voltage.

FIGURE 2-22: Supply Current vs. Power Supply Voltage.

FIGURE 2-20: Output Voltage Headroom vs. Ambient Temperature.

FIGURE 2-23: Power-on Reset Trip Voltage.

FIGURE 2-24: Power-on Reset Voltage vs. Ambient Temperature.

2.3 Frequency Response

FIGURE 2-25: CMRR and PSRR vs. Frequency.

FIGURE 2-28: Gain Bandwidth Product and Phase Margin vs. Ambient Temperature.

FIGURE 2-29: Gain Bandwidth Product and Phase Margin vs. Common Mode Input Voltage.

FIGURE 2-30: Gain Bandwidth Product and Phase Margin vs. Output Voltage.