Datasheet MCP6N16 Datasheet

MCP6N16

V

OUT

20 kΩ

100Ω

2.49 kΩ

68.1Ω

RTD

4.99 kΩ

V

DD

MCP6N16-100

10 µF

100Ω

EN

100Ω

RTD Temperature Sensor

4.99 kΩ 4.99 kΩ

MCP6N16

MSOP

V

IP

V

IM

V

SS

V

OUT

V

FG

1

2

3

4

8

7

6

5

V

REF

V

DD

EN

MCP6N16

3×3 DFN *

V

IP

V

IM

V

SS

V

OUT

V

FG

1

2

3

4

8

7

6

5

V

REF

V

DD

EN

* Includes Exposed Thermal Pad (EP); see Table 3-1.

EP

9

Zero-Drift Instrumentation Amplifier

Features:

• High DC Precision:

-V

: ±17 µV (maximum, G

OS

-TC1: ±60 nV/°C (maximum, G

- CMRR: 112 dB (minimum, G =5.5V)

V

DD

- PSRR: 110 dB (minimum, G =5.5V)

V

DD

: ±0.15% (maximum, G

-g

E

• Flexible:

- Minimum Gain (G

) Options:

MIN

1, 10 and 100 V/V

- Rail-to-Rail Input and Output

- Gain Set by Two External Resistors

• Bandwidth: 500 kHz (typical, Gain = G

• Power Supply:

-VDD: 1.8V to 5.5V

-I

: 1.1 mA (typical)

Q

- Power Savings (Enable) Pin: EN

• Enhanced EMI Protection:

- Electromagnetic Interference Rejection Ratio

(EMIRR): 111 dB at 2.4 GHz

• Extended Temperature Range: -40°C to +125°C

MIN

= 10, 100)

MIN

= 100)

= 100,

=100,

MIN

=1, 10)

Description:

Microchip Technology Inc. offers the single Zero-Drift MCP6N16 instrumentation amplifier (INA) with Enable pin (EN) and three minimum gain options (G

MIN

). The internal offset correction gives high DC precision: it has very low offset and offset drift, and negligible 1/f noise.

Two external resistors set the gain, minimizing gain error and drift over temperature. The reference voltage

) shifts the output voltage (V

(V

REF

OUT

).

The MCP6N16 is designed for single-supply operation, with rail-to-rail input (no common mode crossover distortion) and output performance. The supply voltage range (1.8V to 5.5V) is low enough to support many portable applications. All devices are fully specified from -40°C to +125°C. Each part has EMI filters at the input pins, for good EMI rejection (EMIRR).

These parts have three minimum gain options (1, 10 and 100 V/V). This allows the user to optimize the input offset voltage and input noise for different applications.

Typical Application Circuit

Typical Applications:

• High-Side Current Sensor

• Wheatstone Bridge Sensors

• Difference Amplifier with Level Shifting

• Power Control Loops

Design Aids:

• SPICE Macro Model

• Microchip Advanced Part Selector (MAPS)

• Application Notes

 2014 Microchip Technology Inc. DS20005318A-page 1

Package Types

MCP6N16

-1

0

10

20

30

40

ffset Voltage (µV)

-40

-30

-20

0

-50 -25 0 25 50 75 100 125

Input

O

Ambient Temperature (°C)

G

MIN

= 1 28 Samples V

DD

= 5.5V

V

CM

= VDD/2

NPBW = 3 mHz

4

2

3

(µV)

1

oltag

e

-1

0

ffset

V

-2

nput

O

G

MIN

= 10

28 Samples

-3

I

V

DD

=5.

5V

VCM= VDD/2 NPBW = 3 mHz

-

4

-50 -25 0 25 50 75 100 125 Ambient Temperature (°C)

4

2

3

(µV)

1

oltag

e

-1

0

ffset

V

-2

nput

O

G

MIN

= 100

28 Samples

-3

I

VDD=5.5V

VCM= VDD/2 NPBW = 3 mHz

-

4

-50 -25 0 25 50 75 100 125 Ambient Temperature (°C)

Minimum Gain Options

Table 1 shows key specifications that differentiate

between the different minimum gain (G See Section 1.0 “Electrical Characteristics”,

Section 6.0 “Packaging Information” and Product

Identification System for further information on G

TABLE 1: KEY DIFFERENTIATING SPECIFICATIONS

G

V

MIN

Part No.

(V/V)

Nom.

MCP6N16-001 1 85 1800 89 91 2.7 0.50 19 900

MCP6N16-010 10 22 180 103 104 0.27 5.0 2.2 105

MCP6N16-100 100 17 60 112 110 0.027 35 0.93 45

Note 1: G

is the minimum stable gain (GDM), for a given part option. In other words, GDM≥ G

MIN

Figures 1 to 3 show input offset voltage versus

temperature for the three gain options (G 100 V/V).

OS

(±μV)

Max.

TA= -40 to +125°C

MIN

TC

1

(±nV/°C)

Max.

MIN

) options.

.

MIN

=1, 10,

CMRR

(dB) Min.

VDD=5.5V

PSRR

(dB) Min.

V

DMH

(V)

Min.

GBWP

(MHz)

Typ.

E

ni

(μV

)

P-P

Typ .

f = 0.1 to 10 Hz

.

MIN

(nV/√Hz)

Typ .

f < 500 Hz

e

ni

FIGURE 1: Input Offset Voltage vs. Temperature, with G

FIGURE 2: Input Offset Voltage vs. Temperature, with G

DS20005318A-page 2  2014 Microchip Technology Inc.

MIN

=1.

=10.

FIGURE 3: Input Offset Voltage vs. Temperature, with G

MIN

= 100.

 2014 Microchip Technology Inc. DS20005318A-page 3

1.0 ELECTRICAL CHARACTERISTICS

1.1 Absolute Maximum Ratings †

VDD–VSS ............................................................................................................................................................................................................................................ 6.5V

Current at Input Pins (Note 1) ........................................................................................................................................................................................................... ±2 mA

Analog Inputs (V

All Other Inputs and Outputs ............................................................................................................................................................................... V

Difference Input Voltage .............................................................................................................................................................................................................|V

Output Short-Circuit Current ...................................................................................................................................................................................................... Continuous

Current at Output and Supply Pins .................................................................................................................................................................................................. ±30 mA

Storage Temperature ......................................................................................................................................................................................................... -65°C to +150°C

Maximum Junction Temperature ......................................................................................................................................................................................................+150°C

ESD protection on all pins (HBM, MM)..................................................................................................................................................................................... ≥ 4kV,400V

† Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

Note 1: See Section 4.3.1.2 “Input Voltage Limits” and Section 4.3.1.3 “Input Current Limits”.

and VIM) (Note 1) .................................................................................................................................................................. VSS– 1.0V to VDD+1.0V

IP

– 0.3V to VDD+0.3V

SS

DD–VSS

|

MCP6N16

DS20005318A-page 4  2014 Microchip Technology Inc.

1.2 Specifications

MCP6N16

TABLE 1-1: DC ELECTRICAL SPECIFICATIONS

Electrical Characteristics: Unless otherwise indicated, TA=+25°C, VDD= 1.8V to 5.5V, VSS= GND, VCM=VDD/2, VDM=0V, V

to V

, GDM=G

L

and EN = VDD; see Figures 1-7 and 1-8 (Note 1).

MIN

Parameters Sym. Min. Typ. Max. Units G

REF=VDD

MIN

Input Offset

Input Offset Voltage V

OS

-85 — +85 µV 1 TA=+25°C

-22 — +22 10

-17 — +17 100

Input Offset Voltage Drift – Linear Temp. Co.

TC

1

-1800 — +1800 nV/°C 1 TA= -40°C to +125°C (Note 2)

-180 — +180 10

-60 — +60 100

Input Offset Voltage Drift – Quadratic Temp. Co.

TC

2

—±560—pV/°C

—±63— 10

2

1TA= -40°C to +125°C

—±69— 100

Input Offset Aging ∆V

OS

— ±1.0 — µV 1 408 hr Life Test at +150°C,

—±0.8— 10

—±0.7— 100

Power Supply Rejection Ratio PSRR 91 109 — dB 1

104 122 — 10

110 128 — 100

Output Offset

Output Offset Voltage V

OSO

0µVall

Input Current and Impedance (Note 3)

Input Bias Current I

B

-100 ±2 +100 pA all

Across Temperature — 20 — TA=+85°C

Across Temperature 0 250 2000 TA=+125°C

Note 1: V

=(VIP+VIM)/2, VDM=(VIP–VIM) and GDM=1+RF/RG.

CM

2: For Design Guidance only; not tested. 3: These specifications apply to the V 4: This specification applies to the V 5: Figures 2-52 and 2-53 show the V

, VIM input pair (use VCM) and to the V

IP

, VIM, V

IP

, V

IVL

and VFG pins individually.

REF

, V

DML

and V

DMH

IVH

variation over temperature.

, VFG input pair (use V

REF

instead).

REF

6: See Section 1.5 “Explanation of DC Error Specifications”.

/2, VL=VDD/2, RL=10kΩ

Conditions

measured at +25°C

 2014 Microchip Technology Inc. DS20005318A-page 5

TABLE 1-1: DC ELECTRICAL SPECIFICATIONS (CONTINUED)

Electrical Characteristics: Unless otherwise indicated, TA=+25°C, VDD= 1.8V to 5.5V, VSS= GND, VCM=VDD/2, VDM=0V, V

to VL, GDM=G

and EN = VDD; see Figures 1-7 and 1-8 (Note 1).

MIN

Parameters Sym. Min. Typ. Max. Units G

Input Offset Current I

OS

-800 ±300 +800 pA all

Across Temperature — ±320 — TA=+85°C

Across Temperature -1500 ±350 +1500 T

Common Mode Input Impedance Z

Differential Input Impedance Z

Input Common Mode Voltage (V

CM

or V

) (Note 3)

REF

Input Voltage Range (Note 4, Note 5) V

DIFF

V

CM

IVL

IVH

—10

—V

VDD+0.15 VDD+0.30 —

13

||10 — Ω||pF

13

||4 —

–0.25 VSS–0.15 V all

SS

Common Mode Rejection Ratio CMRR 80 98 — dB 1 V

94 112 — 10

103 121 — 100

89 107 — 1 V

103 121 — 10

112 130 — 100

Common Mode Rejection Ratio at V

REF

CMRR2 83 101 — dB 1 V

98 116 — 10

102 120 — 100

94 112 — 1 V

109 127 — 10

115 133 — 100

Note 1: V

=(VIP+VIM)/2, VDM=(VIP–VIM) and GDM=1+RF/RG.

CM

2: For Design Guidance only; not tested. 3: These specifications apply to the V 4: This specification applies to the V 5: Figures 2-52 and 2-53 show the V

, VIM input pair (use VCM) and to the V

IP

, VIM, V

IP

, V

IVL

and VFG pins individually.

REF

, V

DML

and V

DMH

IVH

variation over temperature.

, VFG input pair (use V

REF

instead).

REF

6: See Section 1.5 “Explanation of DC Error Specifications”.

REF=VDD

MIN

=+125°C

A

CM=VIVL

REF

V

DD

REF

V

DD

/2, VL=VDD/2, RL=10kΩ

Conditions

to V

, VDD=1.8V

IVH

, VDD=5.5V

IVH

= 0.2V to VDD–0.2V,

=1.8V

= 0.2V to VDD–0.2V,

=5.5V

MCP6N16

DS20005318A-page 6  2014 Microchip Technology Inc.

TABLE 1-1: DC ELECTRICAL SPECIFICATIONS (CONTINUED)

Electrical Characteristics: Unless otherwise indicated, TA=+25°C, VDD= 1.8V to 5.5V, VSS= GND, VCM=VDD/2, VDM=0V, V

to VL, GDM=G

Common Mode Nonlinearity (Note 6) INL

and EN = VDD; see Figures 1-7 and 1-8 (Note 1).

MIN

Parameters Sym. Min. Typ. Max. Units G

CM

-550 — +550 ppm 1 VCM=V

REF=VDD

MIN

/2, VL=VDD/2, RL=10kΩ

Conditions

IVL

to V

, VDD=1.8V

IVH

MCP6N16

-75 — +75 10

-20 — +20 100

-310 — +310 1 V

CM=VIVL

to V

, VDD=5.5V

IVH

-35 — +35 10

-10 — +10 100

Input Differential Voltage (V

Differential Input Voltage Range (Note 5) V

Differential Gain Error (Note 6) g

Note 1: V

=(VIP+VIM)/2, VDM=(VIP–VIM) and GDM=1+RF/RG.

CM

) (Note 3)

DM

V

DML

DMH

E

— -3.4/G

+2.7/G

MIN

+3.4/G

MIN

—±0.03—%1V

— ±0.02 — % 10, 100

—±0.03— 1V

— ±0.02 — 10, 100

-2.7/G

MIN

—V

VallVDD≥ 2.9V, V

V

within ±0.2%

OUT

≥ 2.9V, V

DD

within ±0.2%

V

OUT

= 1.8V, V

DD

=±(0.7V)/G

V

DM

= 5.5V, V

DD

V

= ±(2.55V)/G

DM

-0.25 ±0.04 +0.25 % 1 VDD= 5.5V, V = 0 to (2.7V)/G

V

-0.15 ±0.02 +0.15 % 10, 100

-0.25 ±0.04 +0.25 % 1 V

-0.15 ±0.02 +0.15 % 10, 100

DM

= 5.5V, V

DD

= 0 to (-2.7V)/G

V

DM

REF=VDD

=0V,

REF

REF=VDD

MIN

REF=VDD

MIN

=0.2V,

REF

MIN

=5.3V,

REF

MIN

,

/2,

2: For Design Guidance only; not tested. 3: These specifications apply to the V 4: This specification applies to the V 5: Figures 2-52 and 2-53 show the V

, VIM input pair (use VCM) and to the V

IP

, VIM, V

IP

, V

IVL

and VFG pins individually.

REF

, V

DML

and V

DMH

IVH

variation over temperature.

, VFG input pair (use V

REF

instead).

REF

6: See Section 1.5 “Explanation of DC Error Specifications”.

 2014 Microchip Technology Inc. DS20005318A-page 7

TABLE 1-1: DC ELECTRICAL SPECIFICATIONS (CONTINUED)

Electrical Characteristics: Unless otherwise indicated, TA=+25°C, VDD= 1.8V to 5.5V, VSS= GND, VCM=VDD/2, VDM=0V, V

to VL, GDM=G

Differential Gain Drift (Note 6) ∆gE/∆T

Differential Nonlinearity (Note 6) INL

DC Open-Loop Gain A

Note 1: V

2: For Design Guidance only; not tested. 3: These specifications apply to the V 4: This specification applies to the V 5: Figures 2-52 and 2-53 show the V 6: See Section 1.5 “Explanation of DC Error Specifications”.

and EN = VDD; see Figures 1-7 and 1-8 (Note 1).

MIN

Parameters Sym. Min. Typ. Max. Units G

A

— ±3 — ppm/°C all VDD= 1.8V, V

—±4— V

—±3— V

DM

—±300—ppmallV

—±150— V

—±300— V

OL

84 102 — dB 1 VDD=1.8V,

100 118 — 10

108 126 — 100

95 113 — 1 V

111 129 — 10

119 137 — 100

=(VIP+VIM)/2, VDM=(VIP–VIM) and GDM=1+RF/RG.

CM

, VIM input pair (use VCM) and to the V

IP

, VIM, V

IP

, V

IVL

and VFG pins individually.

REF

, V

DML

and V

DMH

IVH

variation over temperature.

, VFG input pair (use V

REF

instead).

REF

REF=VDD

MIN

/2, VL=VDD/2, RL=10kΩ

Conditions

=±(0.7V)/G

V

DM

= 5.5V, V

DD

= ±(2.55V)/G

V

DM

= 5.5V, V

DD

V

= 0 to (2.7V)/G

DM

= 5.5V, V

DD

= 0 to (-2.7V)/G

V

DM

= 1.8V, V

DD

=±(0.7V)/G

V

DM

= 5.5V, V

DD

V

= ±(2.55V)/G

DM

= 5.5V, V

DD

= 0 to (2.7V)/G

V

DM

= 5.5V, V

DD

= 0 to (-2.7V)/G

V

DM

V

= 0.2V to 1.6V

OUT

=5.5V,

DD

V

= 0.2V to 5.3V

OUT

REF=VDD

MIN

REF=VDD

MIN

=0.2V,

REF

=5.3V,

REF

REF=VDD

MIN

REF=VDD

MIN

=0.2V,

REF

=5.3V,

REF

/2,

MIN

/2,

MIN

MCP6N16

DS20005318A-page 8  2014 Microchip Technology Inc.

TABLE 1-1: DC ELECTRICAL SPECIFICATIONS (CONTINUED)

Electrical Characteristics: Unless otherwise indicated, TA=+25°C, VDD= 1.8V to 5.5V, VSS= GND, VCM=VDD/2, VDM=0V, V

to VL, GDM=G

and EN = VDD; see Figures 1-7 and 1-8 (Note 1).

MIN

Parameters Sym. Min. Typ. Max. Units G

REF=VDD

MIN

/2, VL=VDD/2, RL=10kΩ

Conditions

MCP6N16

Output

Minimum Output Voltage Swing V

Maximum Output Voltage Swing V

OL

OH

—V

+3 — mV all RL=10kΩ, VDD=1.8V,

SS

+6 — RL=10kΩ, VDD=5.5V,

SS

+60 VSS+ 250 RL=1kΩ, VDD=5.5V,

SS

–3 — mV RL=10kΩ, VDD=1.8V,

DD

–6 — RL=10kΩ, VDD=5.5V,

DD

V

=-VDD/(2G

DM

V

REF=VDD

V

=-VDD/(2G

DM

V

REF=VDD

V

=-VDD/(2G

DM

V

REF=VDD

V

DM=VDD

V

REF=VDD

V

DM=VDD

V

REF=VDD

/2 – 0.9V

/2 – 1V

/(2G

MIN

/2 + 0.9V

/(2G

MIN

/2 + 1V

MIN

),

VDD–250 VDD–60 — RL=1kΩ, VDD=5.5V,

Output Short-Circuit Current I

SC

V

DM=VDD

V

REF=VDD

—±10—mAV

—±35— V

DD

=1.8V

=5.5V

/(2G

MIN

/2 + 1V

),

Power Supply

Supply Voltage V

Quiescent Current per Amplifier I

POR Trip Voltage V

V

Note 1: V

=(VIP+VIM)/2, VDM=(VIP–VIM) and GDM=1+RF/RG.

CM

DD

Q

PRL

PRH

1.8 — 5.5 V all

0.5 1.1 1.6 mA IO=0

0.9 1.27 — V

—1.331.6V

2: For Design Guidance only; not tested. 3: These specifications apply to the V 4: This specification applies to the V 5: Figures 2-52 and 2-53 show the V

, VIM input pair (use VCM) and to the V

IP

, VIM, V

IP

, V

IVL

and VFG pins individually.

REF

, V

DML

and V

DMH

IVH

variation over temperature.

, VFG input pair (use V

REF

instead).

REF

6: See Section 1.5 “Explanation of DC Error Specifications”.

 2014 Microchip Technology Inc. DS20005318A-page 9

TABLE 1-2: AC ELECTRICAL SPECIFICATIONS

Electrical Characteristics: Unless otherwise indicated, TA= +25°C, VDD= 1.8V to 5.5V, VSS= GND, VCM=VDD/2, VDM=0V, V

R

=10kΩ to VL, CL= 60 pF, GDM=G

L

Parameters Sym.

and EN = VDD; see Figures 1-7 and 1-8.

MIN

Min.

Typ.

Max.

Units G

MIN

REF=VDD

Conditions

AC Response

Gain-Bandwidth Product GBWP — 0.5 — MHz 1

—5 — 10

— 35 — 100

Phase Margin PM — 70 — ° all

Open-Loop Output Impedance R

OL

—1.6 —kΩ

Power Supply Rejection Ratio PSRR — 80 — dB 1 f = 1 kHz

—98 — 10

— 123 — 100

Common Mode Rejection Ratio

and V

at V

CM

REF

CMRR, CMRR2 — 83 — dB 1 f = 10 kHz

—80 — 10

— 140 — 100

Step Response (see Section 4.1.4 “AC Performance”)

Slew Rate SR Note 1 V/µs all

Start-Up Time t

STR

—2 —ms1GDM= 1000, VDD power up to 0.1% V

—0.3 — 10

— 0.2 — 100

Overdrive Recovery,

Input Common Mode

Overdrive Recovery,

Input Differential Mode

Overdrive Recovery, Output t

t

IRC

t

IRD

OR

—1 —µsallVIP=VIM=V

90% of V

—10 — G

MINVDM=GMINVDMH

= 1V (or VDD– 1V), 90% of V

V

REF

—180 — GDMVDM= 1.5V to 0V (or -1.5V to 0V),

V

REF=VDD

+ 0.5V to VDD– 1V (or V

IVH

change (IB≤ 2mA) (Note 4)

OUT

+ 0.5V to 0V (or G

– 1V (or 1V), 90% of V

OUT

Note 1: The slew rate is limited by the GBWP; the large signal step response is dominated by the small signal bandwidth.

2: These parameters were characterized using the circuit in Figure 1-8. In Figures 2-75 and 2-76, there is an IMD tone at DC, a residual tone at 100 Hz and

other IMD tones and clock tones.

3: High gains behave differently; see Section 4.4.4 “Offset at Power-Up”.

, t

4: t

STR

STL

IRC

and tOR include some uncertainty due to clock edge timing.

IRD

/2, VL=VDD/2,

settling (Note 3, Note 4)

OUT

– 0.5V to 1V),

IVL

MINVDML

– 0.5V to 0V),

change (Note 4)

MCP6N16

DS20005318A-page 10  2014 Microchip Technology Inc.

TABLE 1-2: AC ELECTRICAL SPECIFICATIONS (CONTINUED)

Electrical Characteristics: Unless otherwise indicated, TA= +25°C, VDD= 1.8V to 5.5V, VSS= GND, VCM=VDD/2, VDM=0V, V

RL=10kΩ to VL, CL= 60 pF, GDM=G

Parameters Sym.

and EN = VDD; see Figures 1-7 and 1-8.

MIN

Min.

Typ.

Max.

Units G

MIN

Conditions

REF=VDD

/2, VL=VDD/2,

MCP6N16

Noise

Input Noise Voltage Density e

ni

—900 —nV/√Hz 1 f = 500 Hz

—105 — 10

— 45 — 100

Input Noise Voltage E

ni

—19 —µV

1 f = 0.1 Hz to 10 Hz

P-P

—2.2 — 10

— 0.93 — 100

— 5.9 — 1 f = 0.01 Hz to 1 Hz

—0.69 — 10

— 0.30 — 100

Input Current Noise Density i

Output Noise Voltage Density e

Output Noise Voltage E

ni

no

—7 —fA/√Hz all f = 1 kHz

0nV/√Hz

0µV

P-P

Amplifier Distortion (Note 2)

Intermodulation Distortion (AC) IMD — 5 — µV

all VCM tone = 100 mV

PK

at 100 Hz

PK

EMI Protection

EMI Rejection Ratio EMIRR — 103 — dB all VIN=0.1VPK, f = 400 MHz

—106 — V

=0.1VPK, f = 900 MHz

IN

—106 — VIN=0.1VPK, f = 1800 MHz

— 111 — VIN=0.1VPK, f = 2400 MHz

Note 1: The slew rate is limited by the GBWP; the large signal step response is dominated by the small signal bandwidth.

2: These parameters were characterized using the circuit in Figure 1-8. In Figures 2-75 and 2-76, there is an IMD tone at DC, a residual tone at 100 Hz and

other IMD tones and clock tones.

3: High gains behave differently; see Section 4.4.4 “Offset at Power-Up”. 4: t

STR

, t

STL

IRC

and tOR include some uncertainty due to clock edge timing.

IRD

 2014 Microchip Technology Inc. DS20005318A-page 11

TABLE 1-3: DIGITAL ELECTRICAL SPECIFICATIONS

Electrical Characteristics: Unless otherwise indicated, TA=+25°C, VDD= 1.8V to 5.5V, VSS= GND, VCM=VDD/2, VDM=0V, V

R

=10kΩ to VL, CL=60 pF, GDM=G

L

Parameters Sym. Min. Typ. Max. Units G

EN Low Specifications

EN Logic Threshold, Low V

EN Input Current, Low I

GND Current I

Amplifier Output Leakage I

EN High Specifications

EN Logic Threshold, High V

EN Input Current, High I

EN Dynamic Specifications

EN Input Hysteresis V

EN Input Resistance R

EN Low to Amplifier Output High Z Turn-Off Time t

EN High to Amplifier Output On Time t

EN Low to EN High hold time t

EN High to EN Low setup time t

POR Dynamic Specifications

V

↓ to Output Off t

DD

VDD ↑ to Output On t

Note 1: For design guidance only; not tested.

and EN = VDD; see Figures 1-7 and 1-8.

MIN

IL

ENL

SS

O(LEAK)

IH

ENH

HYST

PD

OFF

ON

——0.2VDDVall

— -10 — pA EN = 0V

-8 -2 — µA EN = 0V, VDD=5.5V

—-1—nA EN=0V

0.8V

DD

——Vall

—10—pA EN=V

—

0.16V

—

10

—0.1 2µs EN=0.2VDD to V

— 12 100 VDD= 1.8V, EN = 0.8VDD to V

— 30 100 V

ENLH

ENHL

PHL

PLH

50 — — Minimum time before releasing EN (Note 1)

50 — — Minimum time before exerting EN (Note 1)

—10—µsallV

—

100

13

MIN

—

DD

—

—V

Vall

Ω

DD

=0V, VDD= 1.8V to V

L

=0V, VDD= 0V to V

L

DD

= 5.5V, EN = 0.8VDD to V

REF=VDD

Conditions

=0.1(VDD/2), VL=0V

OUT

– 0.1V step, 90% of V

PRL

+ 0.1V step, 90% of V

PRH

/2, VL=VDD/2,

=0.9(VDD/2), VL=0V

change

OUT

change

OUT

MCP6N16

DS20005318A-page 12  2014 Microchip Technology Inc.

MCP6N16

TABLE 1-4: TEMPERATURE SPECIFICATIONS

Electrical Characteristics: Unless otherwise indicated, all limits are specified for: VDD= 1.8V to 5.5V, VSS= GND.

Parameters Sym. Min. Typ. Max. Units Conditions

Temperature Ranges

Specified Temperature Range T

Operating Temperature Range T

Storage Temperature Range T

Thermal Package Resistances

Thermal Resistance, 8L-DFN (3×3) θ Thermal Resistance, 8L-MSOP θ

Note 1: Operation must not cause T

to exceed the Absolute Maximum Junction Temperature specification (+150°C).

J

A

JA

-40 — +125 °C

-40 — +125 Note 1

-65 — +150

—57 — °C/W

—211 —

1.3 Timing Diagrams

V

DD

V

OUT

1.001 V

REF

0.999 V

REF

0V

1.8V to 5.5V

1.8V

t

STR

V

OUT

t

IRC

V

CM

V

IVH

+0.5V

VDD–1V

V

REF

t

IRC

V

IVL

–0.5V

1V

V

REF

V

OUT

t

IRD

V

REF

GDMV

DM

1V

0V

V

REF

G

MINVDMH

+0.5V

V

OH

t

IRD

VDD–1V

0V

V

REF

G

MINVDML

–0.5V

V

OL

V

OUT

t

OR

V

REF

G

MINVDM

VDD–1V

0V

V

REF

1.5V

V

OH

t

OR

1V

0V

V

REF

-1.5V

V

OL

V

OUT

t

PHL

V

DD

V

PRL

–0.1V

High Z

1.8V

t

PLH

V

PRH

+0.1V

0V

High Z

V

OUT

t

OFF

EN

High Z

t

ON

t

ENLH

t

ENHL

High Z

FIGURE 1-1: Amplifier Start-Up Timing Diagram.

FIGURE 1-2: Common Mode Input Overdrive Recovery Timing Diagram.

MCP6N16

FIGURE 1-3: Differential Mode Input Overdrive Recovery Timing Diagram.

FIGURE 1-4: Output Overdrive Recovery Timing Diagram.

FIGURE 1-5: POR Timing Diagram.

FIGURE 1-6: EN Timing Diagram .

 2014 Microchip Technology Inc. DS20005318A-page 13

MCP6N16

R

G

R

F

R

L

100 nF

V

DD

2.2 µF

V

REF

V

L

31.6 kΩ

V

M

10 µF

C

CNT

U

1

MCP6N16

U

2

MCP6H01

V

CNT

31.6 kΩ

R

CNT

31.6 kΩ

V

OUT

2.2 nF

100Ω

V

CM

2.2 nF

100Ω

G

DM

1RFR

G



+=

V

OUTVCNT

=

V

M

V

REFGDM

1g

E

+V

E

+=

G

DM

1RFR

G



+=

V

M

V

REF

G+

DM

1g

E

+V

DMVE

+=

V

OUT

V

REFGDM

1g

E

+V

DMVE

++=

R

L

63.4 kΩ

100Ω

VCM+VDM/2

1.0 µF

V

OUT

R

F

R

G

V

M

100 nF

V

DD

2.2 µF

V

REF

V

L

VCM–VDM/2

U

1

MCP6N16

1.4 DC Test Circuits

1.4.1 INPUT OFFSET TEST CIRCUIT

Figure 1-7 is a simple circuit that can test the INA’s

input offset errors and input voltage range (V

; see Section 1.5.1 “Input Offset Related

V

IVH

Errors” and Section 1.5.2 “Input Offset Common Mode Nonlinearity”). U2 is part of a control loop that

forces V

to equal V

OUT

; U1 can be set to any bias

CNT

point.

, V

and

E

IVL

1.4.2 DIFFERENTIAL GAIN TEST CIRCUIT

Figure 1-8 is a simple circuit that can test the INA’s

differential gain error, nonlinearity and input voltage range (g

, INLDM, V

E

“Differential Gain Error and Nonlinearity”). R

are 0.01% for accurate gain error measurements.

R

G

The output voltages are (where V offset errors and g

and V

DML

is the gain error):

E

DMH

; see Section 1.5.3

and

F

is the sum of input

E

EQUATION 1-2:

FIGURE 1-7: Simple Test Circuit for Common Mode (Input Offset).

When MCP6N16 is in its normal range of operation, the DC output voltages are (where V offset errors and g

is the gain error):

E

is the sum of input

E

EQUATION 1-1:

Table 1-5 shows the resulting behavior for different

options.

G

MIN

TABLE 1-5: RESULTS

G (V/V)

Nom.

100 68 8.7

DS20005318A-page 14  2014 Microchip Technology Inc.

R

MIN

F

(kΩ) Typ.

1 100 1.00 85 0.50 0.50

10 402 4.02 88 1.2

G

DM

(kV/V)

Typ.

G

DMVOS

(±mV)

Max.

BW

(kHz)

Typ .

at V

OUT

BW (Hz) Typ .

at V

M

FIGURE 1-8: Simple Test Circuit for Differential Mode.

For different values of V ranges to keep V

REF

Table 1-6 shows the recommended R

produce a 10 kΩ load. V

, VDM sweeps over different

REF

, VFG and V

can usually be left open.

L

within their ranges.

OUT

and RG; they

F

TABLE 1-6: SELECTING RF AND R

G

MIN

(V/V)

Nom.

R

F

(kΩ)

Nom.

1 0 Open 1.0000

10 10.0 || 90.9 1.00 10.009

100 10.0 || 1000 100 100.01

R

G

(kΩ)

Nom.

1.4.3 DYNAMIC TESTING OF INPUT BEHAVIOR

The circuit in Figure 1-8 can test the input’s dynamic

, t

behavior (i.e., IMD, t measure the output at V

STR

STL

, instead of at VM.

OUT

IRC

, t

IRD

G

DM

(V/V)

Nom.

and tOR);

1.5 Explanation of DC Error

V

E

VMV

REF

–GDM1g

E

+



=

Where:

PSRR, CMRR, CMRR2 and A

OL

are in

units of V/V

∆T

A

is in units of °C

TC

1

is in units of V/°C

V

DM

=0

V

E

V

OS



V

DD



VSS–

PSRR

---------------------------------



V

CM

CMRR

-----------------



V

REF

CMRR2

--------------------+++=



V

OUT

A

OL

-----------------TATC

1



++

V

1

V

3

VE, V

E_LIN

(V)

VCM (V)

V

IVL

V

IVH

VDD/2

V

2

V

E_LIN

V

E

V

E

Where:

V

E_LINVOS

VCMVDD2



–CMRR



+=

V

OSV2

=

1CMRR



V3V1–V

IVHVIVL

–



=

Where:

INL

CMH

maxVEV

IVHVIVL

–



=



VEVEV

E_LIN

–=

INL

CML

minVEV

IVHVIVL

–



=

INL

CM

INL

CMH

INL

CMH

INL

CML



=

INL

CML

otherwise



=

V

E_LIN2

V

OSVREFVDD

2



–CMRR2



+=

INL

CMH2

maxVE2V

IVHVIVL

–



=

INL

CML2

minVE2V

IVHVIVL

–



=

Where:



V

E2VEVE_LIN2

–=

INL

CM2

INL

CMH2

INL

CMH2

INL

CML2



=

INL

CML2

otherwise



=

Specifications

1.5.1 INPUT OFFSET RELATED ERRORS

The input offset error (VE) is extracted from input offset measurements (see Section 1.4.1 “Input Offset Test

Circuit”), based on Equation 1-1:

EQUATION 1-3:

VE has several terms, which assume a linear response to changes in V

, VSS, VCM, V

DD

are in their specified ranges):

EQUATION 1-4:

and TA (all of which

OUT

MCP6N16

FIGURE 1-9: Input Offset Error vs. Common Mode Input Voltage.

Based on the measured VE data, we obtain the following linear fit:

EQUATION 1-5:

Equation 1-2 shows how VE affects V

1.5.2 INPUT OFFSET COMMON MODE

The input offset error (VE) changes nonlinearly with

. Figure 1-9 shows VE vs. VCM, as well as a linear

V

CM

fit line (V standard conditions (∆V swept from V

Section 1.4.1 “Input Offset Test Circuit” and V

calculated using Equation 1-3.

 2014 Microchip Technology Inc. DS20005318A-page 15

NONLINEARITY

) based on VOS and CMRR. The INA is in

E_LIN

to V

IVL

.

OUT

=0, VDM=0, etc.). VCM is

OUT

. The test circuit is in

IVH

The remaining error (∆VE) is described by the Common Mode Nonlinearity spec:

EQUATION 1-6:

is

E

The same common mode behavior applies to VE when

is swept, instead of VCM, since both input stages

V

REF

are designed the same:

EQUATION 1-7:

MCP6N16

G

DM

1RFR

G



+=

V

M

GDM1g

E

+V

DM

V+

E

=

V

EDVMGDM

 VDM–=

V

1

V

3

VED, V

ED_LIN

(V)

V

DM

(V)

V

DML

V

DMH

0

V

2

V

ED_LIN

V

ED

V

ED

Where:

V

ED_LIN

1g

E

+VEgEV

DM

+=

g

E

V3V1–V

DMHVDML

–



1–=

V

E

V21g

E

+



=

Where:

INL

DMH

max VEDV

DMHVDML

–=

V

ED

VEDV

ED_LIN

–=

INL

DML

min VEDV

DMHVDML

–=

INL

DM

INL

DMH

INL

DMH

INL

DML

=

INL

DML

otherwise=

1.5.3 DIFFERENTIAL GAIN ERROR AND NONLINEARITY

The differential errors are extracted from differential gain measurements (see Section 1.4.2 “Differential

Gain Test Circuit”), based on Equation 1-2. These

errors are the differential gain error (g offset error (V

, which changes nonlinearly with VDM):

E

) and the input

E

EQUATION 1-8:

These errors are adjusted for the expected output, then referred back to the input, giving the differential input error (VED) as a function of VDM:

EQUATION 1-9:

Figure 1-10 shows VED vs. VDM, as well as a linear fit

line (V standard conditions (∆V from V

) based on VED and gE. The INA is in

ED_LIN

to V

DML

DMH

.

=0, etc.). VDM is swept

OUT

EQUATION 1-11:

FIGURE 1-10: Differential Input Error vs. Differential Input Voltage.

Based on the measured VED data, we obtain the following linear fit:

EQUATION 1-10:

Note that the VE value measured here is not as accurate as the one obtained in Section 1.5.1 “Input

Offset Related Errors”.

The remaining error (∆V Differential Nonlinearity spec:

DS20005318A-page 16  2014 Microchip Technology Inc.

ED

) is described by the

MCP6N16

30%

G

MIN

= 1

25%

ence

s

28 Samples

TA= +25°C NPBW = 3 mHz

20%

ccur

r

15%

ge of

O

VDD=1.8V

VDD= 5.5V

10%

rcent

a

5%

P

e

0%

-12-10-8-6-4-2 0 2 4 6 8 1012 Input Offset Voltage (µV)

0%

5%

10%

15%

20%

25%

30%

35%

40%

45%

Percentage of Occurrences

G

MIN

= 10 28 Samples T

A

= +25°C

NPBW = 3 mHz

VDD= 5.5V

VDD= 1.8V

0%

10%

20%

30%

40%

50%

60%

Percentage of Occurrences

G

MIN

= 100 28 Samples T

A

= +25°C

NPBW = 3 mHz

VDD= 5.5V

VDD= 1.8V

40%

G

MIN

= 1

30%

35%

ence

s

28 Samples

TA= -40 to +125°C NPBW = 3 mHz

25%

ccur

r

VDD= 1.8V

15

%

20%

ge of

O

VDD=5.5V

10%

%

rcent

a

5%

P

e

0%

-600 -400 -200 0 200 400 600 Input Offset Voltage Drift; TC

1

(nV/°C)

40%

G

MIN

= 10

30%

35%

ence

s

28 Samples

TA= -40 to +125°C NPBW = 3 mHz

25%

ccur

r

VDD= 5.5V

15

%

20%

ge of

O

VDD=1.8V

10%

%

rcent

a

5%

P

e

0%

-40 -30 -20 -10 0 10 20 30 40 Input Offset Voltage Drift; TC

1

(nV/°C)

40%

G

MIN

= 100

30%

35%

ence

s

28 Samples

TA= -40 to +125°C NPBW = 3 mHz

25%

ccur

r

15

%

20%

ge of

O

VDD= 5.5VVDD= 1.8V

10%

%

rcent

a

5%

P

e

0%

-16 -12 -8 -4 0 4 8 12 16 Input Offset Voltage Drift; TC

1

(nV/°C)

2.0 TYPICAL PERFORMANCE CURVES

Note: The graphs and tables provided following this note are a statistical summary based on a limited number of

samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range.

Note: Unless otherwise indicated, TA=+25°C, VDD= 1.8V to 5.5V, VSS=GND, VCM=VDD/2, VDM=0V, V

REF=VDD

2.1 DC Precision

/2, VL=VDD/2, RL=10kΩ to VL, CL=60pF, GDM=G

and EN = VDD; see Figures 1-7 and 1-8.

MIN

FIGURE 2-1: Input Offset Voltage, with G

=1.

MIN

-2.0 -1.6 -1.2 -0.8 -0.4 0.0 0.4 0.8 1.2 1.6 2.0 Input Offset Voltage (µV)

FIGURE 2-2: Input Offset Voltage, with G

= 10.

MIN

FIGURE 2-4: Input Offset Voltage Drift, with G

MIN

=1.

FIGURE 2-5: Input Offset Voltage Drift, with G

MIN

=10.

FIGURE 2-3: Input Offset Voltage, with G

 2014 Microchip Technology Inc. DS20005318A-page 17

-1.0 -0.6 -0.2 0.2 0.6 1.0 1.4 1.8 2.2 2.6 3.0

= 100.

MIN

Input Offset Voltage (µV)

FIGURE 2-6: Input Offset Voltage Drift, with G

MIN

=100.

MCP6N16

50%

55%

s

G

MIN

= 1

40%

45%

rrenc

e

28 Samples

TA= -40 to +125°C NPBW = 3 mHz

30%

35%

Occu

VDD= 1.8V

20%

25%

age o

f

VDD=5.5V

10%

15%

ercen

t

0%

5%

P

-

1200-800-4000400

800

1200

Quadratic Input Offset Voltage Drift;

TC

2

(pV/°C2)

30%

s

G

MIN

= 10

25%

rrenc

e

28 Samples

TA= -40 to +125°C NPBW = 3 mHz

20%

Occu

=

10%

15%

age o

f

VDD1.8V

VDD= 5.5V

5%

ercen

t

0%

P

-

160-120-80-4004080120

160

Quadratic Input Offset Voltage Drift;

TC

2

(pV/°C2)

4

45%

s

G

MIN

= 100

28 Sam

p

les

35%

40%

rrenc

e

p

TA= -40 to +125°C NPBW = 3 mHz

25%

30%

Occu

VDD= 5.5V V

DD

= 1.8V

15%

20%

age o

f

10%

ercen

t

0%

5%

P

-

120-100-80-60-40-20020

40

Quadratic Input Offset Voltage Drift;

TC

2

(pV/°C2)

25

30

Representative Part

=

15

20

(µV)

G

MIN

1

NPBW = 2 Hz

5

10

oltag

e

-5

0

ffset

V

-15

-10

put

O

VDD= 1.8V

VDD= 5.5V

-25

-

20

I

n

-

30

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Output Voltage (V)

25

30

Representative Part

=

15

20

(µV)

G

MIN

10

NPBW = 2 Hz

5

10

oltag

e

-5

0

ffset

V

VDD= 1.8V

VDD= 5.5V

-15

-10

put

O

-25

-

20

I

n

-

30

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Output Voltage (V)

25

30

Representative Part

=

15

20

(µV)

G

MIN

100

NPBW = 2 Hz

5

10

oltag

e

-5

0

ffset

V

VDD= 1.8V

VDD= 5.5V

-15

-10

put

O

-25

-

20

I

n

-

30

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Output Voltage (V)

Note: Unless otherwise indicated, TA=+25°C, VDD= 1.8V to 5.5V, VSS=GND, VCM=VDD/2, VDM=0V, V

REF=VDD

/2, VL=VDD/2, RL=10kΩ to VL, CL=60pF, GDM=G

and EN = VDD; see Figures 1-7 and 1-8.

MIN

FIGURE 2-7: Quadratic Input Offset Voltage Drift, with G

MIN

=1.

FIGURE 2-8: Quadratic Input Offset Voltage Drift, with G

MIN

=10.

FIGURE 2-10: Input Offset Voltage vs. Output Voltage, with G

MIN

=1.

FIGURE 2-11: Input Offset Voltage vs. Output Voltage, with G

MIN

=10.

FIGURE 2-9: Quadratic Input Offset Voltage Drift, with G

DS20005318A-page 18  2014 Microchip Technology Inc.

MIN

= 100.

FIGURE 2-12: Input Offset Voltage vs. Output Voltage, with G

MIN

= 100.

Datasheet MCP6N16 Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

Zero-Drift Instrumentation Amplifier

Features:

Description:

Typical Application Circuit

Typical Applications:

Design Aids:

Package Types

Minimum Gain Options

TABLE 1: KEY DIFFERENTIATING SPECIFICATIONS

1.0 ELECTRICAL CHARACTERISTICS

1.1 Absolute Maximum Ratings †

1.2 Specifications

TABLE 1-1: DC ELECTRICAL SPECIFICATIONS

TABLE 1-2: AC ELECTRICAL SPECIFICATIONS

TABLE 1-3: DIGITAL ELECTRICAL SPECIFICATIONS

TABLE 1-4: TEMPERATURE SPECIFICATIONS

1.3 Timing Diagrams

FIGURE 1-1: Amplifier Start-Up Timing Diagram.

FIGURE 1-2: Common Mode Input Overdrive Recovery Timing Diagram.

FIGURE 1-3: Differential Mode Input Overdrive Recovery Timing Diagram.

FIGURE 1-4: Output Overdrive Recovery Timing Diagram.

FIGURE 1-5: POR Timing Diagram.

FIGURE 1-6: EN Timing Diagram .

1.4 DC Test Circuits

FIGURE 1-7: Simple Test Circuit for Common Mode (Input Offset).

TABLE 1-5: RESULTS

FIGURE 1-8: Simple Test Circuit for Differential Mode.

FIGURE 1-9: Input Offset Error vs. Common Mode Input Voltage.

FIGURE 1-10: Differential Input Error vs. Differential Input Voltage.

2.0 TYPICAL PERFORMANCE CURVES

2.1 DC Precision