Datasheet MCP6N16 Datasheet

MCP6N16

V

OUT

20 kΩ

100Ω

2.49 kΩ

68.1Ω

RTD

4.99 kΩ

V

DD

MCP6N16-100

10 µF

100Ω

EN

100Ω

RTD Temperature Sensor

4.99 kΩ 4.99 kΩ

MCP6N16

MSOP

V

IP

V

IM

V

SS

V

OUT

V

FG

1

2

3

4

8

7

6

5

V

REF

V

DD

EN

MCP6N16

3×3 DFN *

V

IP

V

IM

V

SS

V

OUT

V

FG

1

2

3

4

8

7

6

5

V

REF

V

DD

EN

* Includes Exposed Thermal Pad (EP); see Table 3-1.

EP

9

Zero-Drift Instrumentation Amplifier

Features:

• High DC Precision:

-V

: ±17 µV (maximum, G

OS

-TC1: ±60 nV/°C (maximum, G

- CMRR: 112 dB (minimum, G =5.5V)

V

DD

- PSRR: 110 dB (minimum, G =5.5V)

V

DD

: ±0.15% (maximum, G

-g

E

• Flexible:

- Minimum Gain (G

) Options:

MIN

1, 10 and 100 V/V

- Rail-to-Rail Input and Output

- Gain Set by Two External Resistors

• Bandwidth: 500 kHz (typical, Gain = G

• Power Supply:

-VDD: 1.8V to 5.5V

-I

: 1.1 mA (typical)

Q

- Power Savings (Enable) Pin: EN

• Enhanced EMI Protection:

- Electromagnetic Interference Rejection Ratio

(EMIRR): 111 dB at 2.4 GHz

• Extended Temperature Range: -40°C to +125°C

MIN

= 10, 100)

MIN

= 100)

= 100,

=100,

MIN

=1, 10)

Description:

Microchip Technology Inc. offers the single Zero-Drift MCP6N16 instrumentation amplifier (INA) with Enable pin (EN) and three minimum gain options (G

MIN

). The internal offset correction gives high DC precision: it has very low offset and offset drift, and negligible 1/f noise.

Two external resistors set the gain, minimizing gain error and drift over temperature. The reference voltage

) shifts the output voltage (V

(V

REF

OUT

).

The MCP6N16 is designed for single-supply operation, with rail-to-rail input (no common mode crossover distortion) and output performance. The supply voltage range (1.8V to 5.5V) is low enough to support many portable applications. All devices are fully specified from -40°C to +125°C. Each part has EMI filters at the input pins, for good EMI rejection (EMIRR).

These parts have three minimum gain options (1, 10 and 100 V/V). This allows the user to optimize the input offset voltage and input noise for different applications.

Typical Application Circuit

Typical Applications:

• High-Side Current Sensor

• Wheatstone Bridge Sensors

• Difference Amplifier with Level Shifting

• Power Control Loops

Design Aids:

• SPICE Macro Model

• Microchip Advanced Part Selector (MAPS)

• Application Notes

 2014 Microchip Technology Inc. DS20005318A-page 1

Package Types

MCP6N16

-1

0

10

20

30

40

ffset Voltage (µV)

-40

-30

-20

0

-50 -25 0 25 50 75 100 125

Input

O

Ambient Temperature (°C)

G

MIN

= 1 28 Samples V

DD

= 5.5V

V

CM

= VDD/2

NPBW = 3 mHz

4

2

3

(µV)

1

oltag

e

-1

0

ffset

V

-2

nput

O

G

MIN

= 10

28 Samples

-3

I

V

DD

=5.

5V

VCM= VDD/2 NPBW = 3 mHz

-

4

-50 -25 0 25 50 75 100 125 Ambient Temperature (°C)

4

2

3

(µV)

1

oltag

e

-1

0

ffset

V

-2

nput

O

G

MIN

= 100

28 Samples

-3

I

VDD=5.5V

VCM= VDD/2 NPBW = 3 mHz

-

4

-50 -25 0 25 50 75 100 125 Ambient Temperature (°C)

Minimum Gain Options

Table 1 shows key specifications that differentiate

between the different minimum gain (G See Section 1.0 “Electrical Characteristics”,

Section 6.0 “Packaging Information” and Product

Identification System for further information on G

TABLE 1: KEY DIFFERENTIATING SPECIFICATIONS

G

V

MIN

Part No.

(V/V)

Nom.

MCP6N16-001 1 85 1800 89 91 2.7 0.50 19 900

MCP6N16-010 10 22 180 103 104 0.27 5.0 2.2 105

MCP6N16-100 100 17 60 112 110 0.027 35 0.93 45

Note 1: G

is the minimum stable gain (GDM), for a given part option. In other words, GDM≥ G

MIN

Figures 1 to 3 show input offset voltage versus

temperature for the three gain options (G 100 V/V).

OS

(±μV)

Max.

TA= -40 to +125°C

MIN

TC

1

(±nV/°C)

Max.

MIN

) options.

.

MIN

=1, 10,

CMRR

(dB) Min.

VDD=5.5V

PSRR

(dB) Min.

V

DMH

(V)

Min.

GBWP

(MHz)

Typ.

E

ni

(μV

)

P-P

Typ .

f = 0.1 to 10 Hz

.

MIN

(nV/√Hz)

Typ .

f < 500 Hz

e

ni

FIGURE 1: Input Offset Voltage vs. Temperature, with G

FIGURE 2: Input Offset Voltage vs. Temperature, with G

DS20005318A-page 2  2014 Microchip Technology Inc.

MIN

=1.

=10.

FIGURE 3: Input Offset Voltage vs. Temperature, with G

MIN

= 100.

 2014 Microchip Technology Inc. DS20005318A-page 3

1.0 ELECTRICAL CHARACTERISTICS

1.1 Absolute Maximum Ratings †

VDD–VSS ............................................................................................................................................................................................................................................ 6.5V

Current at Input Pins (Note 1) ........................................................................................................................................................................................................... ±2 mA

Analog Inputs (V

All Other Inputs and Outputs ............................................................................................................................................................................... V

Difference Input Voltage .............................................................................................................................................................................................................|V

Output Short-Circuit Current ...................................................................................................................................................................................................... Continuous

Current at Output and Supply Pins .................................................................................................................................................................................................. ±30 mA

Storage Temperature ......................................................................................................................................................................................................... -65°C to +150°C

Maximum Junction Temperature ......................................................................................................................................................................................................+150°C

ESD protection on all pins (HBM, MM)..................................................................................................................................................................................... ≥ 4kV,400V

† Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

Note 1: See Section 4.3.1.2 “Input Voltage Limits” and Section 4.3.1.3 “Input Current Limits”.

and VIM) (Note 1) .................................................................................................................................................................. VSS– 1.0V to VDD+1.0V

IP

– 0.3V to VDD+0.3V

SS

DD–VSS

|

MCP6N16

DS20005318A-page 4  2014 Microchip Technology Inc.

1.2 Specifications

MCP6N16

TABLE 1-1: DC ELECTRICAL SPECIFICATIONS

Electrical Characteristics: Unless otherwise indicated, TA=+25°C, VDD= 1.8V to 5.5V, VSS= GND, VCM=VDD/2, VDM=0V, V

to V

, GDM=G

L

and EN = VDD; see Figures 1-7 and 1-8 (Note 1).

MIN

Parameters Sym. Min. Typ. Max. Units G

REF=VDD

MIN

Input Offset

Input Offset Voltage V

OS

-85 — +85 µV 1 TA=+25°C

-22 — +22 10

-17 — +17 100

Input Offset Voltage Drift – Linear Temp. Co.

TC

1

-1800 — +1800 nV/°C 1 TA= -40°C to +125°C (Note 2)

-180 — +180 10

-60 — +60 100

Input Offset Voltage Drift – Quadratic Temp. Co.

TC

2

—±560—pV/°C

—±63— 10

2

1TA= -40°C to +125°C

—±69— 100

Input Offset Aging ∆V

OS

— ±1.0 — µV 1 408 hr Life Test at +150°C,

—±0.8— 10

—±0.7— 100

Power Supply Rejection Ratio PSRR 91 109 — dB 1

104 122 — 10

110 128 — 100

Output Offset

Output Offset Voltage V

OSO

0µVall

Input Current and Impedance (Note 3)

Input Bias Current I

B

-100 ±2 +100 pA all

Across Temperature — 20 — TA=+85°C

Across Temperature 0 250 2000 TA=+125°C

Note 1: V

=(VIP+VIM)/2, VDM=(VIP–VIM) and GDM=1+RF/RG.

CM

2: For Design Guidance only; not tested. 3: These specifications apply to the V 4: This specification applies to the V 5: Figures 2-52 and 2-53 show the V

, VIM input pair (use VCM) and to the V

IP

, VIM, V

IP

, V

IVL

and VFG pins individually.

REF

, V

DML

and V

DMH

IVH

variation over temperature.

, VFG input pair (use V

REF

instead).

REF

6: See Section 1.5 “Explanation of DC Error Specifications”.

/2, VL=VDD/2, RL=10kΩ

Conditions

measured at +25°C

 2014 Microchip Technology Inc. DS20005318A-page 5

TABLE 1-1: DC ELECTRICAL SPECIFICATIONS (CONTINUED)

Electrical Characteristics: Unless otherwise indicated, TA=+25°C, VDD= 1.8V to 5.5V, VSS= GND, VCM=VDD/2, VDM=0V, V

to VL, GDM=G

and EN = VDD; see Figures 1-7 and 1-8 (Note 1).

MIN

Parameters Sym. Min. Typ. Max. Units G

Input Offset Current I

OS

-800 ±300 +800 pA all

Across Temperature — ±320 — TA=+85°C

Across Temperature -1500 ±350 +1500 T

Common Mode Input Impedance Z

Differential Input Impedance Z

Input Common Mode Voltage (V

CM

or V

) (Note 3)

REF

Input Voltage Range (Note 4, Note 5) V

DIFF

V

CM

IVL

IVH

—10

—V

VDD+0.15 VDD+0.30 —

13

||10 — Ω||pF

13

||4 —

–0.25 VSS–0.15 V all

SS

Common Mode Rejection Ratio CMRR 80 98 — dB 1 V

94 112 — 10

103 121 — 100

89 107 — 1 V

103 121 — 10

112 130 — 100

Common Mode Rejection Ratio at V

REF

CMRR2 83 101 — dB 1 V

98 116 — 10

102 120 — 100

94 112 — 1 V

109 127 — 10

115 133 — 100

Note 1: V

=(VIP+VIM)/2, VDM=(VIP–VIM) and GDM=1+RF/RG.

CM

2: For Design Guidance only; not tested. 3: These specifications apply to the V 4: This specification applies to the V 5: Figures 2-52 and 2-53 show the V

, VIM input pair (use VCM) and to the V

IP

, VIM, V

IP

, V

IVL

and VFG pins individually.

REF

, V

DML

and V

DMH

IVH

variation over temperature.

, VFG input pair (use V

REF

instead).

REF

6: See Section 1.5 “Explanation of DC Error Specifications”.

REF=VDD

MIN

=+125°C

A

CM=VIVL

REF

V

DD

REF

V

DD

/2, VL=VDD/2, RL=10kΩ

Conditions

to V

, VDD=1.8V

IVH

, VDD=5.5V

IVH

= 0.2V to VDD–0.2V,

=1.8V

= 0.2V to VDD–0.2V,

=5.5V

MCP6N16

DS20005318A-page 6  2014 Microchip Technology Inc.

TABLE 1-1: DC ELECTRICAL SPECIFICATIONS (CONTINUED)

Electrical Characteristics: Unless otherwise indicated, TA=+25°C, VDD= 1.8V to 5.5V, VSS= GND, VCM=VDD/2, VDM=0V, V

to VL, GDM=G

Common Mode Nonlinearity (Note 6) INL

and EN = VDD; see Figures 1-7 and 1-8 (Note 1).

MIN

Parameters Sym. Min. Typ. Max. Units G

CM

-550 — +550 ppm 1 VCM=V

REF=VDD

MIN

/2, VL=VDD/2, RL=10kΩ

Conditions

IVL

to V

, VDD=1.8V

IVH

MCP6N16

-75 — +75 10

-20 — +20 100

-310 — +310 1 V

CM=VIVL

to V

, VDD=5.5V

IVH

-35 — +35 10

-10 — +10 100

Input Differential Voltage (V

Differential Input Voltage Range (Note 5) V

Differential Gain Error (Note 6) g

Note 1: V

=(VIP+VIM)/2, VDM=(VIP–VIM) and GDM=1+RF/RG.

CM

) (Note 3)

DM

V

DML

DMH

E

— -3.4/G

+2.7/G

MIN

+3.4/G

MIN

—±0.03—%1V

— ±0.02 — % 10, 100

—±0.03— 1V

— ±0.02 — 10, 100

-2.7/G

MIN

—V

VallVDD≥ 2.9V, V

V

within ±0.2%

OUT

≥ 2.9V, V

DD

within ±0.2%

V

OUT

= 1.8V, V

DD

=±(0.7V)/G

V

DM

= 5.5V, V

DD

V

= ±(2.55V)/G

DM

-0.25 ±0.04 +0.25 % 1 VDD= 5.5V, V = 0 to (2.7V)/G

V

-0.15 ±0.02 +0.15 % 10, 100

-0.25 ±0.04 +0.25 % 1 V

-0.15 ±0.02 +0.15 % 10, 100

DM

= 5.5V, V

DD

= 0 to (-2.7V)/G

V

DM

REF=VDD

=0V,

REF

REF=VDD

MIN

REF=VDD

MIN

=0.2V,

REF

MIN

=5.3V,

REF

MIN

,

/2,

2: For Design Guidance only; not tested. 3: These specifications apply to the V 4: This specification applies to the V 5: Figures 2-52 and 2-53 show the V

, VIM input pair (use VCM) and to the V

IP

, VIM, V

IP

, V

IVL

and VFG pins individually.

REF

, V

DML

and V

DMH

IVH

variation over temperature.

, VFG input pair (use V

REF

instead).

REF

6: See Section 1.5 “Explanation of DC Error Specifications”.

 2014 Microchip Technology Inc. DS20005318A-page 7

TABLE 1-1: DC ELECTRICAL SPECIFICATIONS (CONTINUED)

Electrical Characteristics: Unless otherwise indicated, TA=+25°C, VDD= 1.8V to 5.5V, VSS= GND, VCM=VDD/2, VDM=0V, V

to VL, GDM=G

Differential Gain Drift (Note 6) ∆gE/∆T

Differential Nonlinearity (Note 6) INL

DC Open-Loop Gain A

Note 1: V

2: For Design Guidance only; not tested. 3: These specifications apply to the V 4: This specification applies to the V 5: Figures 2-52 and 2-53 show the V 6: See Section 1.5 “Explanation of DC Error Specifications”.

and EN = VDD; see Figures 1-7 and 1-8 (Note 1).

MIN

Parameters Sym. Min. Typ. Max. Units G

A

— ±3 — ppm/°C all VDD= 1.8V, V

—±4— V

—±3— V

DM

—±300—ppmallV

—±150— V

—±300— V

OL

84 102 — dB 1 VDD=1.8V,

100 118 — 10

108 126 — 100

95 113 — 1 V

111 129 — 10

119 137 — 100

=(VIP+VIM)/2, VDM=(VIP–VIM) and GDM=1+RF/RG.

CM

, VIM input pair (use VCM) and to the V

IP

, VIM, V

IP

, V

IVL

and VFG pins individually.

REF

, V

DML

and V

DMH

IVH

variation over temperature.

, VFG input pair (use V

REF

instead).

REF

REF=VDD

MIN

/2, VL=VDD/2, RL=10kΩ

Conditions

=±(0.7V)/G

V

DM

= 5.5V, V

DD

= ±(2.55V)/G

V

DM

= 5.5V, V

DD

V

= 0 to (2.7V)/G

DM

= 5.5V, V

DD

= 0 to (-2.7V)/G

V

DM

= 1.8V, V

DD

=±(0.7V)/G

V

DM

= 5.5V, V

DD

V

= ±(2.55V)/G

DM

= 5.5V, V

DD

= 0 to (2.7V)/G

V

DM

= 5.5V, V

DD

= 0 to (-2.7V)/G

V

DM

V

= 0.2V to 1.6V

OUT

=5.5V,

DD

V

= 0.2V to 5.3V

OUT

REF=VDD

MIN

REF=VDD

MIN

=0.2V,

REF

=5.3V,

REF

REF=VDD

MIN

REF=VDD

MIN

=0.2V,

REF

=5.3V,

REF

/2,

MIN

/2,

MIN

MCP6N16

DS20005318A-page 8  2014 Microchip Technology Inc.

TABLE 1-1: DC ELECTRICAL SPECIFICATIONS (CONTINUED)

Electrical Characteristics: Unless otherwise indicated, TA=+25°C, VDD= 1.8V to 5.5V, VSS= GND, VCM=VDD/2, VDM=0V, V

to VL, GDM=G

and EN = VDD; see Figures 1-7 and 1-8 (Note 1).

MIN

Parameters Sym. Min. Typ. Max. Units G

REF=VDD

MIN

/2, VL=VDD/2, RL=10kΩ

Conditions

MCP6N16

Output

Minimum Output Voltage Swing V

Maximum Output Voltage Swing V

OL

OH

—V

+3 — mV all RL=10kΩ, VDD=1.8V,

SS

+6 — RL=10kΩ, VDD=5.5V,

SS

+60 VSS+ 250 RL=1kΩ, VDD=5.5V,

SS

–3 — mV RL=10kΩ, VDD=1.8V,

DD

–6 — RL=10kΩ, VDD=5.5V,

DD

V

=-VDD/(2G

DM

V

REF=VDD

V

=-VDD/(2G

DM

V

REF=VDD

V

=-VDD/(2G

DM

V

REF=VDD

V

DM=VDD

V

REF=VDD

V

DM=VDD

V

REF=VDD

/2 – 0.9V

/2 – 1V

/(2G

MIN

/2 + 0.9V

/(2G

MIN

/2 + 1V

MIN

),

VDD–250 VDD–60 — RL=1kΩ, VDD=5.5V,

Output Short-Circuit Current I

SC

V

DM=VDD

V

REF=VDD

—±10—mAV

—±35— V

DD

=1.8V

=5.5V

/(2G

MIN

/2 + 1V

),

Power Supply

Supply Voltage V

Quiescent Current per Amplifier I

POR Trip Voltage V

V

Note 1: V

=(VIP+VIM)/2, VDM=(VIP–VIM) and GDM=1+RF/RG.

CM

DD

Q

PRL

PRH

1.8 — 5.5 V all

0.5 1.1 1.6 mA IO=0

0.9 1.27 — V

—1.331.6V

2: For Design Guidance only; not tested. 3: These specifications apply to the V 4: This specification applies to the V 5: Figures 2-52 and 2-53 show the V

, VIM input pair (use VCM) and to the V

IP

, VIM, V

IP

, V

IVL

and VFG pins individually.

REF

, V

DML

and V

DMH

IVH

variation over temperature.

, VFG input pair (use V

REF

instead).

REF

6: See Section 1.5 “Explanation of DC Error Specifications”.

 2014 Microchip Technology Inc. DS20005318A-page 9

TABLE 1-2: AC ELECTRICAL SPECIFICATIONS

Electrical Characteristics: Unless otherwise indicated, TA= +25°C, VDD= 1.8V to 5.5V, VSS= GND, VCM=VDD/2, VDM=0V, V

R

=10kΩ to VL, CL= 60 pF, GDM=G

L

Parameters Sym.

and EN = VDD; see Figures 1-7 and 1-8.

MIN

Min.

Typ.

Max.

Units G

MIN

REF=VDD

Conditions

AC Response

Gain-Bandwidth Product GBWP — 0.5 — MHz 1

—5 — 10

— 35 — 100

Phase Margin PM — 70 — ° all

Open-Loop Output Impedance R

OL

—1.6 —kΩ

Power Supply Rejection Ratio PSRR — 80 — dB 1 f = 1 kHz

—98 — 10

— 123 — 100

Common Mode Rejection Ratio

and V

at V

CM

REF

CMRR, CMRR2 — 83 — dB 1 f = 10 kHz

—80 — 10

— 140 — 100

Step Response (see Section 4.1.4 “AC Performance”)

Slew Rate SR Note 1 V/µs all

Start-Up Time t

STR

—2 —ms1GDM= 1000, VDD power up to 0.1% V

—0.3 — 10

— 0.2 — 100

Overdrive Recovery,

Input Common Mode

Overdrive Recovery,

Input Differential Mode

Overdrive Recovery, Output t

t

IRC

t

IRD

OR

—1 —µsallVIP=VIM=V

90% of V

—10 — G

MINVDM=GMINVDMH

= 1V (or VDD– 1V), 90% of V

V

REF

—180 — GDMVDM= 1.5V to 0V (or -1.5V to 0V),

V

REF=VDD

+ 0.5V to VDD– 1V (or V

IVH

change (IB≤ 2mA) (Note 4)

OUT

+ 0.5V to 0V (or G

– 1V (or 1V), 90% of V

OUT

Note 1: The slew rate is limited by the GBWP; the large signal step response is dominated by the small signal bandwidth.

2: These parameters were characterized using the circuit in Figure 1-8. In Figures 2-75 and 2-76, there is an IMD tone at DC, a residual tone at 100 Hz and

other IMD tones and clock tones.

3: High gains behave differently; see Section 4.4.4 “Offset at Power-Up”.

, t

4: t

STR

STL

IRC

and tOR include some uncertainty due to clock edge timing.

IRD

/2, VL=VDD/2,

settling (Note 3, Note 4)

OUT

– 0.5V to 1V),

IVL

MINVDML

– 0.5V to 0V),

change (Note 4)

MCP6N16

DS20005318A-page 10  2014 Microchip Technology Inc.

TABLE 1-2: AC ELECTRICAL SPECIFICATIONS (CONTINUED)

Electrical Characteristics: Unless otherwise indicated, TA= +25°C, VDD= 1.8V to 5.5V, VSS= GND, VCM=VDD/2, VDM=0V, V

RL=10kΩ to VL, CL= 60 pF, GDM=G

Parameters Sym.

and EN = VDD; see Figures 1-7 and 1-8.

MIN

Min.

Typ.

Max.

Units G

MIN

Conditions

REF=VDD

/2, VL=VDD/2,

MCP6N16

Noise

Input Noise Voltage Density e

ni

—900 —nV/√Hz 1 f = 500 Hz

—105 — 10

— 45 — 100

Input Noise Voltage E

ni

—19 —µV

1 f = 0.1 Hz to 10 Hz

P-P

—2.2 — 10

— 0.93 — 100

— 5.9 — 1 f = 0.01 Hz to 1 Hz

—0.69 — 10

— 0.30 — 100

Input Current Noise Density i

Output Noise Voltage Density e

Output Noise Voltage E

ni

no

—7 —fA/√Hz all f = 1 kHz

0nV/√Hz

0µV

P-P

Amplifier Distortion (Note 2)

Intermodulation Distortion (AC) IMD — 5 — µV

all VCM tone = 100 mV

PK

at 100 Hz

PK

EMI Protection

EMI Rejection Ratio EMIRR — 103 — dB all VIN=0.1VPK, f = 400 MHz

—106 — V

=0.1VPK, f = 900 MHz

IN

—106 — VIN=0.1VPK, f = 1800 MHz

— 111 — VIN=0.1VPK, f = 2400 MHz

Note 1: The slew rate is limited by the GBWP; the large signal step response is dominated by the small signal bandwidth.

2: These parameters were characterized using the circuit in Figure 1-8. In Figures 2-75 and 2-76, there is an IMD tone at DC, a residual tone at 100 Hz and

other IMD tones and clock tones.

3: High gains behave differently; see Section 4.4.4 “Offset at Power-Up”. 4: t

STR

, t

STL

IRC

and tOR include some uncertainty due to clock edge timing.

IRD

 2014 Microchip Technology Inc. DS20005318A-page 11

TABLE 1-3: DIGITAL ELECTRICAL SPECIFICATIONS

Electrical Characteristics: Unless otherwise indicated, TA=+25°C, VDD= 1.8V to 5.5V, VSS= GND, VCM=VDD/2, VDM=0V, V

R

=10kΩ to VL, CL=60 pF, GDM=G

L

Parameters Sym. Min. Typ. Max. Units G

EN Low Specifications

EN Logic Threshold, Low V

EN Input Current, Low I

GND Current I

Amplifier Output Leakage I

EN High Specifications

EN Logic Threshold, High V

EN Input Current, High I

EN Dynamic Specifications

EN Input Hysteresis V

EN Input Resistance R

EN Low to Amplifier Output High Z Turn-Off Time t

EN High to Amplifier Output On Time t

EN Low to EN High hold time t

EN High to EN Low setup time t

POR Dynamic Specifications

V

↓ to Output Off t

DD

VDD ↑ to Output On t

Note 1: For design guidance only; not tested.

and EN = VDD; see Figures 1-7 and 1-8.

MIN

IL

ENL

SS

O(LEAK)

IH

ENH

HYST

PD

OFF

ON

——0.2VDDVall

— -10 — pA EN = 0V

-8 -2 — µA EN = 0V, VDD=5.5V

—-1—nA EN=0V

0.8V

DD

——Vall

—10—pA EN=V

—

0.16V

—

10

—0.1 2µs EN=0.2VDD to V

— 12 100 VDD= 1.8V, EN = 0.8VDD to V

— 30 100 V

ENLH

ENHL

PHL

PLH

50 — — Minimum time before releasing EN (Note 1)

50 — — Minimum time before exerting EN (Note 1)

—10—µsallV

—

100

13

MIN

—

DD

—

—V

Vall

Ω

DD

=0V, VDD= 1.8V to V

L

=0V, VDD= 0V to V

L

DD

= 5.5V, EN = 0.8VDD to V

REF=VDD

Conditions

=0.1(VDD/2), VL=0V

OUT

– 0.1V step, 90% of V

PRL

+ 0.1V step, 90% of V

PRH

/2, VL=VDD/2,

=0.9(VDD/2), VL=0V

change

OUT

change

OUT

MCP6N16

DS20005318A-page 12  2014 Microchip Technology Inc.

MCP6N16

TABLE 1-4: TEMPERATURE SPECIFICATIONS

Electrical Characteristics: Unless otherwise indicated, all limits are specified for: VDD= 1.8V to 5.5V, VSS= GND.

Parameters Sym. Min. Typ. Max. Units Conditions

Temperature Ranges

Specified Temperature Range T

Operating Temperature Range T

Storage Temperature Range T

Thermal Package Resistances

Thermal Resistance, 8L-DFN (3×3) θ Thermal Resistance, 8L-MSOP θ

Note 1: Operation must not cause T

to exceed the Absolute Maximum Junction Temperature specification (+150°C).

J

A

JA

-40 — +125 °C

-40 — +125 Note 1

-65 — +150

—57 — °C/W

—211 —

1.3 Timing Diagrams

V

DD

V

OUT

1.001 V

REF

0.999 V

REF

0V

1.8V to 5.5V

1.8V

t

STR

V

OUT

t

IRC

V

CM

V

IVH

+0.5V

VDD–1V

V

REF

t

IRC

V

IVL

–0.5V

1V

V

REF

V

OUT

t

IRD

V

REF

GDMV

DM

1V

0V

V

REF

G

MINVDMH

+0.5V

V

OH

t

IRD

VDD–1V

0V

V

REF

G

MINVDML

–0.5V

V

OL

V

OUT

t

OR

V

REF

G

MINVDM

VDD–1V

0V

V

REF

1.5V

V

OH

t

OR

1V

0V

V

REF

-1.5V

V

OL

V

OUT

t

PHL

V

DD

V

PRL

–0.1V

High Z

1.8V

t

PLH

V

PRH

+0.1V

0V

High Z

V

OUT

t

OFF

EN

High Z

t

ON

t

ENLH

t

ENHL

High Z

FIGURE 1-1: Amplifier Start-Up Timing Diagram.

FIGURE 1-2: Common Mode Input Overdrive Recovery Timing Diagram.

MCP6N16

FIGURE 1-3: Differential Mode Input Overdrive Recovery Timing Diagram.

FIGURE 1-4: Output Overdrive Recovery Timing Diagram.

FIGURE 1-5: POR Timing Diagram.

FIGURE 1-6: EN Timing Diagram .

 2014 Microchip Technology Inc. DS20005318A-page 13

MCP6N16

R

G

R

F

R

L

100 nF

V

DD

2.2 µF

V

REF

V

L

31.6 kΩ

V

M

10 µF

C

CNT

U

1

MCP6N16

U

2

MCP6H01

V

CNT

31.6 kΩ

R

CNT

31.6 kΩ

V

OUT

2.2 nF

100Ω

V

CM

2.2 nF

100Ω

G

DM

1RFR

G



+=

V

OUTVCNT

=

V

M

V

REFGDM

1g

E

+V

E

+=

G

DM

1RFR

G



+=

V

M

V

REF

G+

DM

1g

E

+V

DMVE

+=

V

OUT

V

REFGDM

1g

E

+V

DMVE

++=

R

L

63.4 kΩ

100Ω

VCM+VDM/2

1.0 µF

V

OUT

R

F

R

G

V

M

100 nF

V

DD

2.2 µF

V

REF

V

L

VCM–VDM/2

U

1

MCP6N16

1.4 DC Test Circuits

1.4.1 INPUT OFFSET TEST CIRCUIT

Figure 1-7 is a simple circuit that can test the INA’s

input offset errors and input voltage range (V

; see Section 1.5.1 “Input Offset Related

V

IVH

Errors” and Section 1.5.2 “Input Offset Common Mode Nonlinearity”). U2 is part of a control loop that

forces V

to equal V

OUT

; U1 can be set to any bias

CNT

point.

, V

and

E

IVL

1.4.2 DIFFERENTIAL GAIN TEST CIRCUIT

Figure 1-8 is a simple circuit that can test the INA’s

differential gain error, nonlinearity and input voltage range (g

, INLDM, V

E

“Differential Gain Error and Nonlinearity”). R

are 0.01% for accurate gain error measurements.

R

G

The output voltages are (where V offset errors and g

and V

DML

is the gain error):

E

DMH

; see Section 1.5.3

and

F

is the sum of input

E

EQUATION 1-2:

FIGURE 1-7: Simple Test Circuit for Common Mode (Input Offset).

When MCP6N16 is in its normal range of operation, the DC output voltages are (where V offset errors and g

is the gain error):

E

is the sum of input

E

EQUATION 1-1:

Table 1-5 shows the resulting behavior for different

options.

G

MIN

TABLE 1-5: RESULTS

G (V/V)

Nom.

100 68 8.7

DS20005318A-page 14  2014 Microchip Technology Inc.

R

MIN

F

(kΩ) Typ.

1 100 1.00 85 0.50 0.50

10 402 4.02 88 1.2

G

DM

(kV/V)

Typ.

G

DMVOS

(±mV)

Max.

BW

(kHz)

Typ .

at V

OUT

BW (Hz) Typ .

at V

M

FIGURE 1-8: Simple Test Circuit for Differential Mode.

For different values of V ranges to keep V

REF

Table 1-6 shows the recommended R

produce a 10 kΩ load. V

, VDM sweeps over different

REF

, VFG and V

can usually be left open.

L

within their ranges.

OUT

and RG; they

F

TABLE 1-6: SELECTING RF AND R

G

MIN

(V/V)

Nom.

R

F

(kΩ)

Nom.

1 0 Open 1.0000

10 10.0 || 90.9 1.00 10.009

100 10.0 || 1000 100 100.01

R

G

(kΩ)

Nom.

1.4.3 DYNAMIC TESTING OF INPUT BEHAVIOR

The circuit in Figure 1-8 can test the input’s dynamic

, t

behavior (i.e., IMD, t measure the output at V

STR

STL

, instead of at VM.

OUT

IRC

, t

IRD

G

DM

(V/V)

Nom.

and tOR);

1.5 Explanation of DC Error

V

E

VMV

REF

–GDM1g

E

+



=

Where:

PSRR, CMRR, CMRR2 and A

OL

are in

units of V/V

∆T

A

is in units of °C

TC

1

is in units of V/°C

V

DM

=0

V

E

V

OS



V

DD



VSS–

PSRR

---------------------------------



V

CM

CMRR

-----------------



V

REF

CMRR2

--------------------+++=



V

OUT

A

OL

-----------------TATC

1



++

V

1

V

3

VE, V

E_LIN

(V)

VCM (V)

V

IVL

V

IVH

VDD/2

V

2

V

E_LIN

V

E

V

E

Where:

V

E_LINVOS

VCMVDD2



–CMRR



+=

V

OSV2

=

1CMRR



V3V1–V

IVHVIVL

–



=

Where:

INL

CMH

maxVEV

IVHVIVL

–



=



VEVEV

E_LIN

–=

INL

CML

minVEV

IVHVIVL

–



=

INL

CM

INL

CMH

INL

CMH

INL

CML



=

INL

CML

otherwise



=

V

E_LIN2

V

OSVREFVDD

2



–CMRR2



+=

INL

CMH2

maxVE2V

IVHVIVL

–



=

INL

CML2

minVE2V

IVHVIVL

–



=

Where:



V

E2VEVE_LIN2

–=

INL

CM2

INL

CMH2

INL

CMH2

INL

CML2



=

INL

CML2

otherwise



=

Specifications

1.5.1 INPUT OFFSET RELATED ERRORS

The input offset error (VE) is extracted from input offset measurements (see Section 1.4.1 “Input Offset Test

Circuit”), based on Equation 1-1:

EQUATION 1-3:

VE has several terms, which assume a linear response to changes in V

, VSS, VCM, V

DD

are in their specified ranges):

EQUATION 1-4:

and TA (all of which

OUT

MCP6N16

FIGURE 1-9: Input Offset Error vs. Common Mode Input Voltage.

Based on the measured VE data, we obtain the following linear fit:

EQUATION 1-5:

Equation 1-2 shows how VE affects V

1.5.2 INPUT OFFSET COMMON MODE

The input offset error (VE) changes nonlinearly with

. Figure 1-9 shows VE vs. VCM, as well as a linear

V

CM

fit line (V standard conditions (∆V swept from V

Section 1.4.1 “Input Offset Test Circuit” and V

calculated using Equation 1-3.

 2014 Microchip Technology Inc. DS20005318A-page 15

NONLINEARITY

) based on VOS and CMRR. The INA is in

E_LIN

to V

IVL

.

OUT

=0, VDM=0, etc.). VCM is

OUT

. The test circuit is in

IVH

The remaining error (∆VE) is described by the Common Mode Nonlinearity spec:

EQUATION 1-6:

is

E

The same common mode behavior applies to VE when

is swept, instead of VCM, since both input stages

V

REF

are designed the same:

EQUATION 1-7:

MCP6N16

G

DM

1RFR

G



+=

V

M

GDM1g

E

+V

DM

V+

E

=

V

EDVMGDM

 VDM–=

V

1

V

3

VED, V

ED_LIN

(V)

V

DM

(V)

V

DML

V

DMH

0

V

2

V

ED_LIN

V

ED

V

ED

Where:

V

ED_LIN

1g

E

+VEgEV

DM

+=

g

E

V3V1–V

DMHVDML

–



1–=

V

E

V21g

E

+



=

Where:

INL

DMH

max VEDV

DMHVDML

–=

V

ED

VEDV

ED_LIN

–=

INL

DML

min VEDV

DMHVDML

–=

INL

DM

INL

DMH

INL

DMH

INL

DML

=

INL

DML

otherwise=

1.5.3 DIFFERENTIAL GAIN ERROR AND NONLINEARITY

The differential errors are extracted from differential gain measurements (see Section 1.4.2 “Differential

Gain Test Circuit”), based on Equation 1-2. These

errors are the differential gain error (g offset error (V

, which changes nonlinearly with VDM):

E

) and the input

E

EQUATION 1-8:

These errors are adjusted for the expected output, then referred back to the input, giving the differential input error (VED) as a function of VDM:

EQUATION 1-9:

Figure 1-10 shows VED vs. VDM, as well as a linear fit

line (V standard conditions (∆V from V

) based on VED and gE. The INA is in

ED_LIN

to V

DML

DMH

.

=0, etc.). VDM is swept

OUT

EQUATION 1-11:

FIGURE 1-10: Differential Input Error vs. Differential Input Voltage.

Based on the measured VED data, we obtain the following linear fit:

EQUATION 1-10:

Note that the VE value measured here is not as accurate as the one obtained in Section 1.5.1 “Input

Offset Related Errors”.

The remaining error (∆V Differential Nonlinearity spec:

DS20005318A-page 16  2014 Microchip Technology Inc.

ED

) is described by the

MCP6N16

30%

G

MIN

= 1

25%

ence

s

28 Samples

TA= +25°C NPBW = 3 mHz

20%

ccur

r

15%

ge of

O

VDD=1.8V

VDD= 5.5V

10%

rcent

a

5%

P

e

0%

-12-10-8-6-4-2 0 2 4 6 8 1012 Input Offset Voltage (µV)

0%

5%

10%

15%

20%

25%

30%

35%

40%

45%

Percentage of Occurrences

G

MIN

= 10 28 Samples T

A

= +25°C

NPBW = 3 mHz

VDD= 5.5V

VDD= 1.8V

0%

10%

20%

30%

40%

50%

60%

Percentage of Occurrences

G

MIN

= 100 28 Samples T

A

= +25°C

NPBW = 3 mHz

VDD= 5.5V

VDD= 1.8V

40%

G

MIN

= 1

30%

35%

ence

s

28 Samples

TA= -40 to +125°C NPBW = 3 mHz

25%

ccur

r

VDD= 1.8V

15

%

20%

ge of

O

VDD=5.5V

10%

%

rcent

a

5%

P

e

0%

-600 -400 -200 0 200 400 600 Input Offset Voltage Drift; TC

1

(nV/°C)

40%

G

MIN

= 10

30%

35%

ence

s

28 Samples

TA= -40 to +125°C NPBW = 3 mHz

25%

ccur

r

VDD= 5.5V

15

%

20%

ge of

O

VDD=1.8V

10%

%

rcent

a

5%

P

e

0%

-40 -30 -20 -10 0 10 20 30 40 Input Offset Voltage Drift; TC

1

(nV/°C)

40%

G

MIN

= 100

30%

35%

ence

s

28 Samples

TA= -40 to +125°C NPBW = 3 mHz

25%

ccur

r

15

%

20%

ge of

O

VDD= 5.5VVDD= 1.8V

10%

%

rcent

a

5%

P

e

0%

-16 -12 -8 -4 0 4 8 12 16 Input Offset Voltage Drift; TC

1

(nV/°C)

2.0 TYPICAL PERFORMANCE CURVES

Note: The graphs and tables provided following this note are a statistical summary based on a limited number of

samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range.

Note: Unless otherwise indicated, TA=+25°C, VDD= 1.8V to 5.5V, VSS=GND, VCM=VDD/2, VDM=0V, V

REF=VDD

2.1 DC Precision

/2, VL=VDD/2, RL=10kΩ to VL, CL=60pF, GDM=G

and EN = VDD; see Figures 1-7 and 1-8.

MIN

FIGURE 2-1: Input Offset Voltage, with G

=1.

MIN

-2.0 -1.6 -1.2 -0.8 -0.4 0.0 0.4 0.8 1.2 1.6 2.0 Input Offset Voltage (µV)

FIGURE 2-2: Input Offset Voltage, with G

= 10.

MIN

FIGURE 2-4: Input Offset Voltage Drift, with G

MIN

=1.

FIGURE 2-5: Input Offset Voltage Drift, with G

MIN

=10.

FIGURE 2-3: Input Offset Voltage, with G

 2014 Microchip Technology Inc. DS20005318A-page 17

-1.0 -0.6 -0.2 0.2 0.6 1.0 1.4 1.8 2.2 2.6 3.0

= 100.

MIN

Input Offset Voltage (µV)

FIGURE 2-6: Input Offset Voltage Drift, with G

MIN

=100.

MCP6N16

50%

55%

s

G

MIN

= 1

40%

45%

rrenc

e

28 Samples

TA= -40 to +125°C NPBW = 3 mHz

30%

35%

Occu

VDD= 1.8V

20%

25%

age o

f

VDD=5.5V

10%

15%

ercen

t

0%

5%

P

-

1200-800-4000400

800

1200

Quadratic Input Offset Voltage Drift;

TC

2

(pV/°C2)

30%

s

G

MIN

= 10

25%

rrenc

e

28 Samples

TA= -40 to +125°C NPBW = 3 mHz

20%

Occu

=

10%

15%

age o

f

VDD1.8V

VDD= 5.5V

5%

ercen

t

0%

P

-

160-120-80-4004080120

160

Quadratic Input Offset Voltage Drift;

TC

2

(pV/°C2)

4

45%

s

G

MIN

= 100

28 Sam

p

les

35%

40%

rrenc

e

p

TA= -40 to +125°C NPBW = 3 mHz

25%

30%

Occu

VDD= 5.5V V

DD

= 1.8V

15%

20%

age o

f

10%

ercen

t

0%

5%

P

-

120-100-80-60-40-20020

40

Quadratic Input Offset Voltage Drift;

TC

2

(pV/°C2)

25

30

Representative Part

=

15

20

(µV)

G

MIN

1

NPBW = 2 Hz

5

10

oltag

e

-5

0

ffset

V

-15

-10

put

O

VDD= 1.8V

VDD= 5.5V

-25

-

20

I

n

-

30

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Output Voltage (V)

25

30

Representative Part

=

15

20

(µV)

G

MIN

10

NPBW = 2 Hz

5

10

oltag

e

-5

0

ffset

V

VDD= 1.8V

VDD= 5.5V

-15

-10

put

O

-25

-

20

I

n

-

30

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Output Voltage (V)

25

30

Representative Part

=

15

20

(µV)

G

MIN

100

NPBW = 2 Hz

5

10

oltag

e

-5

0

ffset

V

VDD= 1.8V

VDD= 5.5V

-15

-10

put

O

-25

-

20

I

n

-

30

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Output Voltage (V)

Note: Unless otherwise indicated, TA=+25°C, VDD= 1.8V to 5.5V, VSS=GND, VCM=VDD/2, VDM=0V, V

REF=VDD

/2, VL=VDD/2, RL=10kΩ to VL, CL=60pF, GDM=G

and EN = VDD; see Figures 1-7 and 1-8.

MIN

FIGURE 2-7: Quadratic Input Offset Voltage Drift, with G

MIN

=1.

FIGURE 2-8: Quadratic Input Offset Voltage Drift, with G

MIN

=10.

FIGURE 2-10: Input Offset Voltage vs. Output Voltage, with G

MIN

=1.

FIGURE 2-11: Input Offset Voltage vs. Output Voltage, with G

MIN

=10.

FIGURE 2-9: Quadratic Input Offset Voltage Drift, with G

DS20005318A-page 18  2014 Microchip Technology Inc.

MIN

= 100.

FIGURE 2-12: Input Offset Voltage vs. Output Voltage, with G

MIN

= 100.

MCP6N16

-10

0

10

20

30

40

50

ffset Voltage (µV)

Representative Part V

CM

= V

SS

G

MIN

= 1

NPBW = 2 Hz

-50

-40

-30

-20

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5

Input

O

Power Supply Voltage (V)

+125°C +85°C +25°C

-40°C

25

30

Representative Part

V

= V

15

20

(µV)

CM

SS

G

MIN

= 10

NPBW = 2 Hz

5

10

oltag

e

-5

0

ffset

V

-15

-

10

nput

O

+125°C +

°

-25

-

20

I

85

C

+25°C

-40°C

-

30

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 Power Supply Voltage (V)

25

30

Representative Part

V

= V

15

20

(µV)

CM

SS

G

MIN

= 100

NPBW = 2 Hz

5

10

oltag

e

-5

0

ffset

V

-15

-

10

nput

O

+125°C +

°

-25

-

20

I

85

C

+25°C

-40°C

-

30

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 Power Supply Voltage (V)

40

50

Representative Part

V

= V

30

(µV)

CM

DD

G

MIN

= 1

NPBW = 2 Hz

10

20

oltag

e

-10

0

ffset

V

-30

-20

nput

O

+125°C

-40

I

+85°C

+25°C

-40°C

-

50

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 Power Supply Voltage (V)

25

30

Representative Part

V

= V

15

20

(µV)

CM

DD

G

MIN

= 10

NPBW = 2 Hz

5

10

oltag

e

-5

0

ffset

V

-15

-

10

nput

O

+125°C

-25

-

20

I

+85°C +25°C

-40°C

-

30

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 Power Supply Voltage (V)

25

30

Representative Part

V

= V

15

20

(µV)

CM

DD

G

MIN

= 100

NPBW = 2 Hz

5

10

oltag

e

-5

0

ffset

V

-15

-

10

nput

O

+125°C

-25

-

20

I

+85°C

+25°C

-40°C

-

30

0.00.51.01.52.02.53.03.54.04.55.05.56.06.5 Power Supply Voltage (V)

Note: Unless otherwise indicated, TA=+25°C, VDD= 1.8V to 5.5V, VSS=GND, VCM=VDD/2, VDM=0V, V

REF=VDD

/2, VL=VDD/2, RL=10kΩ to VL, CL=60pF, GDM=G

and EN = VDD; see Figures 1-7 and 1-8.

MIN

FIGURE 2-13: Input Offset Voltage vs. Power Supply Voltage, with V G

=1.

MIN

= 0V and

CM

FIGURE 2-14: Input Offset Voltage vs. Power Supply Voltage, with V G

= 10.

MIN

= 0V and

CM

FIGURE 2-16: Input Offset Voltage vs. Power Supply Voltage, with V G

=1.

MIN

CM=VDD

and

FIGURE 2-17: Input Offset Voltage vs. Power Supply Voltage, with V G

= 10.

MIN

CM=VDD

and

FIGURE 2-15: Input Offset Voltage vs. Power Supply Voltage, with V G

= 100.

MIN

 2014 Microchip Technology Inc. DS20005318A-page 19

FIGURE 2-18: Input Offset Voltage vs.

= 0V and

CM

Power Supply Voltage, with V G

= 100.

MIN

CM=VDD

and

MCP6N16

-10

0

10

20

30

40

50

ffset Voltage (µV)

Representative Part V

DD

= 1.8V

G

MIN

= 1

NPBW = 2 Hz

-50

-40

-30

-20

-0.5 0.0 0.5 1.0 1.5 2.0 2.5

Input

O

Input Common Mode Voltage (V)

+125°C +85°C +25°C

-40°C

40

50

Representative Part

V

= 1.8V

30

(µV)

DD

8

G

MIN

= 10

NPBW = 2 Hz

10

20

oltag

e

-10

0

ffset

V

-30

-20

nput

O

+125°C

°

-40

I

+85

C

+25°C

-40°C

-

50

-0.5 0.0 0.5 1.0 1.5 2.0 2.5 Input Common Mode Voltage (V)

40

50

Representative Part

V

= 1.8V

30

(µV)

DD

8

G

MIN

= 100

NPBW = 2 Hz

10

20

oltag

e

-10

0

ffset

V

-30

-20

nput

O

+125°C

°

-40

I

+85

C

+25°C

-40°C

-

50

-0.5 0.0 0.5 1.0 1.5 2.0 2.5 Input Common Mode Voltage (V)

40

50

Representative Part

V

= 5.5V

30

(µV)

DD

G

MIN

= 1

NPBW = 2 Hz

10

20

oltag

e

-10

0

ffset

V

-30

-20

nput

O

+125°C +

°

-40

I

85

C

+25°C

-40°C

-

50

-0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 Input Common Mode Voltage (V)

40

50

Representative Part

V

= 5.5V

30

(µV)

DD

G

MIN

= 10

NPBW = 2 Hz

10

20

oltag

e

-10

0

ffset

V

-30

-20

nput

O

+125°C

°

-40

I

+85

C

+25°C

-40°C

-

50

-0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 Input Common Mode Voltage (V)

40

50

Representative Part

V

= 5.5V

30

(µV)

DD

G

MIN

= 100

NPBW = 2 Hz

10

20

oltag

e

-10

0

ffset

V

-30

-20

nput

O

+125°C +

°

-40

I

85

C

+25°C

-40°C

-

50

-0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 Input Common Mode Voltage (V)

Note: Unless otherwise indicated, TA=+25°C, VDD= 1.8V to 5.5V, VSS=GND, VCM=VDD/2, VDM=0V, V

REF=VDD

/2, VL=VDD/2, RL=10kΩ to VL, CL=60pF, GDM=G

and EN = VDD; see Figures 1-7 and 1-8.

MIN

FIGURE 2-19: Input Offset Voltage vs. Common Mode Voltage, with V G

=1.

MIN

= 1.8V and

DD

FIGURE 2-20: Input Offset Voltage vs. Common Mode Voltage, with V G

= 10.

MIN

= 1.8V and

DD

FIGURE 2-22: Input Offset Voltage vs. Common Mode Voltage, with V G

=1.

MIN

= 5.5V and

DD

FIGURE 2-23: Input Offset Voltage vs. Common Mode Voltage, with V G

= 10.

MIN

= 5.5V and

DD

FIGURE 2-21: Input Offset Voltage vs. Common Mode Voltage, with V G

= 100.

MIN

DS20005318A-page 20  2014 Microchip Technology Inc.

= 1.8V and

DD

FIGURE 2-24: Input Offset Voltage vs. Common Mode Voltage, with V G

= 100.

MIN

= 5.5V and

DD

MCP6N16

-30

-25

-20

-15

-10

-5

0

5

10

15

20

25

30

-0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

Input Offset Voltage (µV)

Representative Part G

MIN

= 1

T

A

= +25°C

NPBW = 2 Hz

VDD= 1.8V VDD= 5.5V

-30

-25

-20

-15

-10

-5

0

5

10

15

20

25

30

-0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

Input Offset Voltage (µV)

Representative Part G

MIN

= 10

T

A

= +25°C

NPBW = 2 Hz

VDD= 1.8V VDD= 5.5V

-30

-25

-20

-15

-10

-5

0

5

10

15

20

25

30

-0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

Input Offset Voltage (µV)

Representative Part G

MIN

= 100

T

A

= +25°C

NPBW = 2 Hz

VDD= 1.8V VDD= 5.5V

0%

5%

10%

15%

20%

25%

30%

35%

40%

45%

50%

55%

60%

Percentage of Occurrences

410 Samples T

A

= +25°C

G

MIN

= 1

NPBW = 2.5 Hz

VDD= 5.5V

VDD= 1.8V

0%

5%

10%

15%

20%

25%

30%

35%

40%

45%

50%

Percentage of Occurrences

310 Samples T

A

= +25°C

G

MIN

= 10

NPBW = 2.5 Hz

VDD= 5.5V

VDD= 1.8V

0%

5%

10%

15%

20%

25%

30%

35%

40%

45%

50%

55%

60%

65%

70%

Percentage of Occurrences

410 Samples T

A

= +25°C

G

MIN

= 100

NPBW = 2.5 Hz

VDD= 5.5V

VDD= 1.8V

Note: Unless otherwise indicated, TA=+25°C, VDD= 1.8V to 5.5V, VSS=GND, VCM=VDD/2, VDM=0V, V

REF=VDD

/2, VL=VDD/2, RL=10kΩ to VL, CL=60pF, GDM=G

and EN = VDD; see Figures 1-7 and 1-8.

MIN

Reference Voltage (V)

FIGURE 2-25: Input Offset Voltage vs. Reference Voltage, with G

Reference Voltage (V)

MIN

=1.

FIGURE 2-26: Input Offset Voltage vs. Reference Voltage, with G

MIN

= 10.

-12 -8 -4 0 4 8 12 1/CMRR (µV/V)

FIGURE 2-28: CMRR, with G

-5-4-3-2-1012345 1/CMRR (µV/V)

FIGURE 2-29: CMRR, with G

MIN

=1.

=10.

FIGURE 2-27: Input Offset Voltage vs. Reference Voltage, with G

 2014 Microchip Technology Inc. DS20005318A-page 21

Reference Voltage (V)

= 100.

MIN

-2.0 -1.6 -1.2 -0.8 -0.4 0.0 0.4 0.8 1.2 1.6 2.0 1/CMRR (µV/V)

FIGURE 2-30: CMRR, with G

MIN

=100.

MCP6N16

0%

5%

10%

15%

20%

25%

30%

35%

40%

45%

50%

55%

Percentage of Occurrences

410 Samples T

A

= +25°C

G

MIN

= 1

NPBW = 2.5 Hz

VDD= 5.5V

VDD= 1.8V

50%

55%

310 Samples

°

40

%

45%

ences

TA= +25

C

G

MIN

= 10

NPBW = 2.5 Hz

35%

%

ccur

r

25%

30%

ge of

O

VDD= 5.5V

15%

20%

rcent

a

5%

10%

P

e

VDD= 1.8V

0%

-1.6 -1.2 -0.8 -0.4 0.0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 1/CMRR2 (µV/V)

90%

410 Samples

°

70%

80%

ences

TA= +25

C

G

MIN

= 100

NPBW = 2.5 Hz

50%

60%

ccur

r

40%

ge of

O

VDD= 5.5V

20%

30%

rcent

a

10%

P

e

V

DD

=1.

8V

0%

-1.2 -0.8 -0.4 0.0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 1/CMRR2 (µV/V)

20%

410 Samples

=

°

16%

18%

ences

TA+25

C

VDD= 1.8V to 5.5V G

MIN

= 1

=

12%

14%

ccur

r

NPBW 2.5 Hz

8%

10%

ge of

O

4

%

6%

rcent

a

2%

%

P

e

0%

-5-4-3-2-1012345 1/PSRR (µV/V)

20%

310 Samples

=

°

16%

18%

ences

TA+25

C

VDD= 1.8V to 5.5V G

MIN

= 10

=

12%

14%

ccur

r

NPBW 2.5 Hz

8%

10%

ge of

O

4

%

6%

rcent

a

2%

%

P

e

0%

-0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1/PSRR (µV/V)

20%

22%

410 Samples

=

°

16%

18%

ences

TA+25

C

VDD= 1.8V to 5.5V G

MIN

= 100

=

14%

ccur

r

NPBW 2.5 Hz

10%

12%

ge of

O

6%

8%

rcent

a

2%

4%

P

e

0%

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1/PSRR (µV/V)

Note: Unless otherwise indicated, TA=+25°C, VDD= 1.8V to 5.5V, VSS=GND, VCM=VDD/2, VDM=0V, V

REF=VDD

/2, VL=VDD/2, RL=10kΩ to VL, CL=60pF, GDM=G

and EN = VDD; see Figures 1-7 and 1-8.

MIN

-10-8-6-4-2 0 2 4 6 810 1/CMRR2 (µV/V)

FIGURE 2-31: CMRR2, with G

FIGURE 2-32: CMRR2, with G

MIN

=1.

= 10.

FIGURE 2-34: PSRR, with G

FIGURE 2-35: PSRR, with G

MIN

=1.

=10.

FIGURE 2-33: CMRR2, with G

DS20005318A-page 22  2014 Microchip Technology Inc.

MIN

= 100.

FIGURE 2-36: PSRR, with G

MIN

= 100.

MCP6N16

0%

5%

10%

15%

20%

25%

30%

35%

40%

45%

50%

55%

Percentage of Occurrences

410 Samples T

A

= +25°C

G

MIN

= 1

NPBW = 2.5 Hz

VDD= 5.5V

VDD= 1.8V

50%

55%

310 Samples

°

40

%

45%

ences

TA= +25

C

G

MIN

= 10

NPBW = 2.5 Hz

35%

%

ccur

r

25%

30%

ge of

O

VDD= 5.5V

15%

20%

rcent

a

5%

10%

P

e

VDD= 1.8V

0%

-1.6 -1.2 -0.8 -0.4 0.0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 1/A

OL

(µV/V)

90%

410 Samples

°

70%

80%

ences

TA= +25

C

G

MIN

= 100

NPBW = 2.5 Hz

50%

60%

ccur

r

40%

ge of

O

VDD= 5.5V

20%

30%

rcent

a

10%

P

e

V

DD

=1.

8V

0%

-1.2 -0.8 -0.4 0.0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 1/A

OL

(µV/V)

145

150

G

MIN

= 100, VDD= 5.5V

V

= 1.8V

135

140

DD

8

125

130

(dB)

115

120

MRR

105

110

C

95

100

G

MIN

= 10, VDD= 5.5V

V

DD

= 1.8V

G

MIN

= 1, VDD= 5.5V

V

DD

= 1.8V

90

-50 -25 0 25 50 75 100 125 Ambient Temperature (°C)

145

150

135

140

125

130

(dB)

115

120

MRR

2

105

110

C

G

MIN

= 100, VDD= 5.5V

V

DD

= 1.8V

95

100

G

MIN

= 10, VDD= 5.5V

V

DD

= 1.8V

G

MIN

= 1, VDD= 5.5V

V

DD

= 1.8V

90

-50 -25 0 25 50 75 100 125 Ambient Temperature (°C)

145

150

G

= 100

135

140

MIN

125

130

(dB)

G

MIN

= 10

115

120

PSRR

G

MIN

= 1

105

110

95

100

VDD= 1.8V to 5.5V

90

-50 -25 0 25 50 75 100 125 Ambient Temperature (°C)

Note: Unless otherwise indicated, TA=+25°C, VDD= 1.8V to 5.5V, VSS=GND, VCM=VDD/2, VDM=0V, V

REF=VDD

/2, VL=VDD/2, RL=10kΩ to VL, CL=60pF, GDM=G

and EN = VDD; see Figures 1-7 and 1-8.

MIN

-10-8-6-4-2 0 2 4 6 810 1/AOL(µV/V)

FIGURE 2-37: DC Open-Loop Gain, with G

=1.

MIN

FIGURE 2-38: DC Open-Loop Gain, with G

= 10.

MIN

FIGURE 2-40: CMRR vs. Ambient Temperature.

FIGURE 2-41: CMRR2 vs. Ambient Temperature.

FIGURE 2-39: DC Open-Loop Gain, with

= 100.

G

MIN

 2014 Microchip Technology Inc. DS20005318A-page 23

FIGURE 2-42: PSRR vs. Ambient Temperature.

MCP6N16

90

95

100

105

110

115

120

125

130

135

140

145

150

-50 -25 0 25 50 75 100 125

DC Open-Loop Gain; A

OL

(dB)

G

MIN

= 10, VDD= 5.5V

V

= 1.8V

G

MIN

= 1, VDD= 5.5V

V

DD

= 1.8V

G

MIN

= 100, VDD= 5.5V

V

DD

= 1.8V

500

600

)

Representative Part

=+

°

300

400

nts (p

A

TA85

C

VDD= 5.5V

100

200

Curr

e

-100

0

Offse

t

I

B

-300

-200

t Bias,

-500

-

400

Inpu

I

OS

-

600

0.00.51.01.52.02.53.03.54.04.55.05.56.0 Common Mode Input Voltage (V)

800

1,000

)

Representative Part

=+

°

600

nts (p

A

TA125

C

VDD= 5.5V

200

400

Curr

e

I

B

-200

0

Offse

t

-

-400

t Bias,

I

OS

-800

600

Inpu

-1,

000

0.00.51.01.52.02.53.03.54.04.55.05.56.0 Common Mode Input Voltage (V)

1000

)

nts (p

A

| IOS|

100

Curr

e

Offse

t

10

t Bias,

I

B

Inpu

1

25 45 65 85 105 125

Ambient Temperature (°C)

1.E-11

1.E-10

1.E-9

1.E-8

1.E-7

1.E-6

1.E-5

1.E-4

1.E-3

-1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0

Input Bias Current Magnitude (A)

-40°C +25°C +85°C

+125°C

1m

10p

100µ

10µ

1µ

100n

10n

1n

100p

0.08

0.10

G

MIN

= 100; =

Representative Parts

0.06

VDD1.8V

VDD= 5.5V

0.02

0.04

or (%)

-0.02

0.00

in Er

r

-

-0.04

G

a

-0.08

0.06

G

MIN

= 1;

V

DD

= 1.8V

V

DD

= 5.5V

G

MIN

= 10;

V

DD

= 1.8V

V

DD

= 5.5V

-0.

10

-50 -25 0 25 50 75 100 125 Ambient Temperature (°C)

Note: Unless otherwise indicated, TA=+25°C, VDD= 1.8V to 5.5V, VSS=GND, VCM=VDD/2, VDM=0V, V

REF=VDD

/2, VL=VDD/2, RL=10kΩ to VL, CL=60pF, GDM=G

DD

Ambient Temperature (°C)

FIGURE 2-43: DC Open-Loop Gain vs. Ambient Temperature.

and EN = VDD; see Figures 1-7 and 1-8.

MIN

FIGURE 2-46: Input Bias and Offset Currents vs. Ambient Temperature, with V

=5.5V.

DD

FIGURE 2-44: Input Bias and Offset Currents vs. Common Mode Input Voltage, with T

= +85°C.

A

FIGURE 2-45: Input Bias and Offset Currents vs. Common Mode Input Voltage, with T

= +125°C.

A

DS20005318A-page 24  2014 Microchip Technology Inc.

Input Voltage (V)

FIGURE 2-47: Input Bias Current Magnitude vs. Input Voltage (below V

SS

).

FIGURE 2-48: Gain Error vs. Ambient Temperature.

MCP6N16

16%

s

405 Samples G

= 1

12%

14%

rrenc

e

MIN

VDD= 1.8V VDD= 5.5V

10%

Occu

6%

8%

age o

f

4%

ercen

t

0%

2%

086

680

P

-0.14-0.1

-0.1

-0.0

-0.04-0.0

0.0

2

0.040.0

0.0

0.1

0.120.1

4

Gain Error (%)

16%

18%

s

306 Samples G

= 10

14%

rrenc

e

MIN

10%

12%

Occu

6%

8%

age o

f

4%

ercen

t

V

DD

= 1.8V

V

DD

= 5.5V

0%

2%

086

680

P

-0.14-0.1

-0.1

-0.0

-0.04-0.0

0.0

0.040.0

0.0

0.1

4

Gain Error (%)

16%

18%

s

386 Samples G

= 100

14%

rrenc

e

MIN

10%

12%

Occu

6%

8%

age o

f

4%

ercen

t

V

DD

= 1.8V

V

DD

= 5.5V

0%

2%

086

680

P

-0.14-0.1

-0.1

-0.0

-0.04-0.0

0.0

2

0.040.0

0.0

0.1

0.120.1

4

Gain Error (%)

Note: Unless otherwise indicated, TA=+25°C, VDD= 1.8V to 5.5V, VSS=GND, VCM=VDD/2, VDM=0V, V

REF=VDD

/2, VL=VDD/2, RL=10kΩ to VL, CL=60pF, GDM=G

and EN = VDD; see Figures 1-7 and 1-8.

MIN

2

202

FIGURE 2-49: Gain Error, with G

2

202

FIGURE 2-50: Gain Error, with G

MIN

2

=1.

2

= 10.

2

FIGURE 2-51: Gain Error, with G

202

MIN

2

= 100.

 2014 Microchip Technology Inc. DS20005318A-page 25

MCP6N16

0.4

m

1stWafer Lot

0.2

0.3

adro

o

V

IVH–VDD

0.1

ge H

e

-0.1

0.0

ge Ra

n

(V

)

-0.2

t Volt

a

V

IVL–VSS

-0.3

Inp

u

-0.

4

-50 -25 0 25 50 75 100 125 Ambient Temperature (°C)

4.0

4.2

t

1stWafer Lot

=-

3.8

l Inpu

DMH

(V

)

G

MINVDMHGMINVDML

RTO

3.4

3.6

erenti

a

G

MIN

V

G

= 1, 10, 100

3.0

3.2

d Dif

f

ange

;

MIN

,,

2.6

2.8

rmaliz

e

ltage

R

2.4

N

V

o

2.2

-50 -25 0 25 50 75 100 125 Ambient Temperature (°C)

)

100

m (m

V

VDD= 1.8V

eadro

o

VDD–V

OH

VDD= 5.5V

10

tage

H

ut Vo

l

VOL–V

SS

Out

p

1

0.1 1 10 Output Current Magnitude (mA)

90

100

)

VDD= 5.5V R

= 1 k

80

m (m

V

VDD–V

OH

L

60

70

eadro

o

40

50

tage

H

VOL–V

SS

20

30

ut Vo

l

10

Out

p

0

-50 -25 0 25 50 75 100 125 Ambient Temperature (°C)

1.1

1.2

0.9

1.0

A)

0.7

0.8

ent (

m

+125°C

+85°C +25°C

°

0.5

0.6

ly Cur

r

-

40

C

0.3

0.4

Supp

0.1

0.2

0.0

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 Power Supply Voltage (V)

1.1

1.2

0.9

1.0

A)

VDD= 1.8V

VDD= 5.5V

0.7

0.8

rent (

m

0.5

0.6

ly Cur

0.3

0.4

Sup

p

0.1

0.2

0.0

-0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 Common Mode Input Voltage (V)

Note: Unless otherwise indicated, TA=+25°C, VDD= 1.8V to 5.5V, VSS=GND, VCM=VDD/2, VDM=0V, V

REF=VDD

/2, VL=VDD/2, RL=10kΩ to VL, CL=60pF, GDM=G

2.2 Other DC Voltages and Currents

and EN = VDD; see Figures 1-7 and 1-8.

MIN

FIGURE 2-52: Input Voltage Range Headroom vs. Ambient Temperature.

o

FIGURE 2-53: Normalized Differential Input Voltage Range vs. Ambient Temperature.

FIGURE 2-55: Output Voltage Headroom vs. Ambient Temperat ure.

FIGURE 2-56: Supply Current vs. Power Supply Voltage.

FIGURE 2-54: Output Voltage Headroom vs. Output Current Magnitude.

DS20005318A-page 26  2014 Microchip Technology Inc.

FIGURE 2-57: Supply Current vs. Common Mode Input Voltage.

MCP6N16

50

A)

30

40

rent (

m

10

20

it Cu

r

+125°C

°

-10

0

t-Circ

u

+85

C

+25°C

-40°C

-

-20

t Sho

r

-40

30

Outp

u

-

50

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 Power Supply Voltage (V)

20%

25%

30%

35%

40%

45%

50%

age of Occurrences

V

PRH

V

PRL

103 Samples 1 Wafer Lot T

A

= +25°C

0%

5%

10%

15%

1.20

1.22

1.24

1.26

1.28

1.30

1.32

1.34

1.36

1.38

1.40

Percen

t

Power-On Reset Trip Voltages (V)

1.55

1.60

(V)

1 Wafer Lot

1.45

1.50

ltages

1.30

1.35

1.40

rip Vo

V

PRH

1.20

1.25

eset

T

V

PRL

1.05

1.10

1.15

r-On

R

0.95

1.00

Pow

e

0.90

-50 -25 0 25 50 75 100 125 Ambient Temperature (°C)

Note: Unless otherwise indicated, TA=+25°C, VDD= 1.8V to 5.5V, VSS=GND, VCM=VDD/2, VDM=0V, V

REF=VDD

/2, VL=VDD/2, RL=10kΩ to VL, CL=60pF, GDM=G

FIGURE 2-58: Output Short-Circuit Current vs. Power Supply Voltage.

and EN = VDD; see Figures 1-7 and 1-8.

MIN

FIGURE 2-59: Power-On Reset Trip Voltages.

FIGURE 2-60: Power-On Reset Trip Voltages vs. Temperature.

 2014 Microchip Technology Inc. DS20005318A-page 27

MCP6N16

120

130

100

110

80

90

(dB)

60

70

MRR

40

5

0

C

20

30

G

MIN

=

100

G

MIN

= 10

G

MIN

= 1

10

1.E+04 1.E+05 1.E+06

Frequency (Hz)

10k 100k 1M

110

120

90

100

70

80

(dB)

50

60

PSRR

30

40

10

20

G

MIN

=

100

G

MIN

= 10

G

MIN

= 1

0

1.E+03 1.E+04 1.E+05 1.E+06

Frequency (Hz)

1k 10k 100k 1M

-210

-180

-150

-120

-90

-60

20

40

60

80

100

120

Gain Phase; A

OL

(°)

p Gain Magnitude;

|A

OL

| (dB)

AOL;

G

MIN

= 100

-330

-300

-270

-

240

-60

-40

-20

0

1.E+3 1.E+4 1.E+5 1.E+6 1.E+7

Open-Loo

p

Open-Lo

o

Frequency (Hz)

G

MIN

= 10

G

MIN

= 1

|AOL|;

G

MIN

= 100

G

MIN

= 10

G

MIN

= 1

1k 10k 100k 1M 10M

500

VDD= 5.5V

450

widt

h

(kHz)

400

n Ban

d

P/G

MI

N

350

ed Ga

i

; GB

W

300

rmali

z

oduc

t

250

N

o

P

r

G

MIN

=

1

G

MIN

= 10

G

MIN

= 100

VDD= 1.8V

200

-50 -25 0 25 50 75 100 125 Ambient Temperature (°C)

85

VDD= 5.5V

80

)

75

rgin (

°

70

se M

a

65

Ph

a

60

G

MIN

=

1

G

MIN

= 10

G

MIN

= 100

VDD= 1.8V

55

-50 -25 0 25 50 75 100 125 Ambient Temperature (°C)

1.E+3

1.E+4

d-Loop Output

pedance ()

10k

1k

G

MIN

= 1, 10, 100

1.E+1

1.E+2

1.E+3 1.E+4 1.E+5 1.E+6

Clos

e

I

m

Frequency (Hz)

100

10

GDM/G

MIN

= 1

G

DM/GMIN

= 10

G

DM/GMIN

= 100

1k 10k 100k 1M

Note: Unless otherwise indicated, TA=+25°C, VDD= 1.8V to 5.5V, VSS=GND, VCM=VDD/2, VDM=0V, V

REF=VDD

/2, VL=VDD/2, RL=10kΩ to VL, CL=60pF, GDM=G

2.3 Frequency Response

and EN = VDD; see Figures 1-7 and 1-8.

MIN

FIGURE 2-61: CMRR vs. Frequency.

FIGURE 2-62: PSRR vs. Frequency.

FIGURE 2-64: Normalized Ga in-Bandw idth

Product vs. Ambient Temperature.

FIGURE 2-65: Phase Margin vs. Ambient Temperature.

FIGURE 2-63: Open-Loop Gain vs. Frequency.

DS20005318A-page 28  2014 Microchip Technology Inc.

FIGURE 2-66: Closed-Loop Output Impedance vs. Frequency.

MCP6N16

9

10

8

)

6

7

ing (d

B

G

MIN

=1

GDM= 1

4

5

Peak

G

MIN

= 100

G

MIN

=10

GDM= 10

= 20

3

Gai

n

GDM= 100

= 200 = 500

=

50

1

2

0

10 100 1,000

Normalized Capacitive Load; C

LGMIN/GDM

(pF)

140

VIN= 100 mVPK, at VIPor V

REF

V=5.5

V

120

130

DD

55

100

110

(dB)

90

MIR

R

G

MIN

= 1

70

80

E

G

MIN

=

10

G

MIN

= 100

60

50

1.E+07 1.E+08 1.E+09 1.E+10

Frequency (Hz)

10M 100M 1G 10G

140

f = 400 MHz

V

= 5.5V

120

130

DD

at V

100

110

(dB)

90

MIR

R

70

80

E

G

MIN

= 1

G

MIN

= 10

at V

IP

60

G

MIN

= 100

50

0.01 0.1 1 Input Voltage (V

PK

)

2

140

f = 900 MHz

V

= 5.5V

120

130

DD

at V

100

110

(dB)

IP

90

MIR

R

70

80

E

G

MIN

= 1

G

MIN

= 10

at V

REF

60

G

MIN

= 100

50

0.01 0.1 1 Input Voltage (V

PK

)

2

140

f = 1800 MHz

V

= 5.5V

120

130

DD

at V

100

110

(dB)

REF

90

MIR

R

70

80

E

G

MIN

= 1

G

MIN

= 10

at V

IP

60

G

MIN

= 100

50

0.01 0.1 1 Input Voltage (V

PK

)

2

140

f = 2400 MHz

V

= 5.5V

120

130

DD

at V

REF

100

110

(dB)

90

MIR

R

70

80

E

G

MIN

= 1

a

tV

IP

60

G

MIN

=

10

G

MIN

= 100

50

0.01 0.1 1 Input Voltage (V

PK

)

2

Note: Unless otherwise indicated, TA=+25°C, VDD= 1.8V to 5.5V, VSS=GND, VCM=VDD/2, VDM=0V, V

REF=VDD

/2, VL=VDD/2, RL=10kΩ to VL, CL=60pF, GDM=G

and EN = VDD; see Figures 1-7 and 1-8.

MIN

FIGURE 2-67: Gain Peaking vs. Normalized Capacitive Load.

FIGURE 2-68: EMIRR vs. Frequency, with V

=100mVPK.

IN

FIGURE 2-70: EMIRR vs. Input Voltage, with f = 900 MHz.

FIGURE 2-71: EMIRR vs. Input Voltage, with f = 1800 MHz.

FIGURE 2-69: EMIRR vs. Input Voltage, with f = 400 MHz.

 2014 Microchip Technology Inc. DS20005318A-page 29

FIGURE 2-72: EMIRR vs. Input Voltage, with f = 2400 MHz.

MCP6N16

1.E+5

1.E+6

1.E+3

1.E+4

Input Noise Voltage

(V

P-P

)

ise Voltage Density

(V/¥Hz)

eni; G

MIN

= 1

G

MIN

= 10

G

MIN

= 100

1µ

20µ

1m

20m

10µ

10m

Eni(0 Hz to f);

G

MIN

= 1

G

MIN

= 10

G

MIN

= 100

1.E+3

1.E+4

1.E+1

1.E+2

1.E-1 1.E+0 1.E+1 1.E+2 1.E+3 1.E+4 1.E+5

Integrate

d

Input No

Frequency (Hz)

0.1 1 10 100 1k 10k 100k

100n

10n

100µ

10µ

1E+3

1µ

ensit

y

f = 100 Hz

tage

D

z)

G

MIN

=

1

G

MIN

= 10

G

MIN

= 100

1E+2

ise Vo

l

(V/¥

H

100n

ut No

In

p

1E+1

-0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 Common Mode Input Voltage (V)

10n

10

100

ctrum, RTI (µV

PK

)

Residual 100 Hz Tone

60 Hz Harmonics

VCMtone = 100 mVPK, f = 100 Hz

IMD Tone at DC

G

MIN

= 1

G

= 10

0.1

1

1.E+0 1.E+1 1.E+2 1.E+3 1.E+4 1.E+5

IMD Sp

e

Frequency (Hz)

MIN

G

MIN

= 100

1 10 100 1k 100k10k

100

VDDtone = 100 mVPK, f = 100 Hz

µV

PK

)

Residual

100 Hz Tone

IMD Tone at DC

G

MIN

= 1

10

, RTI

(

ctru

m

G

= 10

1

D Sp

e

MIN

I

M

G

MIN

= 100

0.1

1.E+0 1.E+1 1.E+2 1.E+3 1.E+4 1.E+5

Frequency (Hz)

1 10 100 1k 100k10k

ise Voltage; e

ni

(t)

(5 µV/div)

G

MIN

= 1

NPBW = 10 Hz

0 20 40 60 80 100 120 140 160 180 200

Input N

o

Time (s)

NPBW = 1 Hz

G

MIN

= 10

e

ni

(t)

ltage

;

/div)

oise

Vo

(0.5 µ

V

put N

NPBW = 10 Hz

I

n

NPBW = 1 Hz

0 20 40 60 80 100 120 140 160 180 200

Time (s)

Note: Unless otherwise indicated, TA=+25°C, VDD= 1.8V to 5.5V, VSS=GND, VCM=VDD/2, VDM=0V, V

REF=VDD

/2, VL=VDD/2, RL=10kΩ to VL, CL=60pF, GDM=G

2.4 Noise

and EN = VDD; see Figures 1-7 and 1-8.

MIN

FIGURE 2-73: Input Noise Voltage Density and Integrated Input Noise Voltage vs. Frequency.

FIGURE 2-74: Input Noise Voltage Density vs. Input Common Mode Voltage.

FIGURE 2-76: Intermodulation Distortion vs. Frequency with V

Disturbance

DD

(see Figure1-8).

FIGURE 2-77: Input Noise Voltage vs. Time, with 1 Hz and 10 Hz Filters and G

MIN

=1.

FIGURE 2-75: Intermodulation Distortion vs. Frequency with V

Figure 1-8).

DS20005318A-page 30  2014 Microchip Technology Inc.

Disturbance (see

CM

FIGURE 2-78: Input Noise Voltage vs. Time, with 1 Hz and 10 Hz Filters and G

MIN

=10.

MCP6N16

G

MIN

= 100

ni

(t)

tage;

e

iv)

ise Vo

l

.2 µV/

d

ut No

(

0

NPBW = 10 Hz

In

p

NPBW = 1 Hz

0 20 40 60 80 100 120 140 160 180 200

Time (s)

Note: Unless otherwise indicated, TA=+25°C, VDD= 1.8V to 5.5V, VSS=GND, VCM=VDD/2, VDM=0V, V

REF=VDD

/2, VL=VDD/2, RL=10kΩ to VL, CL=60pF, GDM=G

FIGURE 2-79: Input Noise Voltage vs. Time, with 1 Hz and 10 Hz Filters and G

= 100.

MIN

and EN = VDD; see Figures 1-7 and 1-8.

MIN

 2014 Microchip Technology Inc. DS20005318A-page 31

MCP6N16

100

125

90

100

NPBW = 1.3 Hz

50

75

70

80

(°C)

(µV)

0

25

50

60

ratur

e

oltag

e

G

MIN

= 1

G

MIN

= 10

G

= 100

T

SEN

-50

-25

30

40

Tem p

e

ffset

V

MIN

-100

-75

10

20

enso

r

put

O

V

OS

-150

-

125

-10

0

S

I

n

-

175-20

0 20 40 60 80 100 120 140 160 180

Time (s)

200

30

GDM= 1000

150

25

(µV)

e (V)

G

MIN

= 1

G

MIN

= 10

50

1001520

oltag

e

Vol t a

g

G

MIN

=

100

010

ffset

V

uppl

y

V

OS

-505

nput

O

ower

S

-100

0

I

P

V

DD

-

150-5

0.0 0.5 1.0 1.5 2.0 2.5 3.0

Time (ms)

2.8

2.9

3.0

3.1

3.2

3

4

5

6

7

ut Voltage (V)

ode Input Voltage (V)

VDD= 5.5V

V

CM

2.4

2.5

2.6

2.7

-1

0

1

2

012345678910

Out

p

Common

M

Time (ms)

V

OUT

;

G

MIN

= 1

G

MIN

= 10

G

MIN

= 100

7

5

VDD= 5.5V

5

634

)

l Mod

e

M

(V)

V

DM

42

tage (

V

renti

a

G

DM

V

D

3

1

ut Vo

l

d Diff

e

ltage;

1

2-10

Out

p

maliz

e

put V

o

V

OUT

;

0

-2

No

r

I

n

G

MIN

=

1

G

MIN

= 10

G

MIN

= 100

-

1-3

012345678910

Time (ms)

2.0

2.2

0.0

0.2

1.6

1.8

-0.4

-0.2

)

tial

M

(V)

GDMV

DM

1.4

-

-0.6

tage (

V

iffere

n

G

DM

V

D

V

OUT

;

G

MIN

= 1

G

MIN

= 10

1.0

1.2

-1.0

0.8

ut Vo

l

lized

D

ltage;

G

MIN

= 100

0.6

0.8

-1.4

-

1.2

Out

p

orm

a

put V

o

0.2

0.4

-1.8

-

1.6

N

I

n

0.0-2.0

012345678910

Time (ms)

5.3

5.5

1.8

2.0

4.9

5.1

1.4

1.6

)

ntial

M

(V)

4.7

1.2

ltage (

V

iffere

G

DM

V

D

4.3

4.5

0.8

1.0

ut Vo

lized

D

ltage

;

V

OUT

;

G

MIN

= 1

G

MIN

= 10

3.9

4.1

0.4

0.6

Out

p

Norm

a

put V

o

G

MIN

=

100

3.5

3.7

0.0

0.2

I

n

GDMV

DM

3.3-0.2

012345678910

Time (ms)

Note: Unless otherwise indicated, TA=+25°C, VDD= 1.8V to 5.5V, VSS=GND, VCM=VDD/2, VDM=0V, V

REF=VDD

/2, VL=VDD/2, RL=10kΩ to VL, CL=60pF, GDM=G

2.5 Time Response

and EN = VDD; see Figures 1-7 and 1-8.

MIN

FIGURE 2-80: Input Offset Voltage vs. Time with Temperature Change.

FIGURE 2-81: Input Offset Voltage vs. Time at Power-Up.

FIGURE 2-83: The MCP6N16 Shows No Phase Reversal vs. Differential Input Overdrive, with V

DD

=5.5V.

FIGURE 2-84: The MCP6N16 Shows No Phase Reversal vs. Output Overdrive to V

SS

.

FIGURE 2-82: The MCP6N16 Shows No Phase Reversal vs. Common Mode Input Overdrive, with V

DS20005318A-page 32  2014 Microchip Technology Inc.

=5.5V.

DD

FIGURE 2-85: The MCP6N16 Shows No Phase Reversal vs. Output Overdrive to V

DD

.

MCP6N16

V/div)

(10 m

G

MIN

= 1

G

MIN

= 10

oltag

e

G

MIN

=

100

tput

V

O

u

0 5 10 15 20 25 30 35 40 45 50

Time (µs)

5.0

5.5

4.0

4.5

)

3.5

tage (

V

G

MIN

= 1

G

MIN

= 10

2.5

3.0

ut Vo

l

G

MIN

= 100

1.5

2.0

Out

p

0.5

1.0

0.0

0 5 10 15 20 25 30 35 40 45 50

Time (µs)

2.5

3.0

3.5

4.0

4.5

5.0

5.5

ut Voltage (V)

G

MIN

= 1

G

MIN

= 10

G

MIN

= 100

VDD= 5.5V

0.0

0.5

1.0

1.5

2.0

0 50 100 150 200 250

Out

p

Time (µs)

1

10

100

1000

110

Differential Input Overdrive

Recovery Time (µs)

G

MIN

= 1

G

MIN

= 10

G

MIN

= 100

VDD= 5.5V

5.0

5.5

4.0

4.5

)

3.5

tage (

V

G

= 1

2.5

3.0

ut Vo

l

MIN

G

MIN

= 10

G

MIN

= 100

1.5

2.0

Out

p

0.5

1.0

0.0

0 50 100 150 200 250 300 350 400 450 500 550 600

Time (µs)

100

1000

110

Output Overdrive Recovery

Time (µs)

G

MIN

= 1

G

MIN

= 10

G

MIN

= 100

VDD= 5.5V Recovery from V

SS

and V

DD

Note: Unless otherwise indicated, TA=+25°C, VDD= 1.8V to 5.5V, VSS=GND, VCM=VDD/2, VDM=0V, V

REF=VDD

/2, VL=VDD/2, RL=10kΩ to VL, CL=60pF, GDM=G

and EN = VDD; see Figures 1-7 and 1-8.

MIN

FIGURE 2-86: Small Signal Step Response.

FIGURE 2-87: Large Signal Step Response.

Normalized Gain; GDM/G

MIN

FIGURE 2-89: Differential Input Overdrive Recovery Time vs. Normalized Gain.

FIGURE 2-90: Output Overdrive Recovery vs. Time.

FIGURE 2-88: Differential Input Overdrive Recovery vs. Time.

 2014 Microchip Technology Inc. DS20005318A-page 33

Normalized Gain; GDM/G

MIN

FIGURE 2-91: Output Overdrive Recovery Time vs. Normalized Gain.

MCP6N16

1.8

2.0

(V)

VL= 0V

1.4

1.6

ltage

1.2

tput V

o

G

MIN

=

1

G

MIN

= 10

G

MIN

= 100

0.8

1.0

ly, O

u

On

0.4

0.6

r Sup

p

V

DD

V

OUT

0.0

0.2

Pow

e

Off Off

-0.

2

0 20 40 60 80 100 120 140 160 180 200

Time (ms)

Note: Unless otherwise indicated, TA=+25°C, VDD= 1.8V to 5.5V, VSS=GND, VCM=VDD/2, VDM=0V, V

REF=VDD

/2, VL=VDD/2, RL=10kΩ to VL, CL=60pF, GDM=G

FIGURE 2-92: Power Supply On and Off and Output Voltage vs. Time.

and EN = VDD; see Figures 1-7 and 1-8.

MIN

DS20005318A-page 34  2014 Microchip Technology Inc.

MCP6N16

1.8

2.0

VDD= 1.8V

V

= 0V

1.4

1.6

es (V

)

INA

L

1.0

1.2

Vol t a

g

EN

V

OUT

turns on

turns off

0.8

utpu

t

G

= 100

0.4

0.6

able,

O

MIN

G

MIN

= 10

G

MIN

= 1

0.0

0.2

E

n

-0.

2

0 20 40 60 80 100 120 140 160 180 200

Time (µs)

5.5

6.0

VDD= 5.5V

V

= 0V

4.5

5.0

es (V

)

INA INA

L

3.5

4.0

Vol t a

g

turns on turns off

2.0

2.5

3.0

utpu

t

EN

V

OUT

1.0

1.5

able,

O

G

MIN

= 1 =

0.0

0.5

E

n

G

MIN

10

G

MIN

= 100

-0.

5

0 20 40 60 80 100 120 140 160 180 200

Time (µs)

0.7

/V)

VDD= 1.8V

V

IH_TRIP/VDD

0.6

Input

ges (

V

0.4

0.5

nable

s Volt

a

V

IL_TRIP/VDD

0.3

ized E

teres

i

V

HYST/VDD

0.2

orma

l

nd Hy

s

0.1

N

Trip

a

VDD= 5.5V

0.0

-50 -25 0 25 50 75 100 125 Ambient Temperature (°C)

0

5

10

15

20

25

30

35

40

45

50

-50 -25 0 25 50 75 100 125

Enable Turn-On Time (µs)

G

MIN

= 1

G

MIN

= 10

G

MIN

= 100

VDD=1.8V

VDD=5.5V

G

MIN

= 1

G

MIN

= 10

G

MIN

= 100

2.0

2.5

EN = 0V

1.5

rent

)

0.5

1.0

ly Cur

wn (µ

A

-40°C °

I

DD

-0.5

0.0

Sup

p

hutd

o

+25

C

+85°C

+125°C

-1.5

-1.0

Powe

r

In

S

I

SS

-2.0

-2.

5

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 Power Supply Voltage (V)

1.E-7

EN = 0V

V

= 5.5V

100n

1.E-8

nt (A

)

DD

+125°C

10n

1.E-9

Curr

e

+85°C

1n

1.E-10

eakag

e

100p

1.E-11

tput

L

10

p

O

u

+25°C

p

1.E-12

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 Output Voltage (V)

1p

Note: Unless otherwise indicated, TA=+25°C, VDD= 1.8V to 5.5V, VSS=GND, VCM=VDD/2, VDM=0V, V

REF=VDD

/2, VL=VDD/2, RL=10kΩ to VL, CL=60pF, GDM=G

2.6 Enable Response

FIGURE 2-93: Enable and Output Voltages vs. Time, with V

DD

=1.8V.

and EN = VDD; see Figures 1-7 and 1-8.

MIN

Ambient Temperature (°C)

FIGURE 2-96: Enable Turn-On Time vs. Ambient Temperature.

FIGURE 2-94: Enable and Output Voltages vs. Time, with V

FIGURE 2-95: Normalized Enable Input Trip and Hysteresis Voltages vs. Ambient Temperature.

 2014 Microchip Technology Inc. DS20005318A-page 35

DD

=5.5V.

FIGURE 2-97: Power Supply Current in Shutdown vs. Power Supply Voltage.

FIGURE 2-98: Output Leakage Current in Shutdown vs. Output Voltage.

MCP6N16

3.0 PIN DESCRIPTIONS

Descriptions of the pins are listed in Table 3-1.

TABLE 3-1: PIN FUNCTION TABLE

MCP6N16

MSOP DFN

11

22 V

33 VIPNon-inverting Input

44 VSSNegative Power Supply

55V

66 VFGFeedback Input

77V

88 V

— 9 EP Exposed Thermal Pad (EP); must be connected to VSS.

Symbol Description

EN Enable Input

IM

REF

OUT

DD

Inverting Input

Reference Input

Output

Positive Power Supply

3.1 Digital Enable Input (EN)

This input (EN) is a CMOS, Schmitt-triggered input. When it is low, it puts the part in a low-power state. When high, the part operates normally. The EN pin must not be left floating.

3.2 Analog Signal Inputs (VIP, VIM)

The non-inverting and inverting inputs (VIP and VIM) are high-impedance CMOS inputs with low bias currents.

3.3 Power Supply Pins (VSS, VDD)

The positive power supply (VDD) is 1.8V to 5.5V higher than the negative power supply (V operation, the other pins are between V

Typically, these parts are used in a single (positive) supply configuration. In this case, V ground and V need bypass capacitors.

is connected to the supply; VDD will

DD

3.4 Analog Reference Input (V

The analog reference input (V input of the second input stage; it shifts V desired range. The external gain resistor (R connected to this pin. It is a high-impedance CMOS input with low bias current.

REF

). For normal

SS

and VDD.

SS

is connected to

SS

)

REF

) is the non-inverting

to its

OUT

) is

G

3.5 Analog Feedback Input (VFG)

The analog feedback input (VFG) is the inverting input of the second input stage. The external feedback components (RF and RG) are connected to this pin. It is a high-impedance CMOS input with low bias current.

3.6 Analog Output (V

The analog output (V output. It represents the differential input voltage (VDM=VIP–VIM), with gain GDM and is shifted by

. The external feedback resistor (RF) is connected

V

REF

to this pin.

) is a low impedance voltage

OUT

)

3.7 Exposed Thermal Pad (EP)

There is an internal connection between the exposed thermal pad (EP) and the V connected to the same potential on the printed circuit board (PCB).

This pad can be connected to a PCB ground (V plane region to provide a larger heat sink. This improves the package thermal resistance (θ

pin; they must be

SS

).

JA

SS

)

DS20005318A-page 36  2014 Microchip Technology Inc.

MCP6N16

V

OUT



V

REF+GDMVDM

Where:

G

DM

=1+RF/R

G

V

OUT

V

IP

V

DD

V

IM

V

REF

V

FG

R

F

R

G

U

1

MCP6N16

V

SS

V

DD

V

IP

V

IM

G

M1

V

IP

V

IM

R

F

V

FG

V

OUT

V

OUT

V

REF

R

M4

G

M2

Σ

I

2

V

REF

I

4

R

G

I

1

MCP6N16

R

EN

V

IP

V

CMVDM

2



+=

V

IM

V

CMVDM

2



–=

V

CM

VIPVIM+2



=

V

DM

VIPVIM–=

A

OL

GM2R

M4

=

G

DM

1RFR

G



+=

VFGV

REF

–VDM=

V

OUT

VDMG

DMVREF

+=

Where:

V

OUT

V

REFGDM

1g

E

+V

DM



VED++=

G

DM

1g

E

+V

E



VE++

Where:

PSRR, CMRR, CMRR2 and A

OL

are in

units of V/V

∆T

A

is in units of °C

TC

1

is in units of V/°C

V

DM

=0

V

E

V

OS



V

DD



VSS–

PSRR

---------------------------------



V

CM

CMRR

-----------------



V

REF

CMRR2

--------------------+++=



V

OUT

A

OL

-----------------TATC

1



++



V

ED

INLDMV

DMHVDML

–





VEINLCMV

IVHVIVL

–



4.0 APPLICATIONS

The MCP6N16 instrumentation amplifier (INA) is manufactured using Microchip’s state of the art CMOS process. Its low cost, low power and high speed make it ideal for battery-powered applications.

4.1 Basic Performance

4.1.1 STANDARD CIRCUIT

Figure 4-1 shows the standard circuit configuration for

these INAs. When the inputs and output are in their specified ranges, the output voltage is approximately:

EQUATION 4-1:

EQUATION 4-2:

The negative feedback loop includes GM2, RM4, RF and

. These blocks set the DC open-loop gain (AOL) and

R

G

the nominal differential gain (G

DM

):

EQUATION 4-3:

AOL is very high, so I4 is very small and I1+I2≈ 0. This makes the differential inputs to G

and GM2 equal in

M1

magnitude and opposite in polarity. Ideally, this gives:

EQUATION 4-4:

FIGURE 4-1: Standard Circuit.

For normal operation, keep:

•V

IP

•VIP–VIM (i.e., VDM) between V

•V

OUT

4.1.2 ANALOG ARCHITECTURE

Figure 4-2 shows the block diagram for these INAs,

without details on chopper-stabilized operation.

FIGURE 4-2: MCP6N16 Block Diagram.

The input signal is applied to GM1. Equation 4-2 shows the relationships between the input voltages (V

) and the common mode and differential voltages

V

IM

(V

CM

 2014 Microchip Technology Inc. DS20005318A-page 37

, VIM, V

and VFG between V

REF

between VOL and V

and VDM).

For an ideal part, changing VCM, VSS or VDD produces no change in V

The different G

OUT

MIN

shifts V

REF

options change GM1, GM2 and the

as needed.

OUT

. V

internal compensation capacitor. This results in the performance trade-offs shown in Tab le 1.

4.1.3 DC ERRORS

Section 1.5 “Explanation of DC Error Specifications” defines some of the DC error

specifications. These errors are internal to the INA, and can be summarized as follows:

OH

DML

and V

IVL

and V

IVH

DMH

EQUATION 4-5:

and

IP

MCP6N16

V

OUT

V

IP

V

DD

V

IM

V

REF

R

F

R

G

R

IP

R

IM

R

I

BP

I

BM

V

FG

I

BF

I

BR

U

1

MCP6N16

Where:

CMRR is in units of V/V



V

IP

IBPR

IP

– IBIOS2



+– R

IP

==



V

IM

IBMR

IM

– IBIOS2



–– R

IM

==



V

CM



V

IP



VIM+2



=

I–

BRIPRIM

+2I–OSRIPRIM–4



=



V

DM



V

IP



VIM–=

I

B

– RIPRIM–IOSRIPRIM+2



–=



V

OUT

G

DM



V

DM



VCMCMRR



+=

Where:

R

IP

= R

IM



RTOL

= tolerance of RIP and R

IM



V

OUTGDM



V

DM



GDM2I

BRTOLIOS

–R

IP





V

FG



V

REF





V

OUTIB2RFGDM

R

–I

OS2RFGDM

R

+2



+



due to high A

OL



V

REF

IBRR

R

– IB2I

OS2

2



+– R

R

==

I

B2

meets the I

B

specification

I

OS2

meets the I

OS

specification

I

B2

≠ I

B

, in general

I

OS2

≠ I

OS

, in general

Where:

G

DMRR

= R

F



R

TOL

= tolerance of RR, RF and R

G

V

OUT

2IB2

RTOLIOS2

+R

F



Where:

f

BW

= -3 dB bandwidth

f

GBWP

= Gain-Bandwidth product

f

BWfGBWPGDM



0.50 MHzG

MINGDM



,



0.35 MHzG

MINGDM



,



G

MIN

=1, 10

G

MIN

=100

Where:

V

O

= Maximum output voltage swing  V

OH–VOL

f

FPBW

SRVO



f

BW



, for these parts

The nonlinearity specifications (INLCM and INLDM) describe errors that are nonlinear functions of V V

, respectively. They give the maximum excursion

DM

CM

and

from linear response over the entire common mode and differential ranges.

The input bias current and offset current specifications

and IOS), together with a circuit’s external input

(I

B

resistances, give an additional DC error. Figure 4-3 shows the resistors that set the DC bias point.

FIGURE 4-3: DC Bias Resistors.

The resistors at the main input (RIP and RIM) and its input bias currents (I

and IBM) give the following

BP

changes in the INA’s bias voltages:

EQUATION 4-6:

EQUATION 4-8:

Where:

The change in V for large R G

DMRR

R

and RF are equal (i.e., RR = RF||RG) and small:

REF

(∆V

) can affect the input range,

REF

or RF. The best design results when

EQUATION 4-9:

4.1.4 AC PERFORMANCE

The bandwidth of these amplifiers depends on G and G

MIN

:

EQUATION 4-10:

DM

The change in VCM (∆VCM) can affect the input range, for large R and RIM are equal and small:

EQUATION 4-7:

The resistors at the feedback input (RR, RF and RG) and its input bias currents (I following changes in the INA’s bias voltages:

DS20005318A-page 38  2014 Microchip Technology Inc.

or RIM. The best design results when R

IP

and IBF) give the

BR

The bandwidth at the maximum output swing is called the Full Power Bandwidth (f Slew Rate (SR) for many amplifiers, but is close to f

). It is limited by the

FPBW

BW

for these parts:

IP

EQUATION 4-11:

MCP6N16

V

IP

V

IM

G

M1

V

OUT

R

M4

G

A1

Chopper

Input

Switches

Chopper

Output

Switches

Oscillator

Low-Pass

Filter

Digital Control

V

FG

V

REF

G

A2

Chopper

Input

Switches

POR

G

M2

V

IP

V

IM

G

A1

V

FG

V

REF

G

A2

Low-Pass

Filter

4.1.5 NOISE PERFORMANCE

As shown in Figure 2-73, the noise density is white at low frequencies; the 1/f noise is negligible for almost all applications. As a result, the time domain data in

Figures 2-77, 2-78 and 2-79 is well behaved.

4.2 Overview of Zero-Drift Operation

Figure 4-4 shows a simplified diagram of the MCP6N16

zero-drift INAs. This diagram will be used to explain how low voltage errors are reduced in this architecture (much better V PSRR, A

OL

, TC1 (∆VOS/∆TA), CMRR, CMRR2,

OS

and 1/f noise).

FIGURE 4-4: Simplified Zero-Drift INA Functional Diagram.

4.2.1 BUILDING BLOCKS

The Main Amplifiers (GM1 and GM2) are designed for high gain and bandwidth, with a differential topology. The main input pairs (+ and - pins at the top left) are for the higher frequency portion of the input signal. The auxiliary input pair (+ and - pins at the bottom left of

) is for the low frequency portion of the input signal

G

M1

and corrects the INA’s input offset voltage. Both inputs are added together internally.

The Auxiliary Amplifiers (G Input Switches and the Chopper Output Switches provide a high DC gain to the input signal. DC errors are modulated to higher frequencies and white noise to low frequencies.

The Low-Pass Filter reduces high-frequency content, including harmonics of the Chopping Clock.

The Output Buffer (R and drives external loads at the V

The Oscillator runs at f divided by 8, to produce the Chopping Clock rate of

=25kHz.

f

CHOP

M4

The internal POR part starts the part in a known good state, protecting against power supply brown-outs. The Digital Control block outputs clocks and POR events.

 2014 Microchip Technology Inc. DS20005318A-page 39

and GA2), the Chopper

A1

) converts current to voltage

= 200 kHz. Its output is

CLK

pin.

OUT

4.2.2 CHOPPING ACTION

Figure 4-5 shows the amplifier connections for the first

phase of the Chopping Clock and Figure 4-6 shows them for the second phase. The slow voltage errors alternate in polarity, making the average error small.

FIGURE 4-5: First Chopping Clock Phase; Simplified Diagram.

MCP6N16

V

IP

V

IM

G

A1

V

FG

V

REF

G

A2

Low-Pass

Filter

Bond

Pad

Bond

Pad

Bond

Pad

V

DD

V

IP

V

SS

Input

Stage

Bond

Pad

V

IM

of

INA Input

FIGURE 4-6: Second Chopping Clock Phase; Simplified Diagram.

4.2.3 INTERMODULATION DISTORTION (IMD)

These INAs will show intermodulation distortion (IMD) products when an AC signal is present.

The signal and clock can be decomposed into sine wave tones (Fourier series components). These tones interact with the zero-drift circuitry’s nonlinear response to produce IMD tones at sum and difference frequencies. Each of the square wave clock’s harmonics has a series of IMD tones centered on it. See Figures 2-75 and 2-76.

4.3 Other Functional Blocks

4.3.1 RAIL-TO-RAIL INPUTS

Each input stage uses one PMOS differential pair at the input. The output of each differential pair is processed using current mode circuitry. The inputs show no crossover distortion vs. common mode voltage.

With this topology, the inputs (V normally down to V

– 0.15V and up to VDD+0.15V

SS

at room temperature (see Figure 2-52). The input offset voltage (V V

+ 0.15V (at +25°C) to ensure proper operation.

DD

) is measured at VCM=VSS–0.15V and

OS

4.3.1.1 Phase Reversal

The input devices are designed to not exhibit phase inversion when the input pins exceed the supply voltages. Figure 2-82 shows an input voltage exceeding both supplies with no phase inversion.

The input devices also do not exhibit phase inversion when the differential input voltage exceeds its limits; see Figure 2-83.

4.3.1.2 Input Voltage Limits

In order to prevent damage and/or improper operation of these amplifiers, the circuit must limit the voltages at the input pins (see Section 1.1 “Absolute Maximum

Ratings †”). This requirement is independent of the

current limits discussed later on.

The ESD protection on the inputs can be depicted as shown in Figure 4-7. This structure was chosen to protect the input transistors against many (but not all) overvoltage conditions, and to minimize input bias current (I

).

B

and VIM) operate

IP

FIGURE 4-7: Simplified Analog Input ESD Structures.

The input ESD diodes clamp the inputs when they try to go more than one diode drop below V clamp any voltages that go too far above V breakdown voltage is high enough to allow normal operation, but not low enough to protect against slow over-voltage (beyond V

) events. Very fast ESD

DD

events (that meet the specification) are limited so that damage does not occur.

DS20005318A-page 40  2014 Microchip Technology Inc.

. They also

SS

DD

; their

MCP6N16

V

DD

V

1

D

1

V

2

D

2

U

1

MCP6N16

min(R1,R2)>

VSS–min(V1,V2)

2mA

V

DD

V

1

R

1

D

1

V

2

R

2

D

2

U

1

MCP6N16

min(R1,R2)>

max(V1,V2)–V

DD

2mA

V

IP

V

IM

V

DM

=0

V

IVH

V

IVL

0

V

IVH

V

IVL

0

V

D

M

=

V

D

M

H

V

CM

=V

DD

/2

V

DM

=V

DML

V

DD

V

DD

In some applications, it may be necessary to prevent excessive voltages from reaching the INA inputs.

Figure 4-8 shows one approach to protecting these

inputs. D

and D2 may be small signal silicon diodes,

1

Schottky diodes for lower clamping voltages or diode-connected FETs for low leakage.

FIGURE 4-8: Protecting the Analog Inputs Against High Voltages.

4.3.1.3 Input Current Limits

In order to prevent damage and/or improper operation of these amplifiers, the circuit must limit the currents into the input pins (see Section 1.1 “Absolute

Maximum Ratings †”). This requirement is

independent of the voltage limits previously discussed.

Figure 4-9 shows one approach to protecting these

inputs. The resistors R current in or out of the input pins (and into D The diode currents will dump onto V

and R2 limit the possible

1

DD

.

and D2).

1

4.3.1.4 Input Voltage Ranges

Figure 4-10 shows possible input voltage values

= 0V). Lines with a slope of +1 have constant V

(V

SS

(e.g., the VDM= 0 line). Lines with a slope of -1 have constant V

For normal operation, V

(e.g., the VCM=VDD/2 line).

CM

and VIM must be kept within

IP

the region surrounded by the thick blue lines. The horizontal and vertical blue lines show the limits on the individual inputs. The blue lines with a slope of +1 show the limits on V to the V

DM

; the larger G

DM

= 0 line.

The input voltage range specifications (V change with the supply voltages (V

is, the closer they are

MIN

IVL

and VDD,

SS

respectively). The differential input range specifications (V

DML

and V

) change with minimum gain (G

DMH

Temperature also affects these specifications.

and V

DM

IVH

MIN

)

).

FIGURE 4-10: Input Voltage Ranges.

To take full advantage of V (see Figures 1-7 and 1-8) so that the output (V centered between the supplies (V the gain (G

) to keep V

DM

and V

DML

SS

within its range.

OUT

, set V

DMH

OUT

REF

) is

and VDD). Also set

FIGURE 4-9: Protecting the Analog Inputs Against High Currents.

It is also possible to connect the diodes to the left of the resistor R the diodes D mechanism. The resistors then serve as in-rush current limiters; the DC current into the input pins (VIP and VIM) should be very small.

A significant amount of current can flow out of the inputs (through the ESD diodes) when the common mode voltage (V

Figure 2-47.

 2014 Microchip Technology Inc. DS20005318A-page 41

and R2. In this case, the currents through

1

and D2 need to be limited by some other

1

) is below ground (VSS); see

CM

MCP6N16

VOSTA V

OS

TC

1



TTC

2



T

2

++=

Where:

T

A

= -40°C to +125°C

∆T=TA–25°C

V

OS(TA

) = Input offset voltage at T

A

VOS= Input offset voltage at +25°C

TC1= Linear temperature coefficient

TC

2

= Quadratic temperature coefficient

4.3.2 ENABLE

This input (EN) is a CMOS, Schmitt-triggered input. When it is low, it puts the part in a low-power state and the output is put into a high-impedance state. When high, the part operates normally.

If the EN pin is left floating, the amplifier will not operate properly.

4.3.3 RAIL-TO-RAIL OUTPUT

The Minimum Output Voltage (VOL) and Maximum Output Voltage (V

) specifications describe the

OH

widest output swing that can be achieved under the specified load conditions.

The output can also be limited when V

or V

V

IVL

or when VDM exceeds V

IVH

or VIM exceeds

IP

or V

DML

DMH

.

4.4 Applications Tips

4.4.1 INPUT OFFSET VOLTAGE OVER TEMPERATURE

Table 1 gives both the linear and quadratic temperature

coefficients (TC input offset voltage can be estimated as follows:

EQUATION 4-12:

and TC2) of input offset voltage. The

1

4.4.3 DC GAIN PLOTS

Figures 2-28 to 2-39 are histograms of the reciprocals

(in units of µV/V) of CMRR, PSRR and A

OL

respectively. They represent the change in input offset voltage (VOS) with a change in common mode input voltage (V voltage (V

The 1/A

), power supply voltage (VDD) and output

CM

).

OUT

histogram is centered near 0 µV/V because

OL

the measurements are dominated by the INA’s input noise. The negative values shown represent noise and

tester limitations, not unstable behavior. Production

tests make multiple VOS measurements, which validates an INA's stability; an unstable part would show greater V

variability, or the output would stick

OS

at one of the supply rails.

4.4.4 OFFSET AT POWER-UP

When these parts power up, the input offset (VOS) starts at its uncorrected value (usually less than ±10 mV). Circuits with high DC gain can cause the output to reach one of the two rails. In this case, the time to a valid output is delayed by an output overdrive time (like t

It can be simple to avoid this extra start-up time. Reducing the gain is one method. Adding a capacitor across the feedback resistor (R

), in addition to a start-up time (like t

ODR

) is another method.

F

STR

,

).

These specifications show these INA’s intrinsic performance. The plots of input offset voltage versus temperature on the second page (Figures 1 to 3) show the typical behavior for a few parts from the first wafer lot.

In most designs, other effects will dominate the circuit temperature performance; see Section 4.4.13 “PCB

Design for DC Precision” for more details.

4.4.2 NOISE EFFECT ON OFFSET VOLTAG E

The input noise (eni) makes measured offset values

) vary in a random manner. Lower noise requires

(V

OS

a lower noise power bandwidth (NPBW; see AN1228, mentioned in 5.3 “Application Notes”), which increases measurement time. In the offset-related specifications (A plots, the various values of NPBW were chosen to trade off time versus accuracy of results.

DS20005318A-page 42  2014 Microchip Technology Inc.

, CMRR, CMRR2 and PSRR) and

OL

4.4.5 SOURCE RESISTANCES

The input bias currents have two significant components: switching glitches that dominate at room temperature and below, and input ESD diode leakage currents that dominate at +85°C and above.

Make the resistances seen by the inputs small and equal. This minimizes the output offset caused by the input bias currents.

The inputs should see a resistance on the order of 10Ω to 1 kΩ at high frequencies (i.e., above 1 MHz). This helps minimize the impact of switching glitches, which are very fast, on overall performance. In some cases, it may be necessary to add resistors in series with the inputs to achieve this improvement in performance.

Small input resistances at the inputs may be needed for high gains. Without them, parasitic capacitances might cause positive feedback and instability.

4.4.6 SOURCE CAPACITANCE

The capacitances seen by the inputs should be small. Large input capacitances and source resistances, together with high gain, can lead to positive feedback and instability.

4.4.7 MINIMUM STABLE GAIN

R

ISO

V

OUT

C

L

V

1

V

DD

V

2

V

REF

V

FG

R

F

R

G

U

1

MCP6N16

2k

1,000

()

1k

ed R

IS

O

men

d

Reco

m

100

10 100 1,000 10,000

Normalized Load Capacitance; C

LGMIN/GDM

(F)

10p 100p 1n 10n

10p

V

OUT

V

1

V

DD

V

2

V

REF

V

FG

R

F

R

G

C

DM

C

CM

C

CM

U

1

MCP6N16

There are three options for different Minimum Stable Gains (1, 10 and 100 V/V; see Ta bl e 1 ). The differential gain (G

) needs to be greater than or equal to G

DM

MIN

in order to maintain stability.

Picking a part with higher G lower input noise voltage density (e offset voltage (V

) and increased gain-bandwidth

OS

has the advantages of

MIN

), lower input

ni

product (GBWP). The differential input voltage range (V

DML

and V

) is lower for higher G

DMH

, but supports

MIN

a reasonable output voltage range.

4.4.8 CAPACITIVE LOADS

Driving large capacitive loads can cause stability problems for voltage amplifiers. As the load capacitance increases, the feedback loop’s phase margin decreases and the closed-loop bandwidth reduces. This produces gain peaking in the frequency response, with overshoot and ringing in the step response. Lower gains (G to capacitive loads.

When driving large capacitive loads with these instrumentation amps (e.g., > 80 pF), a small series resistor at the output (R feedback loop’s phase margin (stability) by making the output load resistive at higher frequencies. The bandwidth will be generally lower than the bandwidth with no capacitive load.

) exhibit greater sensitivity

DM

in Figure 4-11) improves the

ISO

MCP6N16

FIGURE 4-12: Recommended R for Capacitive Loads.

After selecting R resulting frequency response peaking and step response overshoot on the bench. Modify R until the response is reasonable.

for the circuit, double check the

ISO

4.4.9 GAIN RESISTORS

Figure 4-13 shows a simple gain circuit with the INA’s

input capacitances at the feedback inputs (V

). These capacitances interact with RG and RF to

V

FG

modify the gain at high frequencies. The equivalent capacitance acting in parallel to RG is CG=CDM+C plus any board capacitance in parallel to RG. CG will cause an increase in G reduces the phase margin of the feedback loop (i.e., reduce the feedback loop’s stability).

at high frequencies, which

DM

ISO

Values

’s value

and

REF

CM

FIGURE 4-11: Output Resistor, R Stabilizes Large Capacitive Loads.

Figure 4-12 gives recommended R

different capacitive loads and gains. The x-axis is the normalized load capacitance (C

is the circuit’s differential gain (1 + RF/RG) and

G

DM

G

is the minimum stable gain.

MIN

 2014 Microchip Technology Inc. DS20005318A-page 43

ISO

values for

ISO

LGMIN/GDM

), where

FIGURE 4-13: Simple Gain Circuit with Parasitic Capacitances.

MCP6N16

Where:



0.25

G

DM



G

MIN

f

GBWP

= Gain-Bandwidth Product

C

G=CDM+CCM

+ (PCB stray capacitance)

RF0=

For G

DM

=1:

R

F



G

DM

2

2f

GBWPCG

------------------------------



For G

DM

>1:

EMIRR dB 20

V

RF



V

OS

-------------





log



=

Where:

V

RF

= Peak Input Voltage of EMI (VPK)

∆VOS= Input Offset Voltage Shift (V)

In this data sheet, RF+RG=10kΩ for most gains (0Ω for G

= 1); see Table 1-6. This choice gives good

DM

phase margin. In general, R meet the following limits to maintain stability:

EQUATION 4-13:

4.4.10 EMI REJECTION RATIO (EMIRR)

Electromagnetic interference (EMI) can be coupled to an INA through electromagnetic induction or radiation, or by conduction. INAs are most sensitive to EMI at their input pins.

EMIRR describes an INA’s EMI robustness. Internal passive filters in these parts improve the EMIRR, when good PCB layout techniques are used. EMIRR is defined to be:

EQUATION 4-14:

4.4.11 REDUCING UNDESIRED NOISE AND SIGNALS

Reduce undesired noise and signals with:

• Low bandwidth signal filters:

- Minimizes random analog noise

- Reduces interfering signals

• Good PCB layout techniques:

- Minimizes crosstalk

- Minimizes parasitic capacitances and inductances that interact with fast switching edges

• Good power supply design:

- Isolation from other parts

- Filtering of interference on supply line(s)

DS20005318A-page 44  2014 Microchip Technology Inc.

F

(Figure 4-13) needs to

4.4.12 SUPPLY BYPASS

With these INAs, the Power Supply pin (VDD for single supply) should have a local bypass capacitor (i.e.,

0.01 µF to 0.1 µF) within 2 mm for good high-frequency performance. Surface mount, multilayer ceramic capacitors, or their equivalent, should be used.

These INAs require a bulk capacitor (i.e., 1.0 µF or larger) within 100 mm to provide large, slow currents. This bulk capacitor can be shared with other nearby analog parts as long as crosstalk through the supplies does not prove to be a problem.

4.4.13 PCB DESIGN FOR DC PRECISION

In order to achieve DC precision on the order of ±1 µV, many physical errors need to be minimized. The design of the printed circuit board (PCB), the wiring, and the thermal environment have a strong impact on the precision achieved. A poor PCB design can easily be more than 100 times worse than the MCP6N16 op amps’ minimum and maximum specifications.

4.4.13.1 PCB Layout

Any time two dissimilar metals are joined together, a temperature dependent voltage appears across the junction (the Seebeck or thermojunction effect). This effect is used in thermocouples to measure temperature. The following are examples of thermojunctions on a PCB:

• Components (resistors, INAs, …) soldered to a copper pad

• Wires mechanically attached to the PCB

• Jumpers

• Solder joints

•PCB vias

Typical thermojunctions have temperature to voltage conversion coefficients of 1 to 100 µV/°C (sometimes higher).

Microchip’s AN1258 (“Op Amp Precision Design: PCB Layout Techniques” – DS01258) contains in-depth

information on PCB layout techniques that minimize thermojunction effects. It also discusses other effects, such as crosstalk, impedances, mechanical stresses and humidity.

4.4.13.2 Crosstalk

DC crosstalk causes offsets that appear as a larger input offset voltage. Common causes include:

• Common mode noise (remote sensors)

• Ground loops (current return paths)

• Power supply coupling

Interference from the mains (usually 50 Hz or 60 Hz), and other AC sources, can also affect the DC performance. Nonlinear distortion can convert these signals to multiple tones, including a DC shift in voltage.

MCP6N16

V

OUT

V

IP

V

DD

V

IM

V

REF

V

FG

R

F

R

G

U

1

MCP6N16

V

OUT

V

DD

V

REF

V

FG

R

F

R

G

R

2

R

1

V

2

C

1

C

2

R

2

R

1

V

1

C

1

C

2

U

1

MCP6N16

V

OUT

20 kΩ

100Ω

2.49 kΩ

68.1Ω

RTD

4.99 kΩ

V

DD

MCP6N16-100

10 µF

100Ω

EN

100Ω

4.99 kΩ 4.99 kΩ

When the signal is sampled by an ADC, these AC signals can also be aliased to DC, causing an apparent shift in offset.

To reduce interference:

- Keep traces and wires as short as possible

- Use shielding

- Use ground plane (at least a star ground)

- Place the input signal source near to the DUT

- Use good PCB layout techniques

- Use a separate power supply filter (bypass capacitors) for these zero-drift INAs

4.4.13.3 Miscellaneous Effects

Keep the resistances seen by the input pins as small and as near to equal as possible, to minimize bias current-related offsets.

Make the (trace) capacitances seen by the input pins small and equal. This is helpful in minimizing switching glitch-induced offset voltages.

Bending a coax cable with a radius that is too small causes a small voltage drop to appear on the center conductor (the triboelectric effect). Make sure the bending radius is large enough to keep the conductors and insulation in full contact.

Mechanical stresses can make some capacitor types (such as some ceramics) output small voltages. Use more appropriate capacitor types in the signal path and minimize mechanical stresses and vibration.

Humidity can cause electrochemical potential voltages to appear in a circuit. Proper PCB cleaning helps, as does the use of encapsulants.

4.5 Typical Applications

4.5.1 HIGH INPUT IMPEDANCE DIFFERENCE AMPLIFIER

Figure 4-14 shows the MCP6N16 used as a difference

amplifier. The inputs are high-impedance and give good CMRR performance.

4.5.2 DIFFERENCE AMPLIFIER FOR VERY LARGE COMMON MODE SIGNALS

Figure 4-15 uses the MCP6N16 INA as a difference

amplifier for signals with a very large common mode component. The input resistor dividers (R

and R2)

1

ensure that the INA’s inputs are within their normal range of operation. The capacitors (C1 and C2) set the same voltage division ratio for high-frequency signals (e.g., a voltage step). C2 includes the INA’s CCM. R and R2’s tolerances affect CMRR.

FIGURE 4-15: Difference Amplifier with Very Large Common Mode Component.

4.5.3 RTD TEMPERATURE SENSOR

Figure 4-16 shows an RTD temperature sensor circuit,

which measures over the -55°C to +155°C range. The sensor chosen changes from 78Ω to 159Ω over this range. The 2.49 kΩ and 4.99 kΩ resistors set the current through the RTD and 68.1Ω resistor. The INA provides a high-differential gain. The 10 µF capacitor filters common mode interference on the bridge.

1

FIGURE 4-14: Difference Amplifier.

 2014 Microchip Technology Inc. DS20005318A-page 45

FIGURE 4-16: RTD Temperature Sensor.

MCP6N16

V

OUT

V

REF

V

FG

R

F

100 kΩ

V

DD

R

W1

R

W2

R

W2

R

W1

U

1

MCP6N16-100

10 µF

R

N

100Ω

R

G

100Ω

R

SH

V

L

I

L

VPS= +1.8V to 5.5V

V

OUT

V

REF

V

FG

R

F

R

G

10.0 kΩ

100Ω

U

1

MCP6N16-100

V

PS

I

PS

I

DD

IPS=IL+I

DD

IPS=(VPS–VL)/(10 mΩ)

=(V

OUT–VREF

)/((10 mΩ)(101V/V))

10 mΩ

4.5.4 WHEATSTONE BRIDGE

Figure 4-17 shows the MCP6N16 INA used to

condition the signal from a Wheatstone bridge (e.g., strain gage). The overall INA gain is set at 1001 V/V. The best G (MCP6N16-100).

FIGURE 4-17: Wheatstone Bridge Amplifier.

option to pick, for this gain, is 100 V/V

MIN

4.5.5 HIGH SIDE CURRENT DETECTOR

Figure 4-18 shows the MCP6N16 INA used to detect

and amplify the high side current in a power supply design. U reduce R temperature effects. U the measurement. The INA’s gain is set at 101 V/V, so V

changes 1.01V for every 1A change in IDD.

OUT

FIGURE 4-18: High Side Current Detector.

DS20005318A-page 46  2014 Microchip Technology Inc.

’s low offset voltage makes it possible to

1

, which saves power and minimizes

SH

’s supply current is included in

1

5.0 DESIGN AIDS

Microchip provides the basic design aids needed for the MCP6N16 instrumentation amplifiers.

5.1 Microchip Advanced Part Selector (MAPS)

MAPS is a software tool that helps efficiently identify Microchip devices that fit a particular design requirement. Available at no cost from the Microchip website at www.microchip.com/maps, the MAPS is an overall selection tool for Microchip’s product portfolio that includes Analog, Memory, MCUs and DSCs. Using this tool, a customer can define a filter to sort features for a parametric search of devices and export side-by-side technical comparison reports. Helpful links are also provided for Data sheets, Purchase and Sampling of Microchip parts.

5.2 Analog Demonstration Board

Microchip offers a broad spectrum of Analog Demonstration and Evaluation Boards that are designed to help customers achieve faster time to market. For a complete listing of these boards and their corresponding user’s guides and technical information, visit the Microchip web site at www.microchip.com/analog tools.

MCP6N16

5.3 Application Notes

The following Microchip Application Notes are available on the Microchip web site at

www.microchip.com/appnotes and are recommended

as supplemental reference resources.

• AN884: “Driving Capacitive Loads With Op

Amps”, DS00884

• AN990: “Analog Sensor Conditioning Circuits –

An Overview”, DS00990

• AN1177: “Op Amp Precision Design: DC

Errors”, DS01177

• AN1228: “Op Amp Precision Design: Random

Noise”, DS01228

• AN1258: “Op Amp Precision Design: PC B Layou t

Techniques”, DS01258

Some of these application notes, and others, are listed in the design guide:

• “Signal Chain Design Guide”, DS21825

 2014 Microchip Technology Inc. DS20005318A-page 47

MCP6N16

Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code Pb-free JEDEC

®

designator for Matte Tin (Sn)

* This package is Pb-free. The Pb-free JEDEC designator ( )

can be found on the outer packaging for this package.

Note: In the event the full Microchip part number cannot be marked on one line, it will

be carried over to the next line, thus limiting the number of available characters for customer-specific information.

3

e

Product Number Code

MCP6N16-001E/MF DADV

MCP6N16T-001E/MF DADV

MCP6N16-010E/MF DADW

MCP6N16T-010E/MF DADW

MCP6N16-100E/MF DADX

MCP6N16T-100E/MF DADX

DADV

1423

256

8-Lead MSOP (3x3 mm) Example

8-Lead DFN (3x3 mm) Example

N16010 423256

6.0 PACKAGING INFORMATION

6.1 Package Marking Information

3

e

DS20005318A-page 48  2014 Microchip Technology Inc.

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

MCP6N16

 2014 Microchip Technology Inc. DS20005318A-page 49

MCP6N16

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

DS20005318A-page 50  2014 Microchip Technology Inc.

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

MCP6N16

 2014 Microchip Technology Inc. DS20005318A-page 51

MCP6N16

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

DS20005318A-page 52  2014 Microchip Technology Inc.

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

MCP6N16

 2014 Microchip Technology Inc. DS20005318A-page 53

MCP6N16

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

DS20005318A-page 54  2014 Microchip Technology Inc.

APPENDIX A: REVISION HISTORY

Revision A (July 2014)

• Original Release of this Document.

MCP6N16

 2014 Microchip Technology Inc. DS20005318A-page 55

MCP6N16

Device: MCP6N16 Single Instrumentation Amplifier

MCP6N16T Single Instrumentation Amplifier

(Tape and Reel)

Gain Option: 001 = Minimum gain of 1 V/V

010 = Minimum gain of 10 V/V 100 = Minimum gain of 100 V/V

Temperature Range: E = -40°C to +125°C

Package: MF = Plastic Dual Flat, no lead Package - 3×3x0.9 mm

Body, 8-lead (DFN)

MS = Plastic Micro Small Outline Package, 8-lead (MSOP)

Examples:

a) MCP6N16T-001E/MF: Tape and Reel,

Minimum gain

= 1,

Extended temperat ure, 8LD 3×3 DFN

b) MCP6N16-010E/MS: Minimum gain

= 10,

Extended temperature, 8LD MSOP

PART NO. X /XX-XXX

Gain PackageTemperature

Range

Device

Option

[X]

(1)

Tape and Reel

Option

Note 1: Tape and Reel identifier only appears in the

catalog part number description. This identifier is used for ordering purposes and is not printed on the device package. Check with your Microchip Sales Office for package availability with the Tape and Reel option.

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

DS20005318A-page 56  2014 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices:

YSTEM

CERTIFIED BY DNV

== ISO/TS 16949 ==

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device

applications and the like is provided only for your convenience

and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip

devices in life support and/or safety applications is entirely at

the buyer’s risk, and the buyer agrees to defend, indemnify and

hold harmless Microchip from any and all damages, claims,

suits, or expenses resulting from such use. No licenses are

conveyed, implicitly or otherwise, under any Microchip intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, dsPIC, FlashFlex, flexPWR, JukeBlox, K LANCheck, MediaLB, MOST, MOST logo, MPLAB, OptoLyzer, PIC, PICSTART, PIC SST, SST Logo, SuperFlash and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

The Embedded Control Solutions Company and mTouch are registered trademarks of Microchip Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, ECAN, In-Circuit Serial Programming, ICSP, Inter-Chip Connectivity, KleerNet, KleerNet logo, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, RightTouch logo, REAL ICE, SQI, Serial Quad I/O, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.

Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries.

GestIC is a registered trademarks of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries.

All other trademarks mentioned herein are property of their respective companies.

ISBN: 978-1-63276-377-8

EELOQ, KEELOQ logo, Kleer,

32

logo, RightTouch, SpyNIC,

QUALITY MANAGEMENT S

 2014 Microchip Technology Inc. DS20005318A-page 57

Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.

®

MCUs and dsPIC® DSCs, KEELOQ

®

code hopping

Worldwide Sales and Service

AMERICAS

Corporate Office

2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support:

http://www.microchip.com/ support

Web Address:

www.microchip.com

Atlanta

Duluth, GA Tel: 678-957-9614 Fax: 678-957-1455

Austin, TX

Tel: 512-257-3370

Boston

Westborough, MA Tel: 774-760-0087 Fax: 774-760-0088

Chicago

Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075

Cleveland

Independence, OH Tel: 216-447-0464 Fax: 216-447-0643

Dallas

Addison, TX Tel: 972-818-7423 Fax: 972-818-2924

Detroit

Novi, MI Tel: 248-848-4000

Houston, TX

Tel: 281-894-5983

Indianapolis

Noblesville, IN Tel: 317-773-8323 Fax: 317-773-5453

Los Angeles

Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608

New York, NY

Tel: 631-435-6000

San Jose, CA

Tel: 408-735-9110

Canada - Toronto

Tel: 905-673-0699 Fax: 905-673-6509

ASIA/PACIFIC

Asia Pacific Office

Suites 3707-14, 37th Floor Tower 6, The Gateway Harbour City, Kowloon Hong Kong Tel: 852-2943-5100 Fax: 852-2401-3431

Australia - Sydney

Tel: 61-2-9868-6733 Fax: 61-2-9868-6755

China - Beijing

Tel: 86-10-8569-7000 Fax: 86-10-8528-2104

China - Chengdu

Tel: 86-28-8665-5511 Fax: 86-28-8665-7889

China - Chongqing

Tel: 86-23-8980-9588 Fax: 86-23-8980-9500

China - Hangzhou

Tel: 86-571-8792-8115 Fax: 86-571-8792-8116

China - Hong Kong SAR

Tel: 852-2943-5100 Fax: 852-2401-3431

China - Nanjing

Tel: 86-25-8473-2460 Fax: 86-25-8473-2470

China - Qingdao

Tel: 86-532-8502-7355 Fax: 86-532-8502-7205

China - Shanghai

Tel: 86-21-5407-5533 Fax: 86-21-5407-5066

China - Shenyang

Tel: 86-24-2334-2829 Fax: 86-24-2334-2393

China - Shenzhen

Tel: 86-755-8864-2200 Fax: 86-755-8203-1760

China - Wuhan

Tel: 86-27-5980-5300 Fax: 86-27-5980-5118

China - Xian

Tel: 86-29-8833-7252 Fax: 86-29-8833-7256

China - Xiamen

Tel: 86-592-2388138 Fax: 86-592-2388130

China - Zhuhai

Tel: 86-756-3210040 Fax: 86-756-3210049

ASIA/PACIFIC

India - Bangalore

Tel: 91-80-3090-4444 Fax: 91-80-3090-4123

India - New Delhi

Tel: 91-11-4160-8631 Fax: 91-11-4160-8632

India - Pune

Tel: 91-20-3019-1500

Japan - Osaka

Tel: 81-6-6152-7160 Fax: 81-6-6152-9310

Japan - Tokyo

Tel: 81-3-6880- 3770 Fax: 81-3-6880-3771

Korea - Daegu

Tel: 82-53-744-4301 Fax: 82-53-744-4302

Korea - Seoul

Tel: 82-2-554-7200 Fax: 82-2-558-5932 or 82-2-558-5934

Malaysia - Kuala Lumpur

Tel: 60-3-6201-9857 Fax: 60-3-6201-9859

Malaysia - Penang

Tel: 60-4-227-8870 Fax: 60-4-227-4068

Philippines - Manila

Tel: 63-2-634-9065 Fax: 63-2-634-9069

Singapore

Tel: 65-6334-8870 Fax: 65-6334-8850

Taiwan - Hsin Chu

Tel: 886-3-5778-366 Fax: 886-3-5770-955

Taiwan - Kaohsiung

Tel: 886-7-213-7830

Taiwan - Taipei

Tel: 886-2-2508-8600 Fax: 886-2-2508-0102

Thailand - Bangkok

Tel: 66-2-694-1351 Fax: 66-2-694-1350

EUROPE

Austria - Wels

Tel: 43-7242-2244-39 Fax: 43-7242-2244-393

Denmark - Copenhagen

Tel: 45-4450-2828 Fax: 45-4485-2829

France - Paris

Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79

Germany - Dusseldorf

Tel: 49-2129-3766400

Germany - Munich

Tel: 49-89-627-144-0 Fax: 49-89-627-144-44

Germany - Pforzheim

Tel: 49-7231-424750

Italy - Milan

Tel: 39-0331-742611 Fax: 39-0331-466781

Italy - Venice

Tel: 39-049-7625286

Netherlands - Drunen

Tel: 31-416-690399 Fax: 31-416-690340

Poland - Warsaw

Tel: 48-22-3325737

Spain - Madrid

Tel: 34-91-708-08-90 Fax: 34-91-708-08-91

Sweden - Stockholm

Tel: 46-8-5090-4654

UK - Wokingham

Tel: 44-118-921-5800 Fax: 44-118-921-5820

03/25/14

DS20005318A-page 58  2014 Microchip Technology Inc.

Datasheet MCP6N16 Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

Zero-Drift Instrumentation Amplifier

Features:

Description:

Typical Application Circuit

Typical Applications:

Design Aids:

Package Types

Minimum Gain Options

TABLE 1: KEY DIFFERENTIATING SPECIFICATIONS

1.0 ELECTRICAL CHARACTERISTICS

1.1 Absolute Maximum Ratings †

1.2 Specifications

TABLE 1-1: DC ELECTRICAL SPECIFICATIONS

TABLE 1-2: AC ELECTRICAL SPECIFICATIONS

TABLE 1-3: DIGITAL ELECTRICAL SPECIFICATIONS

TABLE 1-4: TEMPERATURE SPECIFICATIONS

1.3 Timing Diagrams

FIGURE 1-1: Amplifier Start-Up Timing Diagram.

FIGURE 1-2: Common Mode Input Overdrive Recovery Timing Diagram.

FIGURE 1-3: Differential Mode Input Overdrive Recovery Timing Diagram.

FIGURE 1-4: Output Overdrive Recovery Timing Diagram.

FIGURE 1-5: POR Timing Diagram.

FIGURE 1-6: EN Timing Diagram .

1.4 DC Test Circuits

FIGURE 1-7: Simple Test Circuit for Common Mode (Input Offset).

TABLE 1-5: RESULTS

FIGURE 1-8: Simple Test Circuit for Differential Mode.

FIGURE 1-9: Input Offset Error vs. Common Mode Input Voltage.

FIGURE 1-10: Differential Input Error vs. Differential Input Voltage.

2.0 TYPICAL PERFORMANCE CURVES

2.1 DC Precision

FIGURE 2-40: CMRR vs. Ambient Temperature.

FIGURE 2-41: CMRR2 vs. Ambient Temperature.

FIGURE 2-42: PSRR vs. Ambient Temperature.

FIGURE 2-43: DC Open-Loop Gain vs. Ambient Temperature.

FIGURE 2-48: Gain Error vs. Ambient Temperature.

2.2 Other DC Voltages and Currents

FIGURE 2-52: Input Voltage Range Headroom vs. Ambient Temperature.

FIGURE 2-53: Normalized Differential Input Voltage Range vs. Ambient Temperature.

FIGURE 2-55: Output Voltage Headroom vs. Ambient Temperat ure.

FIGURE 2-56: Supply Current vs. Power Supply Voltage.

FIGURE 2-54: Output Voltage Headroom vs. Output Current Magnitude.

FIGURE 2-57: Supply Current vs. Common Mode Input Voltage.

FIGURE 2-58: Output Short-Circuit Current vs. Power Supply Voltage.

FIGURE 2-59: Power-On Reset Trip Voltages.

FIGURE 2-60: Power-On Reset Trip Voltages vs. Temperature.

2.3 Frequency Response

FIGURE 2-61: CMRR vs. Frequency.

FIGURE 2-62: PSRR vs. Frequency.

FIGURE 2-65: Phase Margin vs. Ambient Temperature.

FIGURE 2-63: Open-Loop Gain vs. Frequency.

FIGURE 2-66: Closed-Loop Output Impedance vs. Frequency.

FIGURE 2-67: Gain Peaking vs. Normalized Capacitive Load.

FIGURE 2-70: EMIRR vs. Input Voltage, with f = 900 MHz.

FIGURE 2-71: EMIRR vs. Input Voltage, with f = 1800 MHz.

FIGURE 2-69: EMIRR vs. Input Voltage, with f = 400 MHz.

FIGURE 2-72: EMIRR vs. Input Voltage, with f = 2400 MHz.

2.4 Noise

FIGURE 2-73: Input Noise Voltage Density and Integrated Input Noise Voltage vs. Frequency.

FIGURE 2-74: Input Noise Voltage Density vs. Input Common Mode Voltage.

2.5 Time Response

FIGURE 2-80: Input Offset Voltage vs. Time with Temperature Change.

FIGURE 2-81: Input Offset Voltage vs. Time at Power-Up.

FIGURE 2-86: Small Signal Step Response.

FIGURE 2-87: Large Signal Step Response.

FIGURE 2-89: Differential Input Overdrive Recovery Time vs. Normalized Gain.

FIGURE 2-90: Output Overdrive Recovery vs. Time.

FIGURE 2-88: Differential Input Overdrive Recovery vs. Time.

FIGURE 2-91: Output Overdrive Recovery Time vs. Normalized Gain.

FIGURE 2-92: Power Supply On and Off and Output Voltage vs. Time.

2.6 Enable Response

FIGURE 2-96: Enable Turn-On Time vs. Ambient Temperature.

FIGURE 2-95: Normalized Enable Input Trip and Hysteresis Voltages vs. Ambient Temperature.

FIGURE 2-97: Power Supply Current in Shutdown vs. Power Supply Voltage.

FIGURE 2-98: Output Leakage Current in Shutdown vs. Output Voltage.

3.0 PIN DESCRIPTIONS