Datasheet MCP65R41, MCP65R46 Datasheet

MCP65R41/6

V

OUT

V

DD

R

2

R

F

R

3

V

REF

V

PU

RPU*

* Pull-up resistor required for the MCP65R46 only.

R

4

Thermistor

V

REF

Over Temperature Alert

6

4

SOT23-6

MCP65R41/6

1
2
3

-

+

5

OUT

V

SS

+IN

V

DD

V

REF

-IN

3 µA Comparator with Integrated Reference Voltage

Features

• Factory Set Reference Voltage

- Available Voltage: 1.21V and 2.4V

- Tolerance: ±1% (typical)

• Low Quiescent Current: 2.5 µA (typical)

• Propagation Dela y: 4 µs with 100 mV overdrive

• Input Offset Voltage: ±3mV (typical)

• Rail-to-Rail Input: V

• Output Options:

- MCP65R41  Push-Pull

- MCP65R46 Open-Drain

• Wide Supply Voltage Range: 1.8V to 5.5V

• Packages: SOT23-6

- 0.3V to VDD + 0.3V

SS

Typical Applications

• Laptop computers

• Mobile Phones

• Hand-held Metering Systems

• Hand-held Electronics

• RC Timers

• Alarm and Monitoring Circuits

• Window Co mparators

Description

The Microchip Technology Inc. MCP65R41/6 family of
push-pull and open-drain output comparators are
offered with integrated Reference Voltages of 1.21V
and 2.4V. This family provides ±1% (typical) tolerance
while consuming 2.5 µA (typical) current. These
comparators operate with a single-supply voltage as
low as 1.8V to 5.5V, which makes them ideal for low
cost and/or battery powered applications.

These comparators are optimized for low power,
single-supply applications with greater than rail-to-rail
input operation. The output li mits suppl y current surge s
and dynamic power consumption while switching. The
internal input hysteresis eliminates output switching
due to internal noise voltage, reducing current draw.
The MCP65R41 output interfaces to CMOS/TTL logic.
The open-drain output de vice MCP65 R46 can be used
as a level-shifter from 1.6V to 10V using a pull-up
resistor. It can also be used as a wired-OR logic.

This family of devices is available with 6 lead SOT-23
package.

Package Types

Design Aids

• Microchip Advanced Part Selector (MAPS)

• Analog Demonstration and Evaluation Boards

Typical Application

 2010 Microchip Technology Inc. DS22269A-page 1

MCP65R41/6

NOTES:

DS22269A-page 2  2010 Microchip Technology Inc.

MCP65R41/6

1.0 ELECTRICAL CHARACTERISTICS

†Notice: S tress es ab ove th ose li ste d under “Maxim um

Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of
the device at tho se or any oth er conditions ab ove those

1.1 Absolute Maximum Ratings†

VDD - VSS.......................................................................7.0V

All other inputs and outputs...........V

Difference Input voltage ......................................|V

Output Short Circuit Current ....................................±25 mA

Current at Input Pins ..................................................±2 mA

Current at Output and Supply Pins ..........................±50 mA

Storage temperature............... .... .. .. ....... .. .. .-65°C to +150°C

Ambient temperature with power applied....-40°C to +125°C

Junction temperature ................................................ +150°C

ESD protection on all pins (HBM/MM)4 kV/200V

ESD protection on MCP65R46 OUT pin (HBM/MM).............

4 kV/175V

– 0.3V to VDD + 0.3V

SS

DD

- VSS|

indicated in the operational listings of this specification
is not implied. Exposure to maximum rating conditions
for extended periods may affect device reliability.

DC CHARACTERISTICS

Unless otherwise indicated, all limits are specified for: VDD = +1.8V to +5.5V, VSS = GND, TA = +25°C, V

/2, V

V

DD

and T

IN-

= -40°C to 125°C.

A

= VSS, RL= 100 k to VDD/2 (MCP65R41 only), and R

= 2.74 k to VDD (MCP65R46 only),

Pull-Up

Parameters Sym Min Typ Max Units Conditions

Power Supply

Supply Voltage V
Quiescent Current per Comparator I

DD
Q

1.8 — 5.5 V
—2.5 4 µAI

OUT

= 0

Input

Input Voltage Range V
Common-Mode Rejection Ratio

= 5V

V

DD

CMRR 55 70 — dB V

CMR

VSS0.3 — VDD+0.3 V

= -0.3V to 5.3V

CM

50 65 — dB VCM = 2.5V to 5. 3V
55 70 — dB MCP65R41,

V

= -0.3V to 2.5V

CM

50 70 — dB MCP65R46,

= -0.3V to 2.5V

V

CM

Power Supply Rejection Ratio PSRR 63 80 — dB V
Input Offset Voltage V

Drift with Temperature V

Input Hysteresis Voltage V

Drift with Temperature V
Drift with Temperature V

HYST

HYST

Input Bias Current I

TA = +85°C I
TA = +125°C I

Input Offset Current I

OS

/T — ±10 — µV/°C VCM = V

OS
HYST

/T — 6 — µV/°C VCM = V

/T

B
B
B

OS

-10 ±3 +10 mV VCM = V

13.3 5 mVVCM = V

2

— 5 —µV/°C2VCM = V
—1 —pAV
—50 — pAVCM = V
— — 5000 pA VCM = V
— ±1 — pAVCM= V

= V

CM

SS
SS
SS
SS
SS
SS

CM = VSS

SS
SS

SS

(Note 1)

(Note 1)

Note 1: The input offset vo lt a ge is the c ente r (ave rage) of the input-referred trip points. Th e inp ut hy ste res is is the

difference between the input-referred trip points.

2: Limit the output current to Absolute Maximum Rating of 30 mA.
3: Do not short the output of the MCP65R46 comparators above V

+ 10V.

SS

4: The low power reference voltage pin is designed to drive small capacitive loads. See Section 4.5.2.

IN+

=

 2010 Microchip Technology Inc. DS22269A-page 3

MCP65R41/6

DC CHARACTERISTICS (CONTINUED)

Unless otherwise indicated, all limits are specified for: VDD = +1.8V to +5.5V, VSS = GND, TA = +25°C, V

V

/2, V

DD

IN-

= -40°C to 125°C.

and T

A

= VSS, RL= 100 k to VDD/2 (MCP65R41 only), and R

= 2.74 k to VDD (MCP65R46 only),

Pull-Up

Parameters Sym Min Typ Max Units Conditions

Common Mode/

ZCM/Z

DIFF

—1013||4 — ||pF

Differential Input Impedance

Push Pull Output

High Level Output Voltage V
Low Level Output Voltage V
Short Circuit Current I

OH
OL
SC

I

SC

VDD0.2 — — V I

——VSS+0.2 V I

= -2 mA, VDD = 5V

OUT

= 2 mA, VDD = 5V

OUT

—±50 — mA(Note 2) MCP65R41
—±1.5 — mA(Note 2) MCP65R46

Open Drain Output (MCP65R46)

Low Level Output Voltage V
Short Circuit Current I
High-Level Output Current I
Pull-up Voltage V
Output Pin Capacitance C

OL
SC

OH

PU

OUT

——VSS+0.2 V I
—±50 — mA

-100 — — nA VPU= 10V

1.6 — 10 V Note 3
—8 —pF

OUT

= 2 mA

Reference Voltage Output

Initial Reference Tolerance V

TOL

V

REF

-2 ±1 +2 % I

1.185 1.21 1.234 V I

= 0A,

REF

= 1.21V and 2.4V

V

REF

= 0A

REF

2.352 2.4 2.448 V
Reference Output Current I
Drift with Temperature (character-

V

REF

ized but not production tested)

Capacitive Load C

REF

/T — 27 100 ppm V

L

— ±500 — µA V

—22100ppmV
—23100ppmV

= ±2% (maximum)

TOL

= 1.21V, VDD = 1.8V

REF

= 1.21V, VDD = 5.5V

REF

= 2.4V, VDD = 5.5V

REF

—200 — pFNote 4

Note 1: The input offset vo lt a ge is the c ente r (ave rage) of the input-referred trip points. Th e inp ut hy ste res is is the

difference between the input-referred trip points.

2: Limit the output current to Absolute Maximum Rating of 30 mA.
3: Do not short the output of the MCP65R46 comparators above V

+ 10V.

SS

4: The low power reference voltage pin is designed to drive small capacitive loads. See Section 4.5.2.

IN+

=

DS22269A-page 4  2010 Microchip Technology Inc.

MCP65R41/6

V

OUT

V

DD

MCP65R41

VIN=V

SS

200k

200k

200k

200k

50p

V

SS

= 0V

V

OUT

V

DD

MCP65R46

VIN=V

SS

200k

200k

2.74k

100k

50p

V

SS

= 0V

AC CHARACTERISTICS

Unless otherwise indicated, all limits are specified for: VDD = +1.8V to +5.5V, VSS = GND, TA = +25°C,

= VDD/2, Step = 200 mV, Overdrive = 100 mV, RL= 100 k to VDD/2 (MCP65R41 only),

V

IN+

R

= 2.74 k to VDD (MCP65R46 only), and CL = 50 pF.

Pull-Up

Parameters Sym Min Typ Max Units Conditions

Rise Time t
Fall Time t
Propagation Delay (High to Low) t
Propagation Delay (Low to High) t
Propagation Delay Skew t
Maximum Toggle Frequency f

Input Noise Voltage E

PHL
PLH
PDS

MAX

f

MAX

R
F

N

Note 1: Propagation Delay Skew is defined as: t

TEMPERATURE SPECIFICATIONS

Unless otherwise indicated, all limits are specified for: VDD = +1.8V to +5.5V and VSS = GND.

Parameters

Temperature Ranges

Specified Temperature Range T
Operating Temperature Range T
Storage Temperature Range T

Thermal Package Resistances

Thermal Resistance, SOT23-6 

—0.85— µs
—0.85— µs
—48.0µs
—48.0µs
—±0.2— µsNote 1
—160—kHzVDD = 1.8V
—120—kHzVDD = 5.5V
—200—µV

= t

- t

PHL

.

Symbo

l

A
A
A

JA

PDS

PLH

Min Typ Max Units Conditions

-40 — +125 °C

-40 — +125 °C

-65 — +150 °C

— 190.5 — °C/W

P-P

10 Hz to 100 kHz

1.2 Test Circuit Configuration

FIGURE 1-2: Test Circuit for the Open

FIGURE 1-1: Test Circuit for the Push-pull

Output Comparators.

 2010 Microchip Technology Inc. DS22269A-page 5

Drain Comparators.

MCP65R41/6

NOTES:

DS22269A-page 6  2010 Microchip Technology Inc.

MCP65R41/6

0%

10%

20%

30%

40%

50%

-10-8-6-4-20 2 4 6 810
V

OS

(mV)

Occurrences (%)

VDD = 1.8V
V

CM

= V

SS

Avg. = 1.09 mV
StDev = 1.59 mV
850 units

VDD = 5.5V
V

CM

= V

SS

Avg. = 0.61 mV
StDev = 1.48 mV
850 units

-10.0

-8.0

-6.0

-4.0

-2.0

0.0

2.0

4.0

6.0

8.0

10.0

-50 -25 0 25 50 75 100 125
Temperature(°C)

VDD= 1.8V

VDD= 5.5V

V

CM

= V

SS

V

OS

(mV)

-10.0

-8.0

-6.0

-4.0

-2.0

0.0

2.0

4.0

6.0

8.0

10.0

-0.3 0.0 0.3 0.6 0.9 1.2 1.5 1.8 2.1
V

CM

(V)

V

OS

(mV)

V

DD

= 1.8V

TA= +25°C

TA= +125°C

TA= +85°C

TA= -40°C

0%

10%

20%

30%

40%

50%

60%

-60 -48 -36 -24 -12 0 12 24 36 48 60

V

OS

Drift (µV/°C)

Occurrences (%)

VCM = V

SS

Avg. = 9.86 µV/°C
StDev = 4.97 µV/°C
850 Units
T

A

= -40°C to +125°C

-3.0

-2.0

-1.0

0.0

1.0

2.0

3.0

1.5 2.5 3.5 4.5 5.5
V

DD

(V)

V

OS

(mV)

TA= -40°C to +125°C

-10.0

-7.5

-5.0

-2.5

0.0

2.5

5.0

7.5

10.0

-1.0 0.0 1.0 2.0 3.0 4.0 5.0 6.0
V

CM

(V)

V

OS

(mV)

TA = -40°C to +125°C
V

DD

= 5.5V

2.0 TYPICAL PERFORMANCE CURVES

Note: The graphs and tables provid ed follo wing this note are a st atis tical summary b ased on a limit ed nu mber of

samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.

Note: Unless otherwise indicated, VDD = +1.8V to +5.5V, VSS = GND, TA = +25°C, VIN+ = VDD/2, V
R

= 100 k to VDD/2 (MCP65R41 only), R

L

FIGURE 2-1: Input Offset Voltage.

= 2.74 k to VDD/2 (MCP65R46 only) and CL = 50 pF.

Pull-Up

FIGURE 2-4: Input Offset Voltage Drift.

– = GND,

IN

FIGURE 2-2: Input Offset Voltage vs. Temperature.

FIGURE 2-3: Input Offset Voltage vs. Common-Mode Input Voltage.

 2010 Microchip Technology Inc. DS22269A-page 7

FIGURE 2-5: Input Offset Voltage vs. Supply Voltage vs. Temperature.

FIGURE 2-6: Input Offset Voltage vs. Common-Mode Input Voltage.

MCP65R41/6

0%

5%

10%

15%

20%

25%

30%

1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
V

HYST

(mV)

Occurrences (%)

V

DD

= 1.8V
Avg. = 2.4 mV
StDev = 0.17 mV
850 units

V

DD

= 5.5V
Avg. = 2.3 mV
StDev = 0.17 mV
850 units

TA = -40°C

0%

5%

10%

15%

20%

25%

30%

1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
V

HYST

(mV)

Occurrences (%)

V

DD

= 1.8V
Avg. = 3 .0 mV
StDev = 0.17 mV
850 units

V

DD

= 5.5V
Avg. = 2.8 mV
StDev = 0.1 7 mV
850 units

TA = +25°C

0%

5%

10%

15%

20%

25%

30%

1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
V

HYST

(mV)

Occurrences (%)

V

DD

= 1.8V
Avg. = 3.4 mV
StDev = 0.14 mV
850 units

V

DD

= 5.5V
Avg. = 3.2 mV
StDev = 0.13 mV
850 units

TA = +125°C

0%

10%

20%

30%

40%

50%

60%

70%

80%

0 2 4 6 8 10 12 14 16 18 20

V

HYST

Drift, TC1 (µV/°C)

Occurrences (%)

850 Units
T

A

= -40°C to +125°C

V

CM

= V

SS

VDD = 5.5V
Avg. = 5.7 µV/°C
StDev = 0.50 µV/°C

VDD = 1.8V
Avg. = 6.1 µV/°C
StDev = 0.55 µV/°C

0%

10%

20%

30%

-0.50 -0.25 0.00 0.25 0.50 0.75 1.00
V

HYST

Drift, TC2 (µV/°C2)

Occurrences (%)

VDD = 5.5V
V

CM

= V

SS

Avg. = 10.4 µV/°C
StDev = 0.6 µV/ ° C

VDD = 5.5V
Avg. = 0.25 µV/°C

2

StDev = 0.1 µV/°C

2

VDD = 1.8V
Avg. = 0.3 µ V /° C

2

StDev = 0.2 µV/°C

2

1380 Units
T

A

= -40°C to +125°C

V

CM

= V

SS

1.0

2.0

3.0

4.0

5.0

-50 -25 0 25 50 75 100 125
Temperature

(°C)

V

HYST

(mV)

VDD= 5.5V

V

DD

= 1.8V

V

CM

= V

SS

Note: Unless otherwise indicated, VDD = +1.8V to +5.5V, VSS = GND, TA = +25°C, VIN+ = VDD/2, V

= 100 k to VDD/2 (MCP65R41 only), R

R

L

FIGURE 2-7: Input Hysteresis Voltage at -40°C.

= 2.74 k to VDD/2 (MCP65R46 only) and CL = 50 pF.

Pull-Up

FIGURE 2-10: Input Hysteresis Voltage Drift - Linear Temperature Compensation (TC1).

– = GND,

IN

FIGURE 2-8: Input Hysteresis Voltage at +25°C.

FIGURE 2-9: Input Hysteresis Voltage at +125°C.

DS22269A-page 8  2010 Microchip Technology Inc.

FIGURE 2-11: Input Hysteresis Voltage Drift - Quadratic Temperature Compensation (TC2).

FIGURE 2-12: Input Hysteresis Voltage vs. Temperature.

MCP65R41/6

1.0

2.0

3.0

4.0

5.0

-0.3 0.0 0.3 0.6 0.9 1.2 1.5 1.8 2.1
V

CM

(V)

V

HYST

(mV)

V

DD

= 1.8V

TA = +125°C
T

A

= +85°C

T

A

= +25°C

T

A

= -40°C

1.0

2.0

3.0

4.0

5.0

-0.5 0.5 1.5 2.5 3.5 4.5 5.5
V

CM

(V)

V

HYST

(mV)

V

DD

= 5.5V

TA = -40°C
T

A

= +25°C

T

A

= +85°C

T

A

= +125°C

1.0

2.0

3.0

4.0

5.0

1.5 2.5 3.5 4.5 5.5
V

DD

(V)

V

HYST

(mV)

TA = -40°C
T

A

= +25°C

T

A

= +85°C

T

A

= +125°C

0%

10%

20%

30%

40%

50%

60%

70%

80%

90%

100%

0.01.02.03.04.05.0
I

Q

(µV/V)

Occurrences (%)

VDD = 1.8V
850 units

Temp +125°C
Avg. = 3.51 µA
StDev= 0.07 µA

Temp +85°C
Avg. = 3 µA
StDev= 0.07 µA

Temp +25°C
Avg. = 2.52 µA
StDev= 0.08 µA

Temp -40°C
Avg. = 1.93 µA
StDev= 0.0 8 µA

2.0

2.1

2.2

2.3

2.4

2.5

2.6

2.7

2.8

2.9

3.0

-0.5 0.0 0.5 1.0 1.5 2.0 2.5
V

CM

(V)

I

Q

(µA)

DD

= 1.8 V

Sweep VIN- ,V

IN+

=

Sweep V

IN+ ,VIN

- = VDD/2

Sweep VIN- ,V

IN+

= VDD/2

2.0

2.1

2.2

2.3

2.4

2.5

2.6

2.7

2.8

2.9

3.0

-1.00.01.02.03.04.05.06.0

V

CM

(V)

I

Q

(µA)

DD

= 5.5V

Sweep VIN- ,V

IN+

= VDD/2

Sweep V

IN+

,V

IN-

= VDD/2

Note: Unless otherwise indicated, VDD = +1.8V to +5.5V, VSS = GND, TA = +25°C, VIN+ = VDD/2, V

= 100 k to VDD/2 (MCP65R41 only), R

R

L

FIGURE 2-13: Input Hysteresis Voltage vs.

= 2.74 k to VDD/2 (MCP65R46 only) and CL = 50 pF.

Pull-Up

FIGURE 2-16: Quiescent Current.

Common-Mode Input Voltage.

V

– = GND,

IN

FIGURE 2-14: Input Hysteresis Voltage vs. Common-Mode Input Voltage.

FIGURE 2-15: Input Hysteresis Voltage vs. Supply Voltage vs. Temperature.

 2010 Microchip Technology Inc. DS22269A-page 9

FIGURE 2-17: Quiescent Current vs. Common-Mode Input Voltage.

V

FIGURE 2-18: Quiescent Current vs. Common-Mode Input Voltage.

MCP65R41/6

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

0.0 1.0 2.0 3.0 4.0 5.0 6.0
V

DD

(V)

I

Q

(µA)

TA = -40°C
T

A

= +25°C

T

A

= +85°C

T

A

= +125°C

0

2

4

6

8

10

12

14

16

18

10 100 1000 10000 100000

Toggle Frequency (Hz)

I

Q

(µA)

V

DD

= 5.5V

V

DD

= 1.8V

1k

10k

100k

100 mV Over-Drive
V

CM

= VDD/2

R

L

= Open

-120

-80

-40

0

40

80

120

0.0 1.0 2.0 3.0 4.0 5.0 6.0
V

DD

(V)

I

SC

(mA)

TA = -40°C

T

T

A

T

A

TA = -40°C

TA = +85°C

TA = +25°C

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

-1.0 0.0 1.0 2.0 3.0 4.0 5.0 6.0
V

CM

(V)

I

Q

(mA)

V

DD

= 5.5V

Sweep V

IN+ ,VIN

- = VDD/2

Sweep VIN- ,V

IN+

= VDD/2

MCP65R46

1.0

2.0

3.0

4.0

5.0

6.0

7.0

8.0

9.0

10.0

012345678910

V

PU

(V)

I

Q

(µA)

VDD = 2.5V
V

DD

= 1.8V

V

DD

= 5.5V

V

DD

= 4.5V

V

DD

= 3.5V

MCP65R46

-1.0

0.0

1.0

2.0

3.0

4.0

5.0

6.0

7.0

Time (3 µs/div)

V

OUT

(V)

VIN-

V

OUT

V

DD

= 5.5V

VIN+ = VDD/2

Note: Unless otherwise indicated, VDD = +1.8V to +5.5V, VSS = GND, TA = +25°C, VIN+ = VDD/2, V

= 100 k to VDD/2 (MCP65R41 only), R

R

L

FIGURE 2-19: Quiescent Current vs. Supply Voltage vs. T emperature.

0 dB Output Attenuation

= 2.74 k to VDD/2 (MCP65R46 only) and CL = 50 pF.

Pull-Up

FIGURE 2-22: Quiescent Current vs. Common-Mode Input Voltage.

– = GND,

IN

10 100

FIGURE 2-20: Quiescent Current vs. Toggle Frequency.

FIGURE 2-21: Short Circuit Current vs. Supply Voltage vs. T emperature.

DS22269A-page 10  2010 Microchip Technology Inc.

= +25°C
= +85°C

A

FIGURE 2-23: Quiescent Current vs. Pull Up Voltage.

= +125°C

FIGURE 2-24: No Phase Reversal.

MCP65R41/6

0.0

0.5

1.0

1.5

2.0

2.5

3.0

0.0 2.0 4.0 6.0 8.0 10.0
I

OUT

(mA)

V

OL

, V

DD

- V

OH

(V)

V

DD

= 1.8V

VDD - V

OH

TA = +125°C
T

A

= -40°C

V

OL

TA = +125°C
T

A

= -40°C

0%

10%

20%

30%

40%

50%

60%

70%

80%

90%

100%

012345678910

Prop. Delay (µs )

Occurrences ( %)

V

DD

= 1.8V
100 mV Over-Drive
V

CM

= VDD/2

t

PLH

Avg. = 3.92 µs
StDev= 0.45 µs
850 units

t

PHL

Avg. = 3.53 µs
StDev= 0.27 µs
850 units

MCP65 R41

0%

10%

20%

30%

40%

50%

60%

70%

80%

90%

100%

012345678910

Prop. Delay (µs)

Occurrences ( %)

V

DD

= 5.5V

100 mV Over-Drive
V

CM

= VDD/2

t

PHL

Avg. = 4.76 µs
StDev = 0.38 µs
850 units

t

PLH

Avg. = 4.97 µs

850 units

MCP65R41

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

0 5 10 15 20 25

I

OUT

(mA)

V

OL

, V

DD

- V

OH

(V)

V

DD

V

OL

T

A

TA = -40°C

V

DD

- V

OH

TA = +125°C
T

A

= -40°C

0%

10%

20%

30%

40%

50%

60%

70%

80%

012345678910

Prop. Delay (µs)

Occurrences ( %)

VDD= 1.8V
100 mV Over-Drive
V

CM

= VDD/2

t

PLH

Avg. = 2.5 µs
StDev= 0.15 µs
850 units

t

PHL

Avg. = 3.6 µs
StDev= 0.19 µs
850 units

MCP65R46

0%

10%

20%

30%

40%

50%

60%

70%

80%

012345678910

Prop. Delay (µs)

Occurrences ( %)

V

DD

= 5.5V
100 mV Over-Drive
V

CM

= VDD/2

t

PLH

Avg. = 3.1 µs

850 units

t

PHL

Avg. = 4.9 µs
StDev = 0.26 µs
850 units

MCP65 R4 6

Note: Unless otherwise indicated, VDD = +1.8V to +5.5V, VSS = GND, TA = +25°C, VIN+ = VDD/2, V

= 100 k to VDD/2 (MCP65R41 only), R

R

L

FIGURE 2-25: Output Headroom vs. Output Current.

= 2.74 k to VDD/2 (MCP65R46 only) and CL = 50 pF.

Pull-Up

= 5.5V

= +125° C

FIGURE 2-28: Output Headroom vs. Output Current.

– = GND,

IN

FIGURE 2-26: Low-to-High and High-to-Low Propagation Delays.

FIGURE 2-27: Low-to-High and High-to-Low Propagation Delays.

 2010 Microchip Technology Inc. DS22269A-page 11

FIGURE 2-29: Low-to-High and High-to-Low Propagation Delays.

StDev = 0.16 µs

StDev = 0.4 1 µs

FIGURE 2-30: Low-to-High and High-to-Low Propagation Delays .

MCP65R41/6

0

1

2

3

4

5

6

7

8

0.00 0.50 1.00 1.50 2.00
V

CM

(V)

Prop. De la y (ns)

t

t

V

DD

= 1.8 V

100 mV Over-

MCP65 R41

Prop. Delay (µs)

0

1

2

3

4

5

6

7

8

0.01.02.03.04.05.06.0
V

CM

(V)

Prop. De la y (ns)

t
t

V

DD

= 5.5V

100 mV Over-Drive

Prop. Delay (µs)

0

4

8

12

16

20

1.5 2.5 3.5 4.5 5.5
V

DD

(V)

Prop. Delay (ns)

t

PHL

, 10 mV Over-Drive

t

PLH

, 10 mV Over-Drive

t

PHL

t

PLH

VCM = VDD/2 MCP65R 4 1

Prop. Delay (µs)

0

1

2

3

4

5

6

7

8

0.0 0.5 1.0 1.5 2.0
V

CM

(V)

Prop. De la y (ns)

t
t

V

DD

= 1.8V

100 mV Ov er-D riv e

MCP65 R46

Prop. Delay (µs)

0

1

2

3

4

5

6

7

8

0.0 1.0 2.0 3.0 4.0 5.0 6.0
V

CM

(V)

Prop. De la y (ns)

t

PLH

t

V

DD

= 5.5V

100 mV Over -Drive

MCP65R 4 6

Prop. Delay (µs)

0

5

10

15

20

25

1.52.53.54.55.5
V

DD

(V)

Prop. Delay (ns)

t

PHL

t

PLH

t

PHL

t

PLH

VCM = VDD/2

MCP65 R46

Prop. Delay (µs)

Note: Unless otherwise indicated, VDD = +1.8V to +5.5V, VSS = GND, TA = +25°C, VIN+ = VDD/2, V

= 100 k to VDD/2 (MCP65R41 only), R

R

L

PLH

PHL

FIGURE 2-31: Propagation Delay vs. Common-Mode Input Voltage.

MCP65R41

PLH
PHL

= 2.74 k to VDD/2 (MCP65R46 only) and CL = 50 pF.

Pull-Up

PLH

PHL

FIGURE 2-34: Propagation Delay vs. Common-Mode Input Voltage.

PHL

– = GND,

IN

FIGURE 2-32: Propagation Delay vs. Common-Mode Input Voltage.

, 100 mV Over-Drive
, 100 mV Over-Drive

FIGURE 2-33: Propagation Delay vs. Supply Voltage.

DS22269A-page 12  2010 Microchip Technology Inc.

FIGURE 2-35: Propagation Delay vs. Common-Mode Input Voltage.

, 10 mV Over-Driv e
, 10 mV Over-Driv e

, 100 mV Over-Drive
, 100 mV Over-Drive

FIGURE 2-36: Propagation Delay vs. Supply Voltage.

MCP65R41/6

0

2

4

6

8

10

-50 -25 0 25 50 75 100 125
Temperature

(°C)

Prop. De la y (ns)

100 mV Over-Drive
V

CM

= VDD/2

t

PHL

, VDD = 5.5V

t

PHL

, VDD = 1.8V

t

PLH

, V

DD

t

PLH

, V

DD

MCP65R41

Prop. Delay (µs)

1

10

100

0.01 0.1 1 10 100

Capacitive Load (nf)

Prop. De lay (µs)

10 100

VDD = 5.5V, t

PLH

VDD = 5.5V, t

PHL

100 mV Over-Drive
V

CM

= VDD/2

VDD = 1.8V, t

PLH

VDD = 1.8V, t

PHL

MCP65R41

0

5

10

15

20

25

30

35

40

45

50

0.001 0.01 0.1 1
Over-Drive (mV)

Prop. De la y (ns)

t

PHL

, VDD = 5.5V

t

PHL

, VDD = 1.8V

VCM = VDD/2

t

PLH

, VDD = 5.5 V

t

PLH

, VDD = 1.8 V

MCP65R41

Prop. Delay (µs)

Prop. Delay (ns)

0

2

4

6

8

10

-50 -25 0 25 50 75 100 125
Temperature(°C)

100mV Over-Drive
V

CM

= VDD/2

t

PLH

, VDD= 5.5V

t

PLH

, VDD= 1.8V

t

PHL

, VDD= 5.5V

t

PHL

, VDD= 1.8V

MCP65R46

Prop. Delay (µs)

1

10

100

1000

0.01 0.1 1 10 100
Capacitive Load (nf)

Prop. De lay (µs)

100 mV Over-Drive
V

CM

= VDD/2

VDD = 1.8V, t

PLH

VDD = 5.5V, t

PLH

VDD = 1.8V, t

PHL

VDD = 5.5V, t

PHL

MCP65R46

0

5

10

15

20

25

30

35

40

45

50

0.001 0.01 0.1 1
Over-Drive (mV)

Prop. De la y (ns)

t

PHL

, V

DD

t

PHL

, V

DD

VCM = VDD/2

t

PLH

, VDD = 5.5V

t

PLH

, VDD = 1.8V

Prop. Delay (µs)

Note: Unless otherwise indicated, VDD = +1.8V to +5.5V, VSS = GND, TA = +25°C, VIN+ = VDD/2, V

= 100 k to VDD/2 (MCP65R41 only), R

R

L

= 5.5V
= 1.8V

FIGURE 2-37: Propagation Delay vs. Temperature.

= 2.74 k to VDD/2 (MCP65R46 only) and CL = 50 pF.

Pull-Up

FIGURE 2-40: Propagation Delay vs. Temperature.

– = GND,

IN

0.01 0.1

FIGURE 2-38: Propagation Delay vs. Capacitive Load.

FIGURE 2-39: Propagation Delay vs. Input Over-Drive.

 2010 Microchip Technology Inc. DS22269A-page 13

1

FIGURE 2-41: Propagation Delay vs. Capacitive Load.

MCP65R46

= 5.5V
= 1.8V

FIGURE 2-42: Propagation Delay vs. Input Over-Drive.

MCP65R41/6

0%

10%

20%

30%

40%

50%

60%

-1.0 -0.5 0.0 0.5 1.0
Prop. Delay Skew (µ s)

Occurrences (%)

VDD= 1.8V
Avg. = -0.36 µs
StDev = 0.07 µs
850 units

100 mV Over-Drive
V

CM

= VDD/2

VDD= 5.5V
Avg. = -0.21 µs
StDev = 0.07 µs
850 units

MCP6 5R41

50

55

60

65

70

75

80

85

90

-50 -25 0 25 50 75 100 125
Temperature

(°C)

CMRR/PSRR (dB)

CMRR

PSRR

V

CM

= -0.3V to V

DD

+ 0.3V

V

DD

= 5.5V

Input Referred

V

CM

= V

SS

V

MCP65 R41

0%

10%

20%

30%

40%

-5 -4 -3 -2 -1 0 1 2 3 4 5
CMRR (mV/V)

Occurrences (%)

V

DD

= 1.8V

850 units

VCM = -0.3V to VDD/2
Avg. = 0.5 mV/V
StDev = 1.14 mV/V

VCM = VDD/2 to VDD+ 0.3V
Avg. = -0.02 mV/V
StDev = 0.54 mV/V

VCM = -0.3V to V

DD

+ 0.2V

Avg. = 0.23 mV/V
StDev = 0.68 mV/V

0%

10%

20%

30%

40%

50%

60%

70%

80%

-3 -1.5 0 1.5 3
Prop. Delay Skew (n s)

Occurrences (%)

100 mV Ov er-D r ive
V

CM

= VDD/2

V

DD

= 1.8V

Avg. = 1.1 µs
StDev = 0.11 µs
850 units

V

DD

= 5.5V

Avg. = 1.81 µs
StDev = 0.14 µs
850 units

MCP65R46

50

55

60

65

70

75

80

85

90

-50 -25 0 25 50 75 100 125
Temperature

(°C)

CMRR/PSRR (dB)

V

CM

= -0.3V to V

DD

+ 0.3V

V

DD

= 5.5V

Input Referred

V

CM

= V

SS

VDD = 1.8V to 5.5V

MCP65R46

PSRR

CMRR

0%

10%

20%

30%

40%

-2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5
CMRR (mV /V)

Occurrences (%)

V

DD

= 5.5V

850 units

VCM = -0.3V to VDD/2
Avg. = 0.05 mV/V
StDev = 0.46 mV /V

VCM = VDD/2 to VDD+ 0.3V
Avg. = 0.02 mV/V
StDev = 0.25 mV/V

VCM = -0.3V to V

DD

+ 0.3V
Avg. = 0.03 mV/V
StDev = 0.3 mV/V

Note: Unless otherwise indicated, VDD = +1.8V to +5.5V, VSS = GND, TA = +25°C, VIN+ = VDD/2, V

= 100 k to VDD/2 (MCP65R41 only), R

R

L

FIGURE 2-43: Propagation Delay Skew.

= 1.8V to 5.5V

DD

= 2.74 k to VDD/2 (MCP65R46 only) and CL = 50 pF.

Pull-Up

FIGURE 2-46: Propagation Delay Skew.

– = GND,

IN

FIGURE 2-44: Common-Mode Rejection Ratio and Power Supply Rejection Ratio vs. Temperature.

FIGURE 2-45: Common-Mode Rejection Ratio.

DS22269A-page 14  2010 Microchip Technology Inc.

FIGURE 2-47: Common-Mode Rejection Ratio and Power Supply Rejection Ratio vs. Temperature.

FIGURE 2-48: Common-Mode Rejection Ratio.

MCP65R41/6

0.01

0.1

1

10

100

1000

25 50 75 100 125

Temperature

(°C)

I

OS

& I

B

(pA)

I

B

|IOS|

0.01

0.1

1

10

100

1000

0.0 1.0 2.0 3.0 4.0 5.0 6.0
V

CM

(V)

I

OS

& I

B

(pA)

IB @ TA = +125°C
IB @ TA = +85°C

|IOS| @ TA = +125°C

|IOS| @ TA = +85°C

V

DD

= 5.5V

1E+00

1E+01

1E+02

1E+03

1E+04

1E+05

1E+06

1E+07

1E+08

1E+09

1E+10

-0.8 -0.6 -0.4 -0.2
Input Voltage

(V)

Input Current (A)

TA= -40°C

TA= +125°C

TA= +25°C
TA= +85°C

10p

100p

10n

100n

100µ

1m

10m

10µ

1µ

1n

1p

0%

5%

10%

15%

20%

25%

30%

-500 -250 0 250 500
PSRR (µV/V)

Occurrences (%)

V

CM

= V

SS

Avg. = -127.9 µV/V
StDev = 99.88 µV/V
3588 units

1.185

1.190

1.195

1.200

1.205

1.210

1.215

1.220

1.225

1.230

1.235

1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
V

DD

(V)

V

REF

(V)

TA = -40°C
T

A

= +125 ° C

TA = +85°C
T

A

= +25°C

I

REF

= 0A

2.35

2.37

2.39

2.41

2.43

2.45

1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
V

DD

(V)

V

REF

(V)

TA = -40°C
T

A

= +125°C

A

= +85°C

A

= +25°C

I

REF

= 0A

Note: Unless otherwise indicated, VDD = +1.8V to +5.5V, VSS = GND, TA = +25°C, VIN+ = VDD/2, V

= 100 k to VDD/2 (MCP65R41 only), R

R

L

FIGURE 2-49: Input Offset Current and Input Bias Current vs. Temperature.

= 2.74 k to VDD/2 (MCP65R46 only) and CL = 50 pF.

Pull-Up

FIGURE 2-52: Power Supply Rejection Ratio.

– = GND,

IN

FIGURE 2-50: Input Offset Current and Input Bias Current vs. Common-Mode Input Voltage vs. Temperature.

FIGURE 2-51: Input Bias Current vs. Input Voltage vs. Temperature.

 2010 Microchip Technology Inc. DS22269A-page 15

FIGURE 2-53: V

FIGURE 2-54: V

vs. VDD.

REF

vs. VDD.

REF

T
T

MCP65R41/6

1.185

1.190

1.195

1.200

1.205

1.210

1.215

1.220

1.225

1.230

1.235

-0.5 -0.3 -0.1 0.1 0.3 0.5
I

REF

(µA)

V

REF

(V)

VDD = 1.8V

TA = +85°C
T

A

= +25°C

TA = -40°C
T

A

= +125°C

1.185

1.190

1.195

1.200

1.205

1.210

1.215

1.220

1.225

1.230

1.235

-0.5 -0.3 -0.1 0.1 0.3 0.5
I

REF

(µA)

V

REF

(V)

VDD = 5.5V

TA = +85°C
T

A

= +25°C

TA = -40°C
T

A

= +125°C

2.35

2.37

2.39

2.41

2.43

2.45

-0.5 -0.3 -0.1 0.1 0.3 0.5
I

REF

(µA)

V

REF

(V)

VDD = 5.5V

TA = +85°C
T

A

= +25°C

TA = -40°C
T

A

= +125 ° C

1.185

1.190

1.195

1.200

1.205

1.210

1.215

1.220

1.225

1.230

1.235

-50 -25 0 25 50 75 100 125
Temperature (°C)

VDD= 1.8V
Temp. Co. = 27ppm

VDD= 5.5V
Temp. Co . = 22ppm

V

REF

(V)

2.35

2.37

2.39

2.41

2.43

2.45

-50 -25 0 25 50 75 100 125
Tem peratu re (°C)

VDD= 5.5V
Temp. Co . = 23ppm

V

REF

(V)

-20.0

-15.0

-10.0

-5.0

0.0

5.0

10.0

15.0

20.0

1.5 2.5 3.5 4.5 5.5
V

DD

(V)

I

SC

(mA)

Sourcing
Sinking

V

REF

= 1.21V

Note: Unless otherwise indicated, VDD = +1.8V to +5.5V, VSS = GND, TA = +25°C, VIN+ = VDD/2, V

= 100 k to VDD/2 (MCP65R41 only), R

R

L

FIGURE 2-55: V

REF

vs. I

REF

over

= 2.74 k to VDD/2 (MCP65R46 only) and CL = 50 pF.

Pull-Up

FIGURE 2-58: V

REF

vs. Temperature.

Temperature.

– = GND,

IN

FIGURE 2-56: V
Temperature.

FIGURE 2-57: V
Temperature.

DS22269A-page 16  2010 Microchip Technology Inc.

REF

REF

vs. I

vs. I

REF

REF

over

over

FIGURE 2-59: V

vs. Temperature.

REF

FIGURE 2-60: Short Circuit Current vs.
V

.

DD

MCP65R41/6

0%

10%

20%

30%

40%

50%

2.0% 1.2% 0.4% -0.4% -1.2% -2.0%
V

TOL

(mV)

Occurrences (%)

VDD = 5.5V
V

REF

= 1.21V
Avg. = 0.02%
850 units

VDD = 1.8V
V

REF

= 1.21V
Avg. = 0.06%
850 units

0%

10%

20%

30%

40%

50%

2.0% 1.2% 0.4% -0.4% -1.2% -2.0%
V

TOL

(mV)

Occurrences (%)

VDD = 5.5V
V

REF

= 2.4V
Avg. = -0.22%
850 units

Note: Unless otherwise indicated, VDD = +1.8V to +5.5V, VSS = GND, TA = +25°C, VIN+ = VDD/2, V

= 100 k to VDD/2 (MCP65R41 only), R

R

L

= 2.74 k to VDD/2 (MCP65R46 only) and CL = 50 pF.

Pull-Up

FIGURE 2-61: Reference Voltage Tolerance.

– = GND,

IN

FIGURE 2-62: Reference Voltage Tolerance.

 2010 Microchip Technology Inc. DS22269A-page 17

MCP65R41/6

NOTES:

DS22269A-page 18  2010 Microchip Technology Inc.

3.0 PIN DESCRIPTIONS

Descripti ons of the pins are listed in Table 3-1.

TABLE 3-1: PIN FUNCTION TABLE

MCP65R41/6

SOT23-6

1OUTDigital Output
2V
3V
4V
5V
6V

Symbol Description

SS

+ Non-inverting Input

IN

– Inverting Input

IN

REF

DD

MCP65R41/6

Ground

Reference V ol t age Output
Positive Power Supply

3.1 Analog Inputs

The comparator non-inverting and inverting inputs are
high-impedance CMOS inputs with low bias currents.

3.2 Digital Outputs

The comparator outputs are CMOS/TTL compatible
push-pull and open-dra in d igi tal outputs. The push -pul l
is designed to directly interface to a CMOS/TTL com­patible pin while the open-drain output is designed for
level shifting and wired-OR interfaces.

3.3 Analog Outputs

The V

1.21V or 2.4V.

Output pin outputs a reference voltage of

REF

3.4 Power Supply (VSS and VDD)

The positive power supply pin (VDD) is 1.8V to 5.5V
higher than the negati ve power supply pin (V
normal operation, the other pins are at voltages
between V

Typically, these parts are used in a single (positive)
supply configuration. In this case, VSS is connected to
ground and V
need a local bypass capacitor (typically 0.01 µF to

0.1µF) within 2mm of the VDD pin. These can share a
bulk capacitor with the nearby analog parts (within
100 mm), but it is not required.

and VDD.

SS

is connected to the supply. VDD will

DD

SS

). For

 2010 Microchip Technology Inc. DS22269A-page 19

MCP65R41/6

NOTES:

DS22269A-page 20  2010 Microchip Technology Inc.

MCP65R41/6

-3

-2

-1

0

1

2

3

4

5

6

7

8

9

0 100 2 00 300 400 500 600 700 800 900 1000

Time (100 ms/div)

Output Voltage (V)

-30

-25

-20

-15

-10

-5

0

5

10

15

20

25

30

Input Vol tage (10 mV /div)

V

T

V

IN

V

DD

Bond

Pad

Bond

Pad

Bond

Pad

V

DD

VIN+

V

SS

Input

Stage

Bond

Pad

VIN–

V

1

R

1

V

DD

D

1

R

2



VSS– (minimum expected V2)

2mA

V

OUT

V

2

R

2

R

3

D

2

+
–

R

1



VSS– (minimum expected V1)

2mA

V

PU

RPU*

* Pull-up resistor required for the MCP65R46 only.

4.0 APPLICATIONS INFORMATION

The MCP65R41/6 family of Push-Pull and Open-Drain
output compara tors are fabricated o n Microchip’ s state­of-the-art CMOS process. They are suitable for a wide
range of high-speed applications requiring low power
consumption.

4.1 Comparator Inputs

4.1.1 NORMAL OPERATION

The input stage of this family of devices uses three
differential inp ut stages in parallel: one operat es at low
input voltages, one at high input voltages, and one at
mid input volt ag es. W ith t his t opolog y, the input volt age
range is 0.3V above VDD and 0.3V below VSS, while
providing low offset voltage throughout the Common
mode range. The input offset voltage is measured at
both V
operation.

The MCP65R41/6 family has internally-set hysteresis
V

HYST

accuracy, and large enough to eliminate the output
chattering caused by th e comp arat or’s own inp ut nois e
voltage
offset voltage (V
(input-referred) low-high and high-low trip points. Input
hysteresis voltage (V
the same trip points.

- 0.3V and VDD + 0.3V to ensure proper

SS

that is small enough to maintain input offset

E

. Figure 4-1 depicts this behavior. Input

NI

= 5.0V

) is the center (average) of the

OS

) is the di fference between

HYST

-

OU

Hysteresis

4.1.2 INPUT VOLTAGE AND CURRENT
LIMITS

The ESD protection on the inputs can be depicted as
shown in Figure 4-2. This structure was chosen to
protect the input transistors, and to minimize the input
bias current (I

). The input ESD diodes clamp the

B

inputs when trying to go more than one diode drop
below V
far above V

. They also clamp any voltages that go too

SS

; their breakdown volt age is high en ough

DD

to allow a normal ope rati on, and low enough to bypas s
the ESD events within the specified limits.

FIGURE 4-2: Simplified Analog Input ESD Structures.

In order to prevent damage and/or improper operation
of these comparators, the circuit they are connected to
limit the currents (and voltages) at the VIN+ and VIN–
pins (see Absolute Maximum Ratings†). Figure 4-3
shows the recommended approach to protect these
inputs. The internal ESD diodes prevent the input pins

+ and VIN–) from going too far below ground, and

(V

IN

the resistors R
out of the input pin. Diodes D
pin (V

IN

When implemented as sho wn, resis tors R
limit the current through D

and R2 limit the possible current drawn

1

and D2 prevent the input

1

+ and VIN–) from going too far above VDD.

and R2 also

and D2.

1

1

FIGURE 4-1: The MCP 65R4 1/6 Comparators’ Internal Hysteresis Elimi nat es Output Chatter Caused by Input Noise Voltage.

 2010 Microchip Technology Inc. DS22269A-page 21

FIGURE 4-3: Protecting the Analog Inputs.

MCP65R41/6

V

REF

V

IN

V

OUT

V

DD

R

1

R

F

+

-

V

PU

RPU*

V

REF

* Pull-up resistor required for the MCP65R46 only.

V

OUT

High-to-Low Low-to-High

V

DD

V

OH

V

OL

V

SS

V

SS

V

DD

V

THLVTLH

V

IN

V

TLH

V

REF

1

R

1

R

F

-------+







V

OL

R

1

R

F

------ -







–=

V

THL

V

REF

1

R

1

R

F

------ -+







V

OH

R

1

R

F

-------







–=

Where:

V

TLH

= trip voltage from low to high

V

THL

= trip voltage from high to low

It is also possi ble to c onnect the diodes t o the left o f the
resistors R
the diodes D

and R2. In this case, the currents through

1

and D2 need to be limited by some other

1

mechanism. The res istor then ser ves as an in-rus h cur­rent limiter; the DC current int o the input pins (V
V

–) should be very small.

IN

IN

+ and

A significant amount of current can flow out of the
inputs when t he Common mo de volt age (V
ground (V

); see Figure 4-3. The applications that ar e

SS

) is below

CM

high impedance may need to limit the usable voltage
range.

4.1.3 PHASE REVERSAL

The MCP65R41/6 com pa rato r fami ly us es CM OS tra n­sistors at the input. They are designed to prevent
phase inversion w hen the input p ins exc eed the suppl y
voltages. Figure 2-3 shows an input volt age exc ee din g
both supplies with no resulting phase inversion.

4.2 Push-Pull Output

The push-pull outpu t is des ig ned to be compatible with
CMOS and TTL logic, while the output transistors are
configured to give a rail-to-rail output performance.
They are driven with circuitry that minimizes any
switching current (shoot-through current from supply­to-supply) when the outp ut is tran sition ed from high -to­low, or from low-to-high (see Figures 2-18 and 2-19 for
more information).

4.3.1 NON-INVERTING CIRCUIT

Figure 4-4 shows a non-inverting circuit for single-

supply applications using just two resistors. The
resulting hysteresis diagram is shown in Figure4-5.

FIGURE 4-4: Non-inverting Circuit with Hysteresis for Single-Supply.

4.3 Externally Set Hysteresis

A greater fl exibility in selec ting the hystere sis (or the
input trip point s) is achieved by usi ng external resistors.
Hysteresis reduce s output ch atterin g when one inp ut is
slowly moving past the othe r. It also helps in syste ms
where it is best not to cycle between high and low
states too frequently (e.g., air conditioner thermostatic
control). Output chatter also increases the dynamic
supply current.

DS22269A-page 22  2010 Microchip Technology Inc.

FIGURE 4-5: Hysteresis Diagram for the Non-Inverting Circuit.

The trip points for Figures 4-4 and 4-5 are:

EXAMPLE 4-1:

MCP65R41/6

V

IN

V

OUT

V

DD

R

2

R

F

R

3

V

REF

V

PU

RPU*

* Pull-up resistor required for the MCP65R46 only.

V

OUT

High-to-LowLow-to-High

V

DD

V

OH

V

OL

V

SS

V

SS

V

DD

V

TLHVTHL

V

IN

V

23

V

OUT

V

DD

R

23

R

F

+

-

V

SS

V

PU

RPU*

* Pull-up resistor required for the MCP65R46 only .

Where:

R

23

R2R

3

R2R3+

-------------------=

V

23

R

3

R2R3+

-------------------V

REF



=

V

THL

V

OH

R

23

R23RF+

-----------------------







V

23

R

F

R23RF+

----------------------





+=

V

TLH

V

OL

R

23

R23RF+

-----------------------







V

23

R

F

R23RF+

--------------------- -





+=

Where:

V

TLH

= trip voltage from low to high

V

THL

= trip voltage from high to low

4.3.2 INVERTING CIRCUIT

Figure 4-6 shows an inverting circuit for single-supply

using three resistors. The resulting hysteresis diagram
is shown in Figure 4-7.

FIGURE 4-6: Inverting Circuit with Hysteresis.

By using this simplified circuit, the trip voltage can be
calculated using the following equation:

EQUATION 4-1:

Figures 2-23 and 2-26 can be used to determine the

typical values for V

and VOL.

OH

4.4 Bypass Capacitors

With this family of comparators, the power supply pin

for single supply) should have a local bypass

(V

DD

capacitor (i.e., 0.01µF to 0.1 µF) within 2 mm for good
edge rate performance.

4.5 Capacitive Loads

FIGURE 4-7: Hysteresis Diagram for the Inverting Circuit.

In order to determine t he tri p voltages (V
for the circuit shown in Figure 4-6, R
simplified to the Thevenin equivalent circuit with
respect to V

FIGURE 4-8: Theven in Equ iv al ent Circ uit.

 2010 Microchip Technology Inc. DS22269A-page 23

, as shown in Figure 4-8:

REF

and V

THL

and R3 can be

2

TLH

4.5.1 OUT PIN

Reasonable capacitive loads (e.g., logic gates) have
little impact on the propagation delay (see Figure 2-34).
The supply curren t increases wi th the incr easing toggl e
frequency (Figure 2-22), especially with higher
capacitive loads. The output slew rate and propagation
delay performance will be reduced with higher capaci­tive loads.

)

4.5.2 V

REF

PIN

The reference output is designed to interface to the
comparator input pins, either directly or with some
resistive network, su ch as volt age divide r network, with
minimal capacitive load. The recommended capacitive
load is 200 pF (typical). Capacitive loads greater than
2000 pF may cause the V

output to oscillate at

REF

power up.

MCP65R41/6

Guard Ring

V

SS

IN- IN+

V

REF

V

DD

V

DD

R

1

R

2

V

OUT

V

IN

V

REF

V

PU

R

PU

MCP65R46

MCP6041

V

REF

V

DD

R

1

R

2

R

3

V

REF

C

1

V

OUT

MCP65R41

V

OUT

V

DD

R

2

R

F

R

3

V

REF

V

PU

RPU*

* Pull-up resistor required for the
MCP65R46 only.

R

4

Thermistor

V

REF

V

REF

4.6 PCB Surface Leakage

In applications where the low input bias current is
critical, the Printed Circuit Board (PCB) surface
leakage effects need to be considered. Surface
leakage is caused by humidity, dust or other type of
contamination on the board. Under low humidity
conditions, a typical resistance between nearby traces

12

. A 5V difference would cause 5 pA of current

is 10
to flow. This is greater than the MCP65R41/6 family’s
bias current at +25°C (1 pA, typical).

The easiest way to re duce the surface lea kage is to use
a guard ring around the sensitive pins (or traces). The
guard ring is biased at the same voltage as the
sensitive pin. An exa mple of this typ e of layout is sh own
in Figure 4-9.

FIGURE 4-10: Precise Inverting Comparator.

4.7.2 BISTABLE MULTI-VIBRATOR

A simple bistable multi-vibrator design is shown in

Figure 4-11. V

maximum comparato r in te rna l V
oscillation. The output duty cycle changes with V

needs to be between ground a nd the

REF

of 2.4V to achi ev e

REF

REF

.

FIGURE 4-9: Example Guard Ring Layout for Inverting Circuit.

1. Inverting Configuration (Figures 4-6 and 4-9):
a) Connect the guard ring to the non-inverting

input pin (V

+). This biases the guard ring

IN

to the same reference voltage as the
comparator (e.g., VDD/2 or ground).

b) Connect the inverting pin (VIN–) to the input

pad without touching the guard ring.

2. Non-inverting Configuration (Figure4-4):
a) Connect the non-inverting pin (V

IN

input pad without touching the guard ring.

b) Connect the guard ring to the inverting input

pin (V

–).

IN

+) to the

FIGURE 4-11: Bistable Multi-Vibrator.

4.7.3 OVER TEMPERATURE
PROTECTION CIRCUIT

The MCP65R41 device can be used as an over
temperature protection circuit using a thermistor. The

2.4V V

thermistor , the ale rt threshold an d hysteresis threshold.
This is ideal for battery powered applications, where
the change in temperature and output toggle
thresholds would remain fixed as battery voltage

can be used as stable reference to the

REF

decays over time.

4.7 Typical Applications

4.7.1 PRECISE COMPARATOR

Some applications require a higher DC precision. An
easy way to solve this problem is to use an amplifier
(such as the MCP6041, a 600 nA low power and
14 kHz bandwidth op amp) to gain-up the input signal
before it re aches the comparator. Figure 4-10 shows
an example o f t h i s app r oa ch, wh i ch a l so l e ve l shi fts t o

using the Open-Drain option, MCP65R46.

V

PU

DS22269A-page 24  2010 Microchip Technology Inc.

FIGURE 4-12: Over Temperature Alert Circuit.

5.0 PACKAGING INFORMATION

Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanume ric trac ea bil ity code
Pb-free JEDEC designator for Matte Tin (Sn)
* This package is Pb-free. The Pb-fr ee JEDEC designator ( )

can be found on the outer packaging for this package.

Note: In the event the full Microchip part nu mber ca nnot be m arked o n one line , it will

be carried over to the next line, thus limiting the number of available
characters for customer-specific information.

3

e

6-Lead SOT-23

XXNN

Example

HV25

Part Number Code

MCP65R41T-1202E/CHY HVNN
MCP65R41T-2402E/CHY HWNN
MCP65R46T-1202E/CHY HXNN
MCP65R46T-2402E/CHY HYNN

5.1 Package Marking Information

MCP65R41/6

3

e

 2010 Microchip Technology Inc. DS22269A-page 25

MCP65R41/6

6-Lead Plastic Small Outline Transistor (CHY) [SOT-23]

Notes:

1. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.127 mm per side.

2. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Units MILLIMETERS

Dimension Limits MIN NOM MAX

Number of Pins N 6

Pitch e 0.95 BSC

Outside Lead Pitch e1 1.90 BSC

Overall Height A 0.90 – 1.45

Molded Package Thickness A2 0.89 – 1.30

Standoff A1 0.00 – 0.15

Overall Width E 2.20 – 3.20

Molded Package Width E1 1.30 – 1.80

Overall Length D 2.70 – 3.10

Foot Length L 0.10 – 0.60

Footprint L1 0.35 – 0.80

Foot Angle  0° – 30°

Lead Thickness c 0.08 – 0.26

Lead Width b 0.20 – 0.51

b

E

4

N

E1

PIN 1 ID BY

LASER MARK

D

1

2

3

e

e1

A

A1

A2

c

L

L1

φ

Microchip Technology Drawing C04-028B

DS22269A-page 26  2010 Microchip Technology Inc.

MCP65R41/6

6-Lead Plastic Small Outline Transistor (CHY) [SOT-23]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

 2010 Microchip Technology Inc. DS22269A-page 27

MCP65R41/6

NOTES:

DS22269A-page 28  2010 Microchip Technology Inc.

APPENDIX A: REVISION HISTORY

Revision A (December 2010)

• Original Release of this Document.

MCP65R41/6

 2010 Microchip Technology Inc. DS22269A-page 29

MCP65R41/6

NOTES:

DS22269A-page 30  2010 Microchip Technology Inc.

MCP65R41/6

Examples:

a) MCP65R41T-1202E/CHY: Push-Pull Output,

1.2VREF,
Tape and Reel,
6LD SOT-23 Pkg.

b) MCP65R41T-2402E/CHY: Push-Pull Output,

2.4VREF,
Tape and Reel,
6LD SOT-23 Pkg.

a) MCP65R46T-1202E/CHY: Open-Drain Output,

1.2VREF,
Tape and Reel,
6LD SOT-23 Pkg.

b) MCP65R46T-2402E/CHY: Open-Drain Output,

2.4VREF,
Tape and Reel,
6LD SOT-23 Pkg.

PART NO.

X

/XX

Package

Tape and

Device

X

Temperature

Range

-X

X

Reference

XX

Reference

Voltage

Tolerance

Device MCP65R41T: Push-pull Output Comparator

MCP65R46T: Open-drain Output Comparator

Reference Voltage 12 = 1.21V (typical) Initial Reference Voltage

24 = 2.4V (typical) Initial Reference Voltage

Reference Tolerance 02 = 2% Reference Voltage Tolerance

Temperature Range E = -40C to +125C (Extended)

Package CHY = Plastic Small OutlineTransistor, 6-Lead

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

 2010 Microchip Technology Inc. DS22269A-page 31

MCP65R41/6

NOTES:

DS22269A-page 32  2010 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market t oday, when used in the
intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are com mitted to continuously improving the c ode prot ection f eatures of our
products. Attempts to break Microchip’s code protection feature may be a violation of t he Digit al Mill ennium Copyright Act. If such act s
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device

applications and t he lik e is provided only for your convenience

and may be su perseded by upda t es . It is y our responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip

devices in life supp ort and/or safety ap plications is entir ely at

the buyer’s risk, and the buyer agrees to defend, indemnify and

hold harmless M icrochip from any and all dama ges, claims,

suits, or expenses re sulting from such use. No licens es are

conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, dsPIC,
K

EELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,

32

logo, rfPIC and UNI/O are registered trademarks of

PIC
Microchip Technology Incorporated in the U.S.A. and other
countries.

FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MXDEV, MXLAB, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified
logo, MPLIB, MPLINK, mTouch, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance,
TSHARC, UniWinDriver, WiperLock and ZENA are
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.

SQTP is a service mark of Microchip T echnology Incorporated
in the U.S.A.

All other trademarks mentioned herein are property of their
respective companies.

© 2010, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.

Printed on recycled paper.

ISBN: 978-1-60932-781-1

Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.

®

MCUs and dsPIC® DSCs, KEELOQ

®

code hopping

 2010 Microchip Technology Inc. DS22269A-page 33

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France - Paris

Tel: [phone]
Fax: [phone]

Germany - Munich

Tel: [phone]
Fax: [phone]

Italy - Milan

Tel: [phone]
Fax: [phone]

Netherlands - Drunen

Tel: [phone]
Fax: [phone]

Spain - Madrid

Tel: [phone]
Fax: [phone]

UK - Wokingham

Tel: [phone]
Fax: [phone]

08/04/10

DS22269A-page 34  2010 Microchip Technology Inc.