Datasheet MCP6546, MCP6546R, MCP6546U, MCP6547, MCP6548 Datasheet

MCP6546/6R/6U/7/8/9

VIN+

V

IN

–

MCP6546

V

SS

V

DD

OUT

1

2
3
4

8
7
6
5

­+

NC

NC

NC

PDIP, SOIC, MSOP

4

1

2

3

-

+

5

SOT-23-5

V

DD

OUT

V

IN

+

V

SS

VIN–

MCP6546R MCP6547

V

INA

+

V

INA

–

V

SS

1

2
3
4

8
7
6
5

-

OUTA

+

-

+

V

DD

OUTB
V

INB

–

V

INB

+

V

IN

+

V

IN

–

MCP6548

V

SS

V

DD

OUT

1
2
3
4

8
7
6
5

­+

NC

CS

NC

PDIP, SOIC, MSOP

PDIP, SOIC, MSOP

MCP6549

V

INA

+

V

INA

–

V

SS

1

2

3

4

14

13

12

11

-

OUTA

+-+

V

DD

OUTD

V

IND

–

V

IND

+

10

9

8

5

6

7

OUTB

V

INB

–

V

INB

+

V

INC

+

V

INC

–

OUTC

+

-

-

+

PDIP, SOIC, TSSOP

4

1

2

3

-

+

5

SOT-23-5, SC-70-5

V

SS

OUT

V

IN

+

V

DD

VIN–

MCP6546

4

1

2

3

5

SOT-23-5

V

SS

VIN+

VIN–

V

DD

OUT

MCP6546U

-

+

Open-Drain Output Sub-Microamp Comparators

Features

• Low Quiescent Current: 600 nA/comparator (typ.)

• Rail-to-Rail Input: V

• Open-Drain Output: V

- 0.3V to V

SS

OUT

≤ 10V

DD

+ 0.3V

• Propagation Delay: 4 µs (typ., 100 mV Overdrive)

• Wide Supply Voltage Range: 1.6V to 5.5V

• Single available in SOT-23-5, SC-70-5 * packages

• Available in Single, Dual and Quad

• Chip Select (CS

) with MCP6548

• Low Switching Current

• Internal Hysteresis: 3.3 mV (typ.)

• Temperature Range:

- Industrial: -40°C to +85°C

- Extended: -40°C to +125°C

Typical Applications

• Laptop Computers

• Mobile Phones

• Metering Systems

• Hand-held Electronics

• RC Timers

• Alarm and Monitoring Circuits

• Windowed Comparators

• Multi-vibrators

Description

The Microchip Technology Inc. MCP6546/6R/6U/7/8/9
family of comparators is offered in single (MCP6546,
MCP6546R, MCP6546U), single with chip select (CS)
(MCP6548), dual (MCP6547) and quad (MCP6549)
configurations. The outputs are open-drain and are
capable of driving heavy DC or capacitive loads.

These comparators are optimized for low power,
single-supply application with greater than rail-to-rail
input operation. The output limits supply current surges
and dynamic power consumption while switching. The
open-drain output of the MCP6546/6R/6U/7/8/9 family
can be used as a level-shifter for up to 10V using a pull­up resistor. It can also be used as a wired-OR logic.
The internal Input hysteresis eliminates output switch­ing due to internal noise voltage, reducing current draw.
These comparators operate with a single-supply
voltage as low as 1.6V and draw a quiescent current of
less than 1 µA/comparator.

The related MCP6541/2/3/4 family of comparators from
Microchip has a push-pull output that supports rail-to­rail output swing and interfaces with CMOS/TTL logic.

* SC-70-5 E-Temp parts not avaliable at this release

the data sheet

.

MCP6546U SOT-23-5 is E-Temp only.

of

Related Devices

• CMOS/TTL-Compatible Output: MCP6541/2/3/4

Package Types

© 2007 Microchip Technology Inc. DS21714F-page 1

MCP6546/6R/6U/7/8/9

1.0 ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings †

VDD - VSS.........................................................................7.0V

Open-Drain output............................................... V

Analog Input (V

All other inputs and outputs ........... V

+, VIN-)††............. VSS - 1.0V to VDD + 1.0V

IN

– 0.3V to VDD + 0.3V

SS

Difference Input voltage ...................................... |V

+ 10.5V

SS

DD

– VSS|

† Notice: Stresses above those listed under “Absolute Maxi­mum Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at those or any other conditions above those indicated
in the operational listings of this specification is not implied.
Exposure to maximum rating conditions for extended periods
may affect device reliability.

†† See Section 4.1.2 “Input Voltage and Current

Limits”

Output Short-Circuit Current .................................continuous

Current at Input Pins ....................................................±2 mA

Current at Output and Supply Pins ............................±30 mA

Storage temperature .....................................-65°C to +150°C

Maximum Junction Temperature (T

) .......................... +150°C

J

ESD protection on all pins:

(HBM;MM) .....................................2 kV;200V (MCP6546U)

(HBM;MM) ................................ 4 kV; 200V (all other parts)

DC CHARACTERISTICS

Electrical Specifications: Unless otherwise indicated, VDD = +1.6V to +5.5V, VSS = GND, TA = 25°C, VIN+ = VDD/2, VIN– = VSS,

R

=2.74kΩ to VPU = VDD (Refer to Figure 1-3).

PU

Parameters Sym Min Typ Max Units Conditions

Power Supply

Supply Voltage V

Quiescent Current
(per comparator)

DD

I

Q

Input

Input Voltage Range V

CMRVSS

Common Mode Rejection Ratio CMRR 55 70 — dB V

Common Mode Rejection Ratio CMRR 50 65 — dB V

Common Mode Rejection Ratio CMRR 55 70 — dB V

Power Supply Rejection Ratio PSRR 63 80 — dB V

Input Offset Voltage V

Drift with Temperature ΔV

Input Hysteresis Voltage V

Linear Temp. Co. TC

Quadratic Temp. Co. TC

Input Bias Current I

At Temperature (I-Temp parts) I

At Temperature (E-Temp parts) I

Input Offset Current I

Common Mode Input Impedance Z

Differential Input Impedance Z

OS

OS

HYST

B

B

B

OS

CM

DIFF

/ΔT

1

2

Note 1: The input offset voltage is the center of the input-referred trip points. The input hysteresis is the difference between the

input-referred trip points.

2: V

at differential temperatures is estimated using: V

HYST

3: Input bias current at temperature is not tested for the SC-70-5 package
4: Do not short the output above V

V

test limit was VDD before Dec. 2004 (week code 52).

PU

1.6 — 5.5 V VPU ≥ V

0.3 0.6 1 µA I

− 0.3 — V

+ 0.3 V

DD

-7.0 ±1.5 +7.0 mV VCM = V

— ±3 — µV/°C TA = -40°C to +125°C, VCM = V

A

1.5 3.3 6.5 mV VCM = V

—6.7 —µV/°CT

— -0.035 — µV/°C2TA = -40°C to +125°C, VCM = V

—1 —pAV

— 25 100 pA TA = +85°C, VCM = V

— 1200 5000 pA TA = +125°C, VCM = V
— ±1 — pA V

DD

= 0

OUT

= 5V, VCM = -0.3V to 5.3V

DD

= 5V, VCM = 2.5V to 5.3V

DD

= 5V, VCM = -0.3V to 2.5V

DD

= V

CM

SS

(Note 1)

SS

SS

(Note 1)

SS

= -40°C to +125°C, VCM = VSS (Note 2)

A

(Note 2)

SS

CM = VSS

(Note 3)

SS

(Note 3)

SS

CM = VSS

—1013||4 — Ω||pF

—1013||2 — Ω||pF

(TA) = V

HYST

+ 10V. Limit the output current to Absolute Maximum Rating of 30 mA. The minimum

SS

+ (TA -25°C) TC1 + (TA - 25°C)2TC2.

HYST

DS21714F-page 2 © 2007 Microchip Technology Inc.

MCP6546/6R/6U/7/8/9

DC CHARACTERISTICS (CONTINUED)

Electrical Specifications: Unless otherwise indicated, VDD = +1.6V to +5.5V, VSS = GND, TA = 25°C, VIN+ = VDD/2, VIN– = VSS,

R

=2.74kΩ to VPU = VDD (Refer to Figure 1-3).

PU

Parameters Sym Min Typ Max Units Conditions

Open-Drain Output

Output Pull-Up Voltage V

High-Level Output Current I

Low-Level Output Voltage V

Short-Circuit Current I

Output Pin Capacitance C

PU

OH

OL

SC

I

SC

OUT

Note 1: The input offset voltage is the center of the input-referred trip points. The input hysteresis is the difference between the

input-referred trip points.

2: V

at differential temperatures is estimated using: V

HYST

3: Input bias current at temperature is not tested for the SC-70-5 package
4: Do not short the output above V

V

test limit was VDD before Dec. 2004 (week code 52).

PU

AC CHARACTERISTICS

Electrical Specifications: Unless otherwise indicated, V

Step = 200 mV, Overdrive = 100 mV, R

Parameters Sym Min Typ Max Units Conditions

Fall Time t

Propagation Delay (High-to-Low) t

Propagation Delay (Low-to-High) t

Propagation Delay Skew t

Maximum Toggle Frequency f

Input Noise Voltage E

Note 1: t

and t

R

depend on the load (RL and CL); these specifications are valid for the indicated load only.

PLH

2: Propagation Delay Skew is defined as: t

=2.74kΩ to VPU = VDD, and CL = 36 pF (Refer to Figure 1-2 and Figure 1-3).

PU

F

PHL

PLH

PDS

MAX

f

MAX

ni

1.6 — 10 V (Note 4)

-100 — — nA VDD = 1.6V to 5.5V, VPU = 10V (Note 4)

V

SS

—V

SS

+ 0.2 V I

= 2 mA, VPU = VDD = 5V

OUT

—±1.5 — mAVPU = VDD = 1.6V (Note 4)

–30—mAV

= VDD = 5.5V (Note 4)

PU

—8 —pF

(TA) = V

HYST

+ 10V. Limit the output current to Absolute Maximum Rating of 30 mA. The minimum

SS

= +1.6V to +5.5V, VSS = GND, TA = 25°C, VIN+ = VDD/2,

DD

+ (TA -25°C) TC1 + (TA - 25°C)2TC2.

HYST

—0.7—µs(Note 1)

—4.08.0µs

—3.08.0µs(Note 1)

—-1.0— µs(Notes 1 and 2)

— 225 — kHz VDD = 1.6V

— 165 — kHz VDD = 5.5V

— 200 — µV

= t

- t

PDS

PLH

PHL

.

10 Hz to 100 kHz

P-P

© 2007 Microchip Technology Inc. DS21714F-page 3

MCP6546/6R/6U/7/8/9

V

IL

High-Z

t

ON

V

IH

CS

t

OFF

V

OUT

-20 pA (typ.)

High-Z

I

SS

I

CS

-20 pA (typ.)-0.6 µA (typ.)

1 pA (typ.) 1 pA (typ.)5 pA (typ.)

V

OL

t

PLH

V

OUT

VIN–

100 mV

100 mV

t

PHL

V

OL

VIN+ = VDD/2

V

OH

MCP6548 CHIP SELECT (CS) CHARACTERISTICS

Electrical Specifications: Unless otherwise indicated, VDD = +1.6V to +5.5V, VSS = GND, TA = 25°C, VIN+ = VDD/2, VIN– = VSS,

R

=2.74kΩ to VPU = VDD, and CL = 36 pF (Refer to Figures 1-1 and 1-3).

PU

Parameters Sym Min Typ Max Units Conditions

CS Low Specifications

CS

Logic Threshold, Low V

CS Input Current, Low I

CS High Specifications

CS

Logic Threshold, High V

CS Input Current, High I

CS Input High, VDD Current I

CS Input High, GND Current I

Comparator Output Leakage I

CS

Dynamic Specifications

CS

Low to Comparator Output Low

O(LEAK)

Turn-on Time

CS High to Comparator Output
High Z Turn-off Time

CS Hysteresis V

CS_HYST

CSL

CSH

DD

SS

t

ON

t

OFF

IL

IH

V

SS

—5—pACS = V

0.8 V

—1—pACS = V

—18—pACS = V

—-20—pACS = V

—1—pAV

— 0.2 V

—VDDV

DD

DD

V

SS

DD

DD

DD

= VSS+10V, CS = V

OUT

—250msCS = 0.2VDD to V

V

– = V

IN

DD

—10—µsCS = 0.8VDD to V

V

– = V

IN

DD

—0.6— VVDD = 5V

OUT

OUT

DD

= VDD/2,

= VDD/2,

FIGURE 1-1: Timing Diagram for the CS
pin on the MCP6548.

DS21714F-page 4 © 2007 Microchip Technology Inc.

FIGURE 1-2: Propagation Delay Timing
Diagram.

MCP6546/6R/6U/7/8/9

V

DD

VSS = 0V

200 kΩ

200 kΩ

100 kΩ

V

OUT

VIN = V

SS

36 pF

MCP654X

R

PU

=

VPU = V

DD

(2 mA)/ V

DD

TEMPERATURE CHARACTERISTICS

Electrical Specifications: Unless otherwise indicated, VDD = +1.6V to +5.5V and VSS = GND.

Parameters Sym Min Typ Max Units Conditions

Temperature Ranges

Specified Temperature Range T

Operating Temperature Range T

Storage Temperature Range T

A

A

A

Thermal Package Resistances

Thermal Resistance, 5L-SC-70 θ
Thermal Resistance, 5L-SOT-23 θ
Thermal Resistance, 8L-PDIP θ
Thermal Resistance, 8L-SOIC θ
Thermal Resistance, 8L-MSOP θ
Thermal Resistance, 14L-PDIP θ
Thermal Resistance, 14L-SOIC θ
Thermal Resistance, 14L-TSSOP θ

JA

JA

JA

JA

JA

JA

JA

JA

Note: The MCP6546/6R/6U/7/8/9 I-temp family operates over this extended temperature range, but with reduced

performance. In any case, the Junction Temperature (T
specification of +150°C.

-40 — +85 °C

-40 — +125 °C Note

-65 — +150 °C

— 331 — °C/W

— 256 — °C/W

—85—°C/W

— 163 — °C/W

— 206 — °C/W

—70—°C/W

— 120 — °C/W

— 100 — °C/W

) must not exceed the absolute maximum

J

1.1 Test Circuit Configuration

This test circuit configuration is used to determine the
AC and DC specifications.

FIGURE 1-3: AC and DC Test Circuit for
the Open-Drain Output Comparators.

© 2007 Microchip Technology Inc. DS21714F-page 5

MCP6546/6R/6U/7/8/9

0%

2%

4%

6%

8%

10%

12%

14%

-7-6-5-4-3-2-101234567

Input Offset Voltage (mV)

Percentage of Occurrences

1200 Samples
V

CM

= V

SS

0%

2%

4%

6%

8%

10%

12%

14%

16%

-14

-12

-10

-8-6-4

-2

02468

101214

Input Offset Voltage Drift (µV/°C)

Percentage of Occurrences

1200 Samples
V

CM

= V

SS

TA = -40°C to +125°C

-1

0

1

2

3

4

5

6

7

012345678910

Time (1 ms/div)

Inverting Input, Output

Voltage (V)

V

OUT

VIN–

VDD = 5.5V

0%

2%

4%

6%

8%

10%

12%

14%

16%

18%

1.62.02.42.83.23.64.04.44.85.25.66.0

Input Hysteresis Voltage (mV)

Percentage of Occurrences

1200 Samples
V

CM

= V

SS

0%

5%

10%

15%

20%

25%

4.6

5.0

5.4

5.8

6.2

6.6

7.0

7.4

7.8

8.2

8.6

9.0

9.4

Input Hysteresis Voltage –

Linear Temp. Co.; TC

1

(µV/°C)

Percentage of Occurrences

596 Samples

V

CM

= V

SS

TA = -40°C to +125°C

VDD = 1.6VVDD = 5.5V

0%

2%

4%

6%

8%

10%

12%

14%

16%

18%

20%

-0.060

-0.056

-0.052

-0.048

-0.044

-0.040

-0.036

-0.032

-0.028

-0.024

-0.020

-0.016

Input Hysteresis Voltage –

Quadratic Temp. Co.; TC

2

(µV/°C2)

Percentage of Occurrences

596 Samples
V

CM

= V

SS

TA = -40°C to +125°C

VDD = 5.5V

VDD = 1.6V

2.0 TYPICAL PERFORMANCE CURVES

Note: The graphs and tables provided following this note are a statistical summary based on a limited number of

samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.

Note: Unless otherwise indicated, VDD = +1.6V to +5.5V, VSS = GND, TA = +25°C, VIN+ = VDD/2, VIN– = GND,
R

= 2.74 kΩ to VPU=VDD, and CL = 36 pF.

PU

FIGURE 2-1: Input Offset Voltage at
V

CM=VSS

.

FIGURE 2-2: Input Offset Voltage Drift at
V

CM=VSS

.

FIGURE 2-4: Input Hysteresis Voltage at
V

CM=VSS

.

FIGURE 2-5: Input Hysteresis Voltage
Linear Temp. Co. (TC

) at VCM=VSS.

1

FIGURE 2-3: The MCP6546/6R/6U/7/8/9
comparators show no phase reversal.

DS21714F-page 6 © 2007 Microchip Technology Inc.

FIGURE 2-6: Input Hysteresis Voltage
Quadratic Temp. Co. (TC

) at VCM=VSS.

2

MCP6546/6R/6U/7/8/9

-1.0

-0.8

-0.6

-0.4

-0.2

0.0

0.2

0.4

0.6

0.8

1.0

-50 -25 0 25 50 75 100 125

Ambient Temperature (°C)

Input Offset Voltage (mV)

VDD = 1.6V

VDD = 5.5V

VCM = V

SS

-2.0

-1.5

-1.0

-0.5

0.0

0.5

1.0

1.5

2.0

-0.4

-0.2

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

Common Mode Input Voltage (V)

Input Offset Voltage (mV)

VDD = 1.6V

TA = +125°C
T

A

= +85°C

T

A

= +25°C

T

A

= -40°C

TA = +125°C

-2.0

-1.5

-1.0

-0.5

0.0

0.5

1.0

1.5

2.0

-0.5

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

Common Mode Input Voltage (V)

Input Offset Voltage (mV)

VDD = 5.5V

TA = +85°C

T

A

= +125°C

T

A

T

A

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

6.5

-50-250 255075100125
Ambient Temperature (°C)

Input Hysteresis Voltage (mV)

VDD = 1.6V

VDD = 5.5V

VCM = V

SS

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

6.5

-0.4

-0.2

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

Common Mode Input Voltage (V)

Input Hysteresis Voltage (mV)

TA = +25°C
T

A

= -40°C

TA = +125°C
T

A

= +85°C

VDD = 1.6V

TA = +125°C

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

6.5

-0.5

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

Common Mode Input Voltage (V)

Input Hysteresis Voltage (mV)

VDD = 5.5V TA = +125°C

T

A

= +85°C

T

A

= +25°C

T

A

= -40°C

Note: Unless otherwise indicated, VDD= +1.6V to +5.5V, VSS= GND, TA= +25°C, VIN+=VDD/2, VIN– = GND,

RPU=2.74kΩ to VPU=VDD, and CL=36pF.

FIGURE 2-7: Input Offset Voltage vs.
Ambient Temperature at V

CM=VSS

.

FIGURE 2-8: Input Offset Voltage vs.
Common Mode Input Voltage at V

DD

= -40°C

= +25°C

=1.6V.

FIGURE 2-10: Input Hysteresis Voltage vs.
Ambient Temperature at V

CM=VSS

.

FIGURE 2-11: Input Hysteresis Voltage vs.
Common Mode Input Voltage at V

DD

=1.6V.

FIGURE 2-9: Input Offset Voltage vs.
Common Mode Input Voltage at V

© 2007 Microchip Technology Inc. DS21714F-page 7

FIGURE 2-12: Input Hysteresis Voltage vs.

= 5.5V.

DD

Common Mode Input Voltage at V

DD

=5.5V.

MCP6546/6R/6U/7/8/9

55

60

65

70

75

80

85

90

-50 -25 0 25 50 75 100 125
Ambient Temperature (°C)

CMRR, PSRR (dB)

Input Referred

PSRR, VIN+ = VSS, VDD = 1.6V to 5.5V

CMRR, VIN+ = -0.3 to 5.3V, VDD = 5.0V

0.1

1

10

100

1000

55 65 75 85 95 105 115 125

Ambient Temperature (°C)

Input Bias, Offset Currents

(pA)

I

B

| IOS |

VDD = 5.5V
V

CM

= V

DD

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6

Common Mode Input Voltage (V)

Quiescent Current

per Comparator (µA)

VDD = 1.6V

Sweep VIN+, VIN– = VDD/2

Sweep VIN–, VIN+ = VDD/2

IQ does not include pull-up resistor current

0.1

1

10

100

1000

10000

0.00.51.01.52.02.53.03.54.04.55.05.5

Common Mode Input Voltage (V)

Input Bias, Offset Currents

(A)

VDD = 5.5V

100f

100p

1p

10p

1n

10n

IB, TA = +125°C

IB, TA = +85°C

IOS, TA = +125°C

IOS, TA = +85°C

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.00.51.01.52.02.53.03.54.04.55.05.5

Power Supply Voltage (V)

Quiescent Current

per Comparator (µA)

TA = +125°C

T

A

= +85°C

T

A

= +25°C

T

A

= -40°C

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

Common Mode Input Voltage (V)

Quiescent Current

per Comparator (µA)

VDD = 5.5V

Sweep VIN+, VIN– = VDD/2

Sweep VIN–, VIN+ = VDD/2

IQ does not include pull-up resistor current

Note: Unless otherwise indicated, VDD= +1.6V to +5.5V, VSS= GND, TA= +25°C, VIN+=VDD/2, VIN– = GND,

RPU=2.74kΩ to VPU=VDD, and CL=36pF.

FIGURE 2-13: CMRR,PSRR vs. Ambient
Temperature.

FIGURE 2-14: Input Bias Current, Input
Offset Current vs. Ambient Temperature.

FIGURE 2-16: Input Bias Current, Input
Offset Current vs. Common Mode Input Voltage.

FIGURE 2-17: Quiescent Current vs.
Power Supply Voltage.

FIGURE 2-15: Quiescent Current vs.
Common Mode Input Voltage at V

DS21714F-page 8 © 2007 Microchip Technology Inc.

DD

=1.6V.

FIGURE 2-18: Quiescent Current vs.
Common Mode Input Voltage at VDD=5.5V.

MCP6546/6R/6U/7/8/9

0.1

1

10

01234567891011

Pull-Up Voltage, V

PU

(V)

Supply Current

per Comparator (µA)

VDD = 2.1V
V

DD

= 2.6V

V

DD

= 3.6V

V

DD

= 4.6V

V

DD

= 5.6V

IDD spike near VPU = 1.3V

VDD = 1.6V

0.1

1

10

0.1 1 10 100
Toggle Frequency (kHz)

Supply Current

per Comparator (µA)

VDD = 5.5V
V

DD

= 1.6V

100 mV Overdrive
V

CM

= VDD/2

I

DD

does not include

pull-up resistor current

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6
Output Current (mA)

Output Voltage Headroom (V)

VDD = 1.6V

VOL–VSS:
T

A

= +125°C

T

A

= +85°C

T

A

= +25°C

T

A

= -40°C

0.1

1

10

-4-3-2-10123456789

Pull-up to Supply Voltage Difference,

V

PU

– VDD (V)

Supply Current

per Comparator (µA)

VDD = 5.6V
V

DD

= 4.6V

V

DD

= 3.6V

V

DD

= 2.6V

VPU = 1.6V to 10.5V

VDD = 1.6V
V

DD

= 2.1V

0

5

10

15

20

25

30

35

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Power Supply Voltage (V)

Output Short Circuit Current

Magnitude (mA)

TA = -40°C

T

A

= +25°C

T

A

= +85°C

T

A

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

0 5 10 15 20 25

Output Current (mA)

Output Voltage Headroom (V)

VDD = 5.5V

TA = +125°C
T

A

= +85°C

T

A

= +25°C

T

A

= -40°C

VOL – VSS:

Note: Unless otherwise indicated, VDD= +1.6V to +5.5V, VSS= GND, TA= +25°C, VIN+=VDD/2, VIN– = GND,

RPU=2.74kΩ to VPU=VDD, and CL=36pF.

FIGURE 2-19: Supply Current vs. Pull-Up
Voltage.

FIGURE 2-20: Supply Current vs. Toggle
Frequency.

FIGURE 2-22: Supply Current vs. Pull-Up
to Supply Voltage Difference.

= +125°C

FIGURE 2-23: Output Short Circuit Current
Magnitude vs. Power Supply Voltage.

FIGURE 2-21: Output Voltage Headroom
vs. Output Current at V

© 2007 Microchip Technology Inc. DS21714F-page 9

DD

=1.6V.

FIGURE 2-24: Output Voltage Headroom
vs. Output Current at VDD=5.5V.

MCP6546/6R/6U/7/8/9

0%

5%

10%

15%

20%

25%

30%

35%

40%

45%

50%

012345678

High-to-Low Propagation Delay (µs)

Percentage of Occurrences

408 Samples
100 mV Overdrive
V

CM

= VDD/2

VDD = 5.5VVDD = 1.6V

0%

5%

10%

15%

20%

25%

30%

35%

40%

45%

50%

-2.0

-1.6

-1.2

-0.8

-0.4

0.0

0.4

0.8

1.2

1.6

2.0

Propagation Delay Skew (µs)

Percentage of Occurrences

VCM = VDD/2

VDD = 1.6V

VDD = 5.5V

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

1.52.02.53.03.54.04.55.05.5

Power Supply Voltage (V)

Propagation Delay (µs)

VCM = VDD/2

t

PHL

10 mV Overdrive

100 mV Overdrive

t

PLH

0%

5%

10%

15%

20%

25%

30%

35%

40%

45%

50%

55%

60%

65%

012345678

Low-to-High Propagation Delay (µs)

Percentage of Occurrences

408 Samples
100 mV Overdrive
V

CM

= VDD/2

VDD = 5.5V

VDD = 1.6V

0

1

2

3

4

5

6

7

8

-50 -25 0 25 50 75 100 125

Ambient Temperature (°C)

Propagation Delay (µs)

100 mV Overdrive
V

CM

= VDD/2

t

PHL

t

PLH

VDD = 5.5V

VDD = 1.6V

1

10

100

1 10 100 1000

Input Overdrive (mV)

Propagation Delay (µs)

VCM = VDD/2

t

PLH

VDD = 5.5V

t

PHL

VDD = 1.6V

Note: Unless otherwise indicated, VDD= +1.6V to +5.5V, VSS= GND, TA= +25°C, VIN+=VDD/2, VIN– = GND,

RPU=2.74kΩ to VPU=VDD, and CL=36pF.

FIGURE 2-25: High-to-Low Propagation
Delay.

408 Samples

100 mV Overdrive

FIGURE 2-26: Propagation Delay Skew.

FIGURE 2-28: Low-to-High Propagation

Delay.

FIGURE 2-29: Propagation Delay vs.
Ambient Temperature.

FIGURE 2-27: Propagation Delay vs.
Power Supply Voltage.

DS21714F-page 10 © 2007 Microchip Technology Inc.

FIGURE 2-30: Propagation Delay vs. Input
Overdrive.

MCP6546/6R/6U/7/8/9

0

1

2

3

4

5

6

7

8

0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6

Common Mode Input Voltage (V)

Propagation Delay (µs)

VDD = 1.6V
100 mV Overdrive

t

PLH

t

PHL

0

1

2

3

4

5

6

7

8

01234567891011

Pull-up Voltage (V)

Propagation Delay (µs)

VCM = VDD/2
V

IN

+ = V

CM

t

PHL

VIN– = 100 mV Overdrive

VDD = 5.5V

VDD = 1.6V t

PLH

0

1

2

3

4

5

6

7

8

0.00.51.01.52.02.53.03.54.04.55.05.5

Common Mode Input Voltage (V)

Propagation Delay (µs)

VDD = 5.5V
100 mV Overdrive

t

PHL

t

PLH

0

20

40

60

80

100

120

140

160

180

200

0 102030405060708090

Load Capacitance (nF)

Propagation Delay (µs)

100 mV Overdrive
V

CM

= VDD/2

t

PLH

t

PHL

VDD = 1.6V

VDD = 5.5V

1.E-01

1.E+00

1.E+01

1.E+02

1.E+03

1.E+04

01234567891011

Output Voltage (V)

Output Leakage Current (A)

TA = +85°C

CS = V

DD

VIN+ = VDD/2
V

IN

– = V

SS

TA = +125°C

TA = +25°C

10n

1n

100p

10p

1p

100f

Note: Unless otherwise indicated, VDD= +1.6V to +5.5V, VSS= GND, TA= +25°C, VIN+=VDD/2, VIN– = GND,

RPU=2.74kΩ to VPU=VDD, and CL=36pF.

FIGURE 2-31: Propagation Delay vs.
Common Mode Input Voltage at V

8

VIN– = 100 mV Overdrive

7

VCM = VDD/2

6

+ = V

V

IN

5

4

3

2

Propagation Delay (µs)

1

0

0 102030405060708090100

CM

Pull-up Resistor, R

VDD = 5.5V

VDD = 1.6V

PU

(k:)

DD

=1.6V.

t

PLH

t

PHL

FIGURE 2-32: Propagation Delay vs.
Pull-up Resistor.

FIGURE 2-34: Propagation Delay vs.
Common Mode Input Voltage at VDD=5.5V.

FIGURE 2-35: Propagation Delay vs. Load
Capacitance.

FIGURE 2-33: Propagation Delay vs.
Pull-up Voltage.

© 2007 Microchip Technology Inc. DS21714F-page 11

FIGURE 2-36: Output Leakage Current

=VDD) vs. Output Voltage (MCP6548 only).

(CS

MCP6546/6R/6U/7/8/9

1.E-11

1.E-10

1.E-09

1.E-08

1.E-07

1.E-06

1.E-05

1.E-04

1.E-03

0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6

Chip Select (CS) Voltage (V)

Supply Current

per Comparator (A)

r

f

Comparator
Turns On

VDD = 1.6V

CS Hysteresis

CS

CS
Low-to-High

1m

1µ

10µ

100n

1n

10n

100p

10p

100µ

0

5

10

15

20

25

30

01234567891011121314

Time (1 ms/div)

Supply Current (µA)

-8.1

-6.5

-4.9

-3.2

-1.6

0.0

1.6

Output Voltage,

Chip Select Voltage (V),

Start-up
I

DD

Charging output

capacitance

VDD = 1.6V

V

OUT

CS

-0.5

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

012345678910

Time (ms)

Chip Select, Output Voltage

(V)

V

OUT

VDD = 5.5V

CS

1.E-11

1.E-10

1.E-09

1.E-08

1.E-07

1.E-06

1.E-05

1.E-04

1.E-03

0.00.51.01.52.02.53.03.54.04.55.05.5

Chip Select (CS) Voltage (V)

Supply Current

per Comparator (A)

r

f

Comparator
Turns On

VDD = 5.5V

1m

1µ

10µ

100n

1n

10n

100p

10p

CS

Low-to-High

CS

Hysteresis

100µ

0

20

40

60

80

100

120

140

160

180

200

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
Time (0.5 ms/div)

Supply Current

per Comparator (µA)

-24

-21

-18

-15

-12

-9

-6

-3

0

3

6

Output Voltage,

Chip Select Voltage (V)

Start-up I

DD

Charging output

capacitance

VDD = 5.5V

V

OUT

CS

1.E-12

1.E-11

1.E-10

1.E-09

1.E-08

1.E-07

1.E-06

1.E-05

1.E-04

1.E-03

1.E-02

-1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0

Input Voltage (V)

Input Current Magnitude (A)

+125°C

+85°C
+25°C

-40°C

10m

1m

100µ

10µ

1µ

100n

10n

1n

100p

10p

1p

Note: Unless otherwise indicated, VDD= +1.6V to +5.5V, VSS= GND, TA= +25°C, VIN+=VDD/2, VIN– = GND,

RPU=2.74kΩ to VPU=VDD, and CL=36pF.

Comparato

Shuts Of

High-to-Low

FIGURE 2-37: Supply Current (shoot
through current) vs. Chip Select (CS
V

= 1.6V (MCP6548 only).

DD

) Voltage at

Comparato

Shuts Of

High-to-Low

CS

FIGURE 2-40: Supply Current (shoot
through current) vs. Chip Select (CS
V

= 5.5V (MCP6548 only).

DD

) Voltage at

FIGURE 2-38: Supply Current (charging
current) vs. Chip Select (CS
(MCP6548 only).

FIGURE 2-39: Chip Select (CS
Response (MCP6548 only).

DS21714F-page 12 © 2007 Microchip Technology Inc.

) pulse at VDD=1.6V

) Step

FIGURE 2-41: Supply Current (charging
current) vs. Chip Select (CS

) pulse at VDD=5.5V

(MCP6548 only).

FIGURE 2-42: Input Bias Current vs. Input
Voltage.

MCP6546/6R/6U/7/8/9

3.0 PIN DESCRIPTIONS

Descriptions of the pins are listed in Table 3-1.

TABLE 3-1: PIN FUNCTION TABLE

MCP6546

PDIP,

SOIC,

MSOP

————5—5V

————6—6V

— — — — 7 — 7 OUTB Digital Output (comparator B)

— — — — — — 8 OUTC Digital Output (comparator C)

——————9V

——————10V

——————12V

——————13V

— — — — — — 14 OUTD Digital Output (comparator D)

—————8—CS

1, 5, 8 — — — — 1, 5 — NC No Internal Connection

MCP6546

SOT-23-5,

SC-70-5

MCP6546R

MCP6546U

MCP6547

MCP6548

Symbol Description

MCP6549

6 1 1 4 1 6 1 OUT, OUTA Digital Output (comparator A)

2443222V

3331333V

IN

IN

–, V

– Inverting Input (comparator A)

INA

+, V

+ Non-inverting Input (comparator A)

INA

7525874VDDPositive Power Supply

+ Non-inverting Input (comparator B)

INB

– Inverting Input (comparator B)

INB

– Inverting Input (comparator C)

INC

+ Non-inverting Input (comparator C)

INC

42524411V

SS

IND

IND

Negative Power Supply

+ Non-inverting Input (comparator D)

– Inverting Input (comparator D)

Chip Select

3.1 Analog Inputs

The comparator non-inverting and inverting inputs are
high-impedance CMOS inputs with low bias currents.

3.2 CS Digital Input

This is a CMOS, Schmitt-triggered input that places the
part into a low power mode of operation.

3.3 Digital Outputs

The comparator outputs are CMOS, open-drain digital
outputs. They are designed to make level shifting and
wired-OR easy to implement.

3.4 Power Supply (VSS and VDD)

The positive power supply pin (VDD) is 1.6V to 5.5V
higher than the negative power supply pin (V
normal operation, the other pins are at voltages
between VSS and VDD, except the output pins which
can be as high as 10V above V

SS

.

Typically, these parts are used in a single (positive)
supply configuration. In this case, V

is connected to

SS

ground and VDD is connected to the supply. VDD will
need a local bypass capacitor (typically 0.01 µF to

0.1 µF) within 2 mm of the V

pin. These can share a

DD

bulk capacitor with nearby analog parts (within
100 mm), but it is not required.

SS

). For

© 2007 Microchip Technology Inc. DS21714F-page 13

MCP6546/6R/6U/7/8/9

Bond

Pad

Bond

Pad

Bond

Pad

V

DD

VIN+

V

SS

Input

Stage

Bond

Pad

VIN–

V

1

MCP6G0X

R

1

V

DD

D

1

R

1

≥

VSS– (minimum expected V1)

2mA

V

OUT

V

2

R

2

R

3

D

2

+

–

R

2

≥

VSS– (minimum expected V2)

2mA

4.0 APPLICATIONS INFORMATION

The MCP6546/6R/6U/7/8/9 family of push-pull output
comparators are fabricated on Microchip’s state-of-the­art CMOS process. They are suitable for a wide range
of applications requiring very low power consumption.

4.1 Comparator Inputs

4.1.1 PHASE REVERSAL

The MCP6546/6R/6U/7/8/9 comparator family uses
CMOS transistors at the input. They are designed to
prevent phase inversion when the input pins exceed
the supply voltages. Figure 2-3 shows an input voltage
exceeding both supplies with no resulting phase
inversion.

4.1.2 INPUT VOLTAGE AND CURRENT
LIMITS

The ESD protection on the inputs can be depicted as
shown in Figure 4-1. This structure was chosen to pro­tect the input transistors, and to minimize input bias
current (IB). The input ESD diodes clamp the inputs
when they try to go more than one diode drop below

. They also clamp any voltages that go too far

V

SS

above V
allow normal operation, and low enough to bypass ESD
events within the specified limits.

; their breakdown voltage is high enough to

DD

FIGURE 4-2: Protecting the Analog
Inputs.

It is also possible to connect the diodes to the left of the
resistors R
the diodes D1 and D2 need to be limited by some other
mechanism. The resistor then serves as in-rush current
limiter; the DC current into the input pins (V
VIN–) should be very small.

A significant amount of current can flow out of the
inputs when the common mode voltage (V
ground (V
high impedance may need to limit the useable voltage
range.

and R2. In this case, the currents through

1

+ and

IN

) is below

); see Figure 2-42. Applications that are

SS

CM

4.1.3 NORMAL OPERATION

The input stage of this family of devices uses two
differential input stages in parallel: one operates at low
input voltages and the other at high input voltages.
With this topology, the input voltage is 0.3V above V
and 0.3V below VSS. The input offset voltage is
measured at both V

- 0.3V and V

SS

proper operation.

The MCP6546/6R/6U/7/8/9 family has internally-set

FIGURE 4-1: Simplified Analog Input ESD
Structures.

In order to prevent damage and/or improper operation
of these amplifiers, the circuits they are in must limit the
currents (and voltages) at the V

+ and VIN– pins (see

IN

hysteresis that is small enough to maintain input offset
accuracy (<7 mV), and large enough to eliminate
output chattering caused by the comparator’s own
input noise voltage (200 µV

P-P

this capability.

Absolute Maximum Ratings † at the beginning of
Section 1.0 “Electrical Characteristics”). Figure 4-3
shows the recommended approach to protecting these
inputs. The internal ESD diodes prevent the input pins

+ and VIN–) from going too far below ground, and

(V

IN

the resistors R1 and R2 limit the possible current drawn
out of the input pin. Diodes D1 and D2 prevent the input
pin (V

IN

When implemented as shown, resistors R
limit the current through D1 and D2.

DS21714F-page 14 © 2007 Microchip Technology Inc.

and R2 also

1

+ and VIN–) from going too far above VDD.

+ 0.3V to ensure

DD

). Figure 4-3 illustrates

DD

FIGURE 4-3: The MCP6546/6R/6U/7/8/9

-3

-2

-1

0

1

2

3

4

5

6

7

8

Time (100 ms/div)

Output Voltage (V)

-30

-25

-20

-15

-10

-5

0

5

10

15

20

25

Input Voltage (10 mV/div)

V

OUT

VIN–

VDD = 5.0V

Hysteresis

V

IN

V

OUT

MCP654X

V

DD

R

2

R

F

R

3

V

PU

R

PU

V

DD

I

OL

I

RF

I

PU

V

OUT

High-to-LowLow-to-High

V

OH

V

OL

V

SS

V

SS

V

DD

V

TLHVTHL

V

IN

V

PU

V

TLH

= trip voltage from low to high

V

THL

= trip voltage from high to low

V

23

V

OUT

MCP654X

V

PU

R

23

R

F

+

-

R

PU

comparators’ internal hysteresis eliminates
output chatter caused by input noise voltage.

4.2 Open-Drain Output

MCP6546/6R/6U/7/8/9

4.4.1 INVERTING CIRCUIT

Figure 4-4 shows an inverting circuit for a single-supply

application using three resistors, besides the pull-up
resistor. The resulting hysteresis diagram is shown in

Figure 4-5.

The open-drain output is designed to make level­shifting and wired-OR logic easy to implement. The
output can go as high as 10V for 9V battery-powered
applications. The output stage minimizes switching cur­rent (shoot-through current from supply-to-supply)
when the output changes state. See Figures 2-15, 2-18
and 2-37 through 2-41, for more information.

4.3 MCP6548 Chip Select (CS)

The MCP6548 is a single comparator with a Chip
Select (CS
current consumption drops to 20 pA (typ.). 1 pA (typ.)
flows through the CS pin, 1 pA (typ.) flows through the
output pin and 18 pA (typ.) flows through the V
as shown in Figure 1-1. When this happens, the
comparator output is put into a high-impedance state.
By pulling CS
pin is left floating, the comparator will not operate
properly. Figure 1-1 shows the output voltage and
supply current response to a CS

The internal CS
glitches when cycling the CS
power, which is especially important in battery-powered
applications.

) pin. When CS is pulled high, the total

pin,

DD

low, the comparator is enabled. If the CS

pulse.

circuitry is designed to minimize

pin. This helps conserve

FIGURE 4-4: Inverting Circuit with
Hysteresis.

FIGURE 4-5: Hysteresis diagram for the
inverting circuit.

In order to determine the trip voltages (V
for the circuit shown in Figure 4-4, R2 and R3 can be
simplified to the Thevenin equivalent circuit with
respect to V

, as shown in Figure 4-6.

DD

THL

and V

TLH

)

4.4 Externally Set Hysteresis

Greater flexibility in selecting hysteresis, or input trip
points, is achieved by using external resistors.

Input offset voltage (V
(input-referred) low-high and high-low trip points. Input
hysteresis voltage (V
the same trip points. Hysteresis reduces output
chattering when one input is slowly moving past the
other, thus reducing dynamic supply current. It also
helps in systems where it is best not to cycle between
states too frequently (e.g., air conditioner thermostatic
control).

© 2007 Microchip Technology Inc. DS21714F-page 15

) is the center (average) of the

OS

) is the difference between

HYST

FIGURE 4-6: Thevenin Equivalent Circuit.

MCP6546/6R/6U/7/8/9

R

23

R2R

3

R2R3+

------------------

=

V

23

R

3

R2R3+

------------------

VDD×=

V

THL

V

PU

R

23

R23RFR

PU

++

----------------------------------------

⎝⎠

⎜⎟

⎛⎞

V

23

RFRPU+

R

23RFRPU

++

---------------------------------------

⎝⎠

⎛⎞

+=

V

TLH

V

OL

R

23

R23RF+

---------------------- -

⎝⎠

⎜⎟

⎛⎞

V

23

R

F

R23RF+

--------------------- -

⎝⎠

⎛⎞

+=

V

TLH

= trip voltage from low to high

V

THL

= trip voltage from high to low

I

OLIPUIRF

+=

I

OL

VPUVOL–

R

PU

--------------------------

⎝⎠

⎛⎞

V

23VOL

–

R

23RF

+

------------------------

⎝⎠

⎛⎞

+=

V

OH

VPUV23–()

R

23RF

+

R

23RFRPU

++

--------------------------------------

⎝⎠

⎛⎞

×=

Guard Ring

V

SS

VIN-V

IN

+

EQUATION 4-1:

Using this simplified circuit, the trip voltage can be
calculated using the following equation:

EQUATION 4-2:

Figure 2-21 and Figure 2-24 can be used to determine

typical values for V

. This voltage is dependent on the

OL

output current IOL as shown in Figure 4-4. This current
can be determined using the equation below:

EQUATION 4-3:

4.6 Capacitive Loads

Reasonable capacitive loads (e.g., logic gates) have
little impact on propagation delay (see Figure 2-27).
The supply current increases with increasing toggle
frequency (Figure 2-30), especially with higher
capacitive loads.

4.7 Battery Life

In order to maximize battery life in portable
applications, use large resistors and small capacitive
loads. Avoid toggling the output more than necessary.
Do not use Chip Select (CS

) too frequently in order to
conserve power. Capacitive loads will draw additional
power at start-up.

4.8 PCB Surface Leakage

In applications where low input bias current is critical,
PCB (Printed Circuit Board) surface leakage effects
need to be considered. Surface leakage is caused by
humidity, dust or other contamination on the board.
Under low-humidity conditions, a typical resistance
between nearby traces is 10
would cause 5 pA of current to flow. This is greater
than the MCP6546/6R/6U/7/8/9 family’s bias current at
25°C (1 pA, typ.).

The easiest way to reduce surface leakage is to use a
guard ring around sensitive pins (or traces). The guard
ring is biased at the same voltage as the sensitive pin.
An example of this type of layout is shown in

Figure 4-7.

12

Ω. A 5V difference

VOH can be calculated using the equation below:

EQUATION 4-4:

As explained in Section 4.1 “Comparator Inputs”, it
is important to keep the non-inverting input below

+0.3V when VPU > VDD.

V

DD

4.5 Supply Bypass

With this family of comparators, the power supply pin

for single supply) should have a local bypass

(V

DD

capacitor (i.e., 0.01 µF to 0.1 µF) within 2 mm for good
edge rate performance.

DS21714F-page 16 © 2007 Microchip Technology Inc.

FIGURE 4-7: Example Guard Ring Layout
for Inverting Circuit.

1. Inverting Configuration (Figures 4-4 and 4-7):

a. Connect the guard ring to the non-inverting

input pin (V
to the same reference voltage as the
comparator (e.g., V

b. Connect the inverting pin (V

pad without touching the guard ring.

+). This biases the guard ring

IN

/2 or ground).

DD

–) to the input

IN

MCP6546/6R/6U/7/8/9

¼ MCP6549

V

DD

–

+

V

REF

V

DD

V

DD

R

1

R

2

V

OUT

V

IN

V

REF

V

PU

R

PU

MCP6546

MCP6041

V

RT

1/2

V

RB

V

IN

V

PU

R

PU

V

OUT

MCP6547

1/2
MCP6547

4.9 Unused Comparators

An unused amplifier in a quad package (MCP6549)
should be configured as shown in Figure 4-8. This
circuit prevents the output from toggling and causing
crosstalk. It uses the minimum number of components
and draws minimal current (see Figure 2-15 and

Figure 2-18).

FIGURE 4-8: Unused Comparators.

4.10 Typical Applications

4.10.1 PRECISE COMPARATOR

Some applications require higher DC precision. An
easy way to solve this problem is to use an amplifier
(such as the MCP6041) to gain-up the input signal
before it reaches the comparator. Figure 4-9 shows an
example of this approach.

FIGURE 4-9: Precise Inverting
Comparator.

4.10.2 WINDOWED COMPARATOR

Figure 4-10 shows one approach to designing a

windowed comparator. The wired-OR connection
produces a high output (logic 1) when the input voltage
is between V

and VRT (where VRT > VRB).

RB

FIGURE 4-10: Windowed Comparator.

© 2007 Microchip Technology Inc. DS21714F-page 17

MCP6546/6R/6U/7/8/9

XXXXXXXX
XXXXXNNN

YYWW

8-Lead PDIP (300 mil)

Example:

8-Lead SOIC (150 mil)

Example:

XXXXXXXX
XXXXYYWW

NNN

MCP6546

I/P256

0729

MCP6546

I/SN0729

256

8-Lead MSOP

Example:

XXXXXX

YWWNNN

6546I

729256

Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
* This package is Pb-free. The Pb-free JEDEC designator ( )

can be found on the outer packaging for this package.

Note: In the event the full Microchip part number cannot be marked on one line, it will

be carried over to the next line, thus limiting the number of available
characters for customer-specific information.

3

e

5-Lead SOT-23 (MCP6546, MCP6546R, MCP6546U)

Example: (I-temp)

XXNN AC25

5-Lead SC-70 (MCP6546)

Example: (I-temp)

XXNN (Front)
YWW (Back)

AC25(Front)
729 (Back)

Device

I-Temp

Code

E-Temp

Code

MCP6546 ACNN GWNN

MCP6546R AHNN GXNN

MCP6546U — AWNN

Note: Applies to 5-Lead SOT-23

Device

I-Temp

Code

E-Temp

Code

MCP6546 ACNN Note 2

Note 1: I-Temp parts prior to March

2005 are marked “ACN”

2: SC-70-5 E-Temp parts not

available at this release of
the data sheet.

MCP6546

I/P^^256

0729

MCP6546I
SN^^0729

256

3

e

OR

OR

Example: (I-temp)

AC25

OR

5.0 PACKAGING INFORMATION

5.1 Package Marking Information

3

e

DS21714F-page 18 © 2007 Microchip Technology Inc.

3

e

Package Marking Information (Continued)

14-Lead PDIP (300 mil) (MCP6549) Example:

14-Lead TSSOP (MCP6549)

Example:

14-Lead SOIC (150 mil) (MCP6549)

Example:

XXXXXXXXXXXXXX
XXXXXXXXXXXXXX

YYWWNNN

XXXXXXXXXX

YYWWNNN

XXXXXXXX

YYWW

NNN

MCP6549-I/P

0729256

MCP6549I

0729

256

XXXXXXXXXX

MCP6549ISL

0729256

XXXXXXXXXX

MCP6549-E/P

0729256

OR

MCP6549

0729256

E/SL^^

OR

3

e

MCP6549

I/P^^

0729256

OR

MCP6546/6R/6U/7/8/9

3

e

3

e

© 2007 Microchip Technology Inc. DS21714F-page 19

MCP6546/6R/6U/7/8/9

5-Lead Plastic Small Outline Transistor (LT) [SC70]

Notes:

1. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.127 mm per side.

2. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Units MILLIMETERS

Dimension Limits MIN NOM MAX
Number of Pins N 5
Pitch e 0.65 BSC
Overall Height A 0.80 – 1.10
Molded Package Thickness A2 0.80 – 1.00
Standoff A1 0.00 – 0.10
Overall Width E 1.80 2.10 2.40
Molded Package Width E1 1.15 1.25 1.35
Overall Length D 1.80 2.00 2.25
Foot Length L 0.10 0.20 0.46
Lead Thickness c 0.08 – 0.26
Lead Width b 0.15 – 0.40

D

b

1

23

E1

E

4

5

ee

c

L

A1

AA2

Microchip Technology Drawing C04-061B

DS21714F-page 20 © 2007 Microchip Technology Inc.

MCP6546/6R/6U/7/8/9

5-Lead Plastic Small Outline Transistor (OT) [SOT-23]

Notes:

1. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.127 mm per side.

2. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Units MILLIMETERS

Dimension Limits MIN NOM MAX
Number of Pins N 5
Lead Pitch e 0.95 BSC
Outside Lead Pitch e1 1.90 BSC
Overall Height A 0.90 – 1.45
Molded Package Thickness A2 0.89 – 1.30
Standoff A1 0.00 – 0.15
Overall Width E 2.20 – 3.20
Molded Package Width E1 1.30 – 1.80
Overall Length D 2.70 – 3.10
Foot Length L 0.10 – 0.60
Footprint L1 0.35 – 0.80
Foot Angle φ 0° – 30°
Lead Thickness c 0.08 – 0.26
Lead Width b 0.20 – 0.51

φ

N

b

E

E1

D

1

2

3

e

e1

A

A1

A2

c

L

L1

Microchip Technology Drawing C04-091B

© 2007 Microchip Technology Inc. DS21714F-page 21

MCP6546/6R/6U/7/8/9

8-Lead Plastic Dual In-Line (P) – 300 mil Body [PDIP]

Notes:

1. Pin 1 visual index feature may vary, but must be located with the hatched area.

2. § Significant Characteristic.

3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side.

4. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Units INCHES

Dimension Limits MIN NOM MAX
Number of Pins N 8
Pitch e .100 BSC
Top to Seating Plane A – – .210
Molded Package Thickness A2 .115 .130 .195
Base to Seating Plane A1 .015 – –
Shoulder to Shoulder Width E .290 .310 .325
Molded Package Width E1 .240 .250 .280
Overall Length D .348 .365 .400
Tip to Seating Plane L .115 .130 .150
Lead Thickness c .008 .010 .015
Upper Lead Width b1 .040 .060 .070
Lower Lead Width b .014 .018 .022
Overall Row Spacing § eB – – .430

N

E1

NOTE 1

D

12

3

A

A1

A2

L

b1

b

e

E

eB

c

Microchip Technology Dra wing C04-018B

DS21714F-page 22 © 2007 Microchip Technology Inc.

MCP6546/6R/6U/7/8/9

8-Lead Plastic Small Outline (SN) – Narrow, 3.90 mm Body [SOIC]

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.

2. § Significant Characteristic.

3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.

4. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimension, usually without tolerance, for information purposes only.

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Units MILLIMETERS

Dimension Limits MIN NOM MAX
Number of Pins N 8
Pitch e 1.27 BSC
Overall Height A – – 1.75
Molded Package Thickness A2 1.25 – –
Standoff

§ A1 0.10 – 0.25

Overall Width E 6.00 BSC
Molded Package Width E1 3.90 BSC
Overall Length D 4.90 BSC
Chamfer (optional) h 0.25 – 0.50
Foot Length L 0.40 – 1.27
Footprint L1 1.04 REF
Foot Angle φ 0° – 8°
Lead Thickness c 0.17 – 0.25
Lead Width b 0.31 – 0.51
Mold Draft Angle Top α 5° – 15°
Mold Draft Angle Bottom β 5° – 15°

D

N

e

E

E1

NOTE 1

12 3

b

A

A1

A2

L

L1

c

h

h

φ

β

α

Microchip Technology Drawing C04-057B

© 2007 Microchip Technology Inc. DS21714F-page 23

MCP6546/6R/6U/7/8/9

8-Lead Plastic Micro Small Outline Package (MS) [MSOP]

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.

2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.

3. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Units MILLIMETERS

Dimension Limits MIN NOM MAX
Number of Pins N 8
Pitch e 0.65 BSC
Overall Height A – – 1.10
Molded Package Thickness A2 0.75 0.85 0.95
Standoff A1 0.00 – 0.15
Overall Width E 4.90 BSC
Molded Package Width E1 3.00 BSC
Overall Length D 3.00 BSC
Foot Length L 0.40 0.60 0.80
Footprint L1 0.95 REF
Foot Angle φ 0° – 8°
Lead Thickness c 0.08 – 0.23
Lead Width b 0.22 – 0.40

D

N

E

E1

NOTE 1

1

2

e

b

A

A1

A2

c

L1

L

φ

Microchip Technology Drawing C04-111B

DS21714F-page 24 © 2007 Microchip Technology Inc.

MCP6546/6R/6U/7/8/9

14-Lead Plastic Dual In-Line (P) – 300 mil Body [PDIP]

Notes:

1. Pin 1 visual index feature may vary, but must be located with the hatched area.

2. § Significant Characteristic.

3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side.

4. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Units INCHES

Dimension Limits MIN NOM MAX
Number of Pins N 14
Pitch e .100 BSC
Top to Seating Plane A – – .210
Molded Package Thickness A2 .115 .130 .195
Base to Seating Plane A1 .015 – –
Shoulder to Shoulder Width E .290 .310 .325
Molded Package Width E1 .240 .250 .280
Overall Length D .735 .750 .775
Tip to Seating Plane L .115 .130 .150
Lead Thickness c .008 .010 .015
Upper Lead Width b1 .045 .060 .070
Lower Lead Width b .014 .018 .022
Overall Row Spacing § eB – – .430

N

E1

D

NOTE 1

12

3

E

c

eB

A2

L

A

A1

b1

b e

Microchip Technology Drawing C04-005B

© 2007 Microchip Technology Inc. DS21714F-page 25

MCP6546/6R/6U/7/8/9

14-Lead Plastic Small Outline (SL) – Narrow, 3.90 mm Body [SOIC]

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.

2. § Significant Characteristic.

3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.

4. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimension, usually without tolerance, for information purposes only.

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Units MILLIMETERS

Dimension Limits MIN NOM MAX
Number of Pins N 14
Pitch e 1.27 BSC
Overall Height A – – 1.75
Molded Package Thickness A2 1.25 – –
Standoff § A1 0.10 – 0.25
Overall Width E 6.00 BSC
Molded Package Width E1 3.90 BSC
Overall Length D 8.65 BSC
Chamfer (optional) h 0.25 – 0.50
Foot Length L 0.40 – 1.27
Footprint L1 1.04 REF
Foot Angle φ 0° – 8°
Lead Thickness c 0.17 – 0.25
Lead Width b 0.31 – 0.51
Mold Draft Angle Top α 5° – 15°
Mold Draft Angle Bottom β 5° – 15°

NOTE 1

N

D

E

E1

1

2 3

b

e

A

A1

A2

L

L1

c

h

h

α

β

φ

Microchip Technology Drawing C04-065B

DS21714F-page 26 © 2007 Microchip Technology Inc.

MCP6546/6R/6U/7/8/9

14-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm Body [TSSOP]

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.

2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.

3. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimension, usually without tolerance, for information purposes only.

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Units MILLIMETERS

Dimension Limits MIN NOM MAX
Number of Pins N 14
Pitch e 0.65 BSC
Overall Height A – – 1.20
Molded Package Thickness A2 0.80 1.00 1.05
Standoff A1 0.05 – 0.15
Overall Width E 6.40 BSC
Molded Package Width E1 4.30 4.40 4.50
Molded Package Length D 4.90 5.00 5.10
Foot Length L 0.45 0.60 0.75
Footprint L1 1.00 REF
Foot Angle φ 0° – 8°
Lead Thickness c 0.09 – 0.20
Lead Width b 0.19 – 0.30

NOTE 1

D

N

E

E1

1

2

e

b

c

A

A1

A2

L1

L

φ

Microchip Technology Drawing C04-087B

© 2007 Microchip Technology Inc. DS21714F-page 27

MCP6546/6R/6U/7/8/9

NOTES:

DS21714F-page 28 © 2007 Microchip Technology Inc.

APPENDIX A: REVISION HISTORY

Revision F (September 2007)

The following is the list of modifications:

1. Corrected polarity of MCP6546U SOT-23-5 pin
out diagram on front page.

2. Section 5.1 “Package Marking Information”:
Updated package outline drawings per marcom.

Revision E (September 2006)

The following is the list of modifications:

1. Added MCP6546U pinout for the SOT-23-5
package.

2. Clarified Absolute Maximum Analog Input
Voltage and Current Specifications.

3. Added applications writeups on unused
comparators.

4. Added disclaimer to package outline drawings.

Revision D (May 2006)

MCP6546/6R/6U/7/8/9

The following is the list of modifications:

1. Added E-temp parts.

2. Changed minimum pull-up voltage specification

) to 1.6V for parts starting Dec. 2004 (week

(V

PU

code 52); previous parts are specified at a
minimum of V

3. Changed V
linear and quadratic temperature coefficients.

4. Changed specifications and plots to include E­Temp parts.

5. Added Section 3.0 “Pin Descriptions”.

6. Corrected package markings (Section 5.1
“Package Marking Information”).

7. Added Appendix A: “Revision History”.

.

DD

temperature specifications to

HYST

Revision C (May 2003)

Revision B (December 2002)

Revision A (February 2002)

• Original Release of this Document.

© 2007 Microchip Technology Inc. DS21714F-page 29

MCP6546/6R/6U/7/8/9

NOTES:

DS21714F-page 30 © 2007 Microchip Technology Inc.

MCP6546/6R/6U/7/8/9

Device: MCP6546: Single Comparator

MCP6546T: Single Comparator (Tape and Reel)

(SC-70, SOT-23, SOIC, MSOP)

MCP6546RT: Single Comparator (Rotated - Tape and

Reel) (SOT-23 only)

MCP6546UT: Single Comparator (Tape and Reel)

(SOT-23-5 is E-Temp only)

MCP6547: Dual Comparator
MCP6547T: Dual Comparator

(Tape and Reel for SOIC and MSOP)
MCP6548: Single Comparator with CS
MCP6548T: Single Comparator with CS

(Tape and Reel for SOIC and MSOP)
MCP6549: Quad Comparator
MCP6549T: Quad Comparator

(Tape and Reel for SOIC and TSSOP)

Temperature Range: I = -40°C to +85°C

E * = -40°C to +125°C

* SC-70-5 E-Temp parts not available at this release of the
data sheet.

Package: LT = Plastic Package (SC-70), 5-lead

OT = Plastic Small Outline Transistor (SOT-23), 5-lead
MS = Plastic MSOP, 8-lead
P = Plastic DIP (300 mil Body), 8-lead, 14-lead
SN = Plastic SOIC (150 mil Body), 8-lead
SL = Plastic SOIC (150 mil Body), 14-lead (MCP6549)
ST = Plastic TSSOP (4.4mm Body), 14-lead (MCP6549)

PART NO. –X /XX

PackageTemperature

Range

Device

Examples:

a) MCP6546T-I/LT: Tape and Reel,

Industrial Temperature,
5LD SC-70.

b) MCP6546T-I/OT: Tape and Reel,

Industrial Temperature,
5LD SOT-23.

c) MCP6546-E/P: Extended Temperature,

8LD PDIP.

d) MCP6546RT-I/OT: Tape and Reel,

Industrial Temperature,
5LD SOT23.

e) MCP6546-E/SN: Extended Temperature,

8LD SOIC.

f) MCP6546UT-E/OT:Tape and Reel,

Extended Temperature,
5LD SOT23.

a) MCP6547-I/MS: Industrial Temperature,

8LD MSOP.

b) MCP6547T-I/MS: Tape and Reel,

Industrial Temperature,
8LD MSOP.

c) MCP6547-I/P: Industrial Temperature,

8LD PDIP.

d) MCP6547-E/SN: Extended Temperature,

8LD SOIC.

a) MCP6548-I/SN: Industrial Temperature,

8LD SOIC.

b) MCP6548T-I/SN: Tape and Reel,

Industrial Temperature,
8LD SOIC.

c) MCP6548-I/P: Industrial Temperature,

8LD PDIP.

d) MCP6548-E/SN: Extended Temperature,

8LD SOIC.

a) MCP6549T-I/SL: Tape and Reel,

Industrial Temperature,
14LD SOIC.

b) MCP6549T-E/SL: Tape and Reel,

Extended Temperature,
14LD SOIC.

c) MCP6549-I/P: Industrial Temperature,

14LD PDIP.

d) MCP6549-E/ST: Extended Temperature,

14LD TSSOP.

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

© 2007 Microchip Technology Inc. DS21714F-page 31

NOTES:

MCP6546/6R/6U/7/8/9

© 2007 Microchip Technology Inc. DS21714F-page 32

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, K

EELOQ, KEELOQ logo, microID, MPLAB, PIC,

PICmicro, PICSTART, PRO MATE, rfPIC and SmartShunt are
registered trademarks of Microchip Technology Incorporated
in the U.S.A. and other countries.

AmpLab, FilterLab, Linear Active Thermistor, Migratable
Memory, MXDEV, MXLAB, SEEVAL, SmartSensor and The
Embedded Control Solutions Company are registered
trademarks of Microchip Technology Incorporated in the
U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,
In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi,
MPASM, MPLAB Certified logo, MPLIB, MPLINK, PICkit,
PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal,
PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select
Mode, Smart Serial, SmartTel, Total Endurance, UNI/O,
WiperLock and ZENA are trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.

All other trademarks mentioned herein are property of their
respective companies.

© 2007, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.

Printed on recycled paper.

Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.

®

MCUs and dsPIC® DSCs, KEELOQ

®

code hopping

© 2007 Microchip Technology Inc. DS21714F-page 33

WORLDWIDE SALES AND SERVICE

AMERICAS

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06/25/07

DS21714F-page 34 © 2007 Microchip Technology Inc.