Datasheet MCP4706, MCP4716, MCP4726 Datasheet
MCP4706/4716/4726
8-/10-/12-Bit Voltage Output Digital-to-Analog Converter
with EEPROM and I2C Interface
Features
• Output V oltage Resolutions
- 12-bit: MCP4726
- 10-bit: MCP4716
-8-bit: MCP4706
• Rail-to-Rail Output
• Fast Settling Time of 6 µs (typical)
• DAC Voltage Reference Options
-V
DD
-V
Pin
REF
• Output Gain Opt io n s
- Unity (1x)
- 2x, only when V
pin is used as voltage
REF
source
• Nonvolatile Memory (EEPROM)
- Auto Recall of Saved DAC register setting
- Auto Recall of Saved Device Configu ration
(Volt a ge R efer enc e, Gain, Pow er Down)
• Power-Down Modes
- Disconnects output buf fer
- Selection of V
pull-down resistors
OUT
(640 kΩ, 125 kΩ, or 1 kΩ)
• Low Power Consumption
- Normal Operation: 210µA typ.
- Power Down Operation: 60 nA typ.
(PD1:PD0 = “11”)
• Single-Supply Operation: 2.7V to 5.5V
2
•I
C™ Interface:
- Eight Available Addresses
- Standard (100 kbps), Fast (400 kbps), and
High-S pe ed (3.4Mbps ) Modes
• Small 6-lead SOT-23 and DFN (2x2) Packages
• Extended Temperature Range: -40°C to +125°C
Applications
• Set Point or Offset Trimming
• Sensor Calibration
• Low Power Portable Instrumentation
• PC Peripherals
• Data AcquisitionSystems
• Motor Control
Package Types
MCP4706 / 16 / 26
V
1
OUT
2
V
SS
V
3
DD
SOT-23-6
* Includes Exposed Thermal Pad (EP); see Table 3-1.
6
5
4
V
REF
SCL
SDA
V
REF
SCL
SDA
1
EP
2
7
3
2x2 DFN-6*
6
V
OUT
5
V
SS
4
V
DD
Description
The MCP4706/4716/4726 are single channel 8-bit,
10-bit, and 12-bit buffered voltage output Digital-toAnalog Converters (DAC) with nonvo latile m emory and
2
C Serial Interface. This family will a lso be re ferre d
an I
to as MCP47X6.
The V
DAC’s referenc e voltage. Wh en V
connected internally to the DAC reference circuit.
When the V
output buffer’s gain to 1 or 2. When the gain is 2, the
V
REF
V
DD
The DAC Register value and configuration bits can be
programmed to nonvolatile memory (EEPROM). The
nonvolatile memory holds the DAC Register and
configuration bi t values wh en the devi ce is pow ered of f.
A device reset (such as a Power On Reset) latches
these stored values into the volatile memory.
Power-down modes enable system current reduction
when the DAC output voltage i s not require d. The V
pin can be configure d to present a low , medi um, or high
resistance load.
These devices h ave a two-wire I
interface for standa rd (100 kHz), fast (400 kHz), or high
speed (3.4 MHz) mode.
These devices a re avai lable i n sma ll 6-pi n SOT-23 and
DFN 2x2 mm packages.
pin or the device VDD can be selected as th e
REF
pin is used, the user can select the
REF
is selected, VDD is
DD
pin voltage should be limited to a maximum of
/2.
2
C™ compatible serial
OUT
© 2011 Microchip Technology Inc. DS22272A-page 1
MCP4706/4716/4726
Block Diagram
V
REF
V
DD
V
SS
SDA
SCL
C Interface Logic
2
I
V
DD
Buffer
DAC
Register
EEPROM
Control
Logic
V
REF1:VREF0
Reference
Selection
Resistor Ladder
V
RL
PD1:PD0
V
W
Gain (1x or 2x)
(G = 0 or 1)
Op
Amp
PD1:PD0
V
OUT
1kΩ
640 kΩ
125 kΩ
DS22272A-page 2 © 2011 Microchip Technology Inc.
MCP4706/4716/4726
1.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings †
Voltage on VDD with respect to VSS................ -0.6V to +6.5V
Voltage on all pins with respect to V
................................................................................
Input clamp current, I
....................................................................................±20 mA
Output clamp current, I
....................................................................................±20 mA
Maximum input current source/sunk by SDA, SCL pins
........................................................................................2 mA
Maximum output current sunk by SDA Output pin
......................................................................................25 mA
Maximum current out of V
Maximum current into V
Maximum current sourced by the V
Maximum current sunk by the V
Maximum current sunk by the V
Package power dissipation (T
SOT-23-6 .......................................................452 mW
DFN-6 ..........................................................1098 mW
Storage temperature.....................................-65°C to +150°C
Ambient temperature with power applied
......................................................................-55°C to +125°C
ESD protection on all pins ....................................≥ 6kV (HBM)
....................................................................................≥ 400V (MM)
Maximum Junction Temperature (T
(VI < 0, VI > VDD, VI)
IK
(VO < 0 or VO > VDD)
OK
pin...................................50 mA
SS
pin......................................50 mA
DD
SS
-0.3V to VDD + 0.3V
pin ..................40 mA
OUT
pin........................40 mA
OUT
pin.........................40 µA
REF
= +50°C, TJ = +150°C)
A
) ......................... +150°C
J
† Notice: Stresses above those listed under “Maximum
Ratings” may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at
those or any other conditions above those indicated in the
operational listings of this specification is not implied.
Exposure to maximum rating condit ions f or ext ended periods
may affect device reliability.
© 2011 Microchip Technology Inc. DS22272A-page 3
MCP4706/4716/4726
ELECTRICAL CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, VDD = 2.7V to 5.5V, VSS = 0V , RL = 5 kΩ from V
= -40°C to +125°C. Typical values at +25°C.
Parameters Symbol Min Typical Max Units Conditions
Power Requirements
Input Voltage V
Input Current I
DD
DD
2.7 — 5.5 V
— 210 400 µA V
REF1:VREF0
SCL = SDA = V
volatile DAC Register = 0x000
— 210 400 µA V
REF1:VREF0
SCL = SDA = V
volatile DAC Register = 0x000
Power-Down Current I
Power-On Reset
V
DDP
POR
— 0.09 2 µA PD1:PD0 = ‘01’ (Note 6),
not connected
V
OUT
— 2.2 — V RAM retent ion voltage, (V
Threshold
Power-Up Ramp Rate V
Note 1: This parameter is ensured by design and is not 100% tested.
2: This gain error does not include offset error. See Section 2 for more details in plots.
3: Within 1/2 LSb of final value when code changes from 1/4 to 3/4 of FSR. (Example: 400h to C00h in 12- bit device).
4: The power-up ramp rate affects on uploading the EEPROM contents to the DAC register. It measures the rise of V
over time.
5: This parameter is ensured by characterization, and not 100% tested.
6: The PD1:PD0 = ‘10’, and ‘11’ configurations should have the same current.
7: V
= 5.5V.
DD
RAMP
1——V/S(Note 1, Note 4)
to GND, CL = 100 pF , TA
OUT
= ‘00’,
, V
SS
= ‘11’, V
, V
SS
is unloaded,
OUT
= VDD,
REF
is unloaded,
OUT
RAM
) < V
POR
DD
DS22272A-page 4 © 2011 Microchip Technology Inc.
MCP4706/4716/4726
ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise indicated, VDD = 2.7V to 5.5V, VSS = 0V , RL = 5 kΩ from V
= -40°C to +125°C. Typical values at +25°C.
Parameters Symbol Min Typical Max Units Conditions
DC Accuracy
Offset Error V
Offset Error Tempera-
V
ture
OS
/°C — ±1 — ppm/°C -40°C to +25°C
OS
— ±2 — ppm/°C +25°C to +85°C
±0.02 0 .75 % of FSR Code = 0x000h
V
REF1:VREF0
Coefficient
Zero Scale Error EZS — 0.13 2.0 LSb MCP4706, Code = 0x00h
— 0.52 7.7 LSb MCP4716, Co de = 0x000h
— 2.05 30.8 LSb MCP4726, Code = 0x000h
Full Scale Error E
— 0.3 5.2 LSb MCP4706, Code = 0xFFh
FS
— 1.1 20.5 LSb MCP4716, Code = 0x3FFh
— 4.1 82.0 LSb MCP4726, Code = 0xFFFh
Gain Error
(Note 2)
g
E
-2 -0.10 2 % of FSR MCP4706, Code = 0xFFh
V
REF1:VREF0
-2 -0.10 2 % of FSR MCP4716, Code = 0x3FFh
V
REF1:VREF0
-2 -0.10 2 % of FSR MCP4726, Code = 0xFFFh
V
REF1:VREF0
Gain Error Drift ΔG/°C — -3 — ppm/°C
Resolution n 8 bits MCP4706
10 bits MCP4716
12 bits MCP4726
INL Error
(Note 7)
INL -0.907 ±0.125 +0.907 LSb MCP4706 (codes: 6 to 250)
-3.625 ±0.5 +3.625 LSb MCP4716 (codes: 25 to 1000)
-14.5 ±2 +14.5 LSb MCP4726 (codes: 100 to 4000)
DNL Error
(Note 7)
DNL -0.05 ±0.0125 +0.05 LSb MCP4706 (codes: 6 to 250)
-0.188 ±0.05 +0.188 LSb MCP4716 (codes: 25 to 1000)
-0.75 ±0.2 +0.75 LSb MCP4726 (codes: 100 to 4000)
Note 1: This parameter is ensured by design and is not 100% tested.
2: This gain error does not include offset error. See Section 2 for more details in plots.
3: Within 1/2 LSb of final value when code changes from 1/4 to 3/4 of FSR. (Example: 400h to C00h in 12- bit device).
4: The power-up ramp rate affects on uploading the EEPROM contents to the DAC register. It measures the rise of V
over time.
5: This parameter is ensured by characterization, and not 100% tested.
6: The PD1:PD0 = ‘10’, and ‘11’ configurations should have the same current.
7: V
= 5.5V.
DD
to GND, CL = 100 pF , TA
OUT
= ‘00’, G = ‘0’
= ‘00’, G = ‘0’
= ‘00’, G = ‘0’
= ‘00’, G = ‘0’
DD
© 2011 Microchip Technology Inc. DS22272A-page 5
MCP4706/4716/4726
ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise indicated, VDD = 2.7V to 5.5V, VSS = 0V , RL = 5 kΩ from V
= -40°C to +125°C. Typical values at +25°C.
Parameters Symbol Min Typical Max Units Conditions
Output Amplifier
Minimum Output Volt-
V
OUT(MIN)
— 0.01 — V Output Amplifier’s minimum drive
age
Maximum Output
Voltage
Phase Margin PM — 66 — Degree
V
OUT(MAX)
—VDD –
0.04
— V Output Amplifier’s maximum drive
= 400 pF, R
C
L
(°)
Slew Rate SR — 0.55 — V/µs
Short Circuit Current I
Settling Time t
SETTLING
Power Down Output
Disable Time Delay
T
SC
PDD
71524mA
—6—µsNote 3
— 1 — µs PD1:PD0 = “00” -> ‘11’, ‘10’, or ‘01’
started from falling edge SCL at end of
ACK bit.
= V
V
OUT
OUT
connected.
Power Down Output
Enable Time Delay
— 10.5 — µs PD1:PD0 = ‘11’, ‘10’, or ‘01’ -> “00”
T
PDE
started from falling edge SCL at end of
ACK bit.
Volatile DAC Register = FFh,
=10mV. V
V
OUT
External Reference (V
Input Range V
) (Note 1)
REF
0.04 — VDD -
REF
V Buffered Mode
0.04
V Unbuffered Mode
Input Impedance R
0—V
— 210 — kΩ Unbuffered Mode
VREF
DD
Input Capacitance C_REF — 29 — pF Unbuffered Mode
-3 dB Bandwidth — 86.5 — kHz V
—67.7— kHzV
Total Harmonic Distor-
THD — -73 — dB V
tion
= 2.048V ± 0.1V,
REF
V
REF1:VREF0
= 2.048V ± 0.1V,
REF
V
REF1:VREF0
= 2.048V ± 0.1V,
REF
V
REF1:VREF0
Frequency = 1 kHz
Dynamic Performance (Note 1)
Major Code Transition
Glitch
— 45 — nV-s 1 LSb change around major carry
(800h to 7FFh)
Digital Feedthrough — <10 — nV-s
Note 1: This parameter is ensured by design and is not 100% tested.
2: This gain error does not include offset error. See Section 2 for more details in plots.
3: Within 1/2 LSb of final value when code changes from 1/4 to 3/4 of FSR. (Example: 400h to C00h in 12- bit device).
4: The power-up ramp rate affects on uploading the EEPROM contents to the DAC register. It measures the rise of V
over time.
5: This parameter is ensured by characterization, and not 100% tested.
6: The PD1:PD0 = ‘10’, and ‘11’ configurations should have the same current.
7: V
= 5.5V.
DD
to GND, CL = 100 pF , TA
OUT
= ∞
L
- 10 mV. V
OUT
=‘10’, G = ‘0’
=‘10’, G = ‘1’
=‘10’, G = ‘0’,
not
OUT
not connected.
DD
DS22272A-page 6 © 2011 Microchip Technology Inc.
MCP4706/4716/4726
ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise indicated, VDD = 2.7V to 5.5V, VSS = 0V , RL = 5 kΩ from V
= -40°C to +125°C. Typical values at +25°C.
Parameters Symbol Min Typical Max Units Conditions
Digital Interface
Output Low V oltage VOL ——0.4 V IOL = 3 mA
Input High Voltage
VIH 0.7V
—— V
DD
(SDA and SCL Pins)
Input Low Voltage
V
— —0.3VDDV
IL
(SDA and SCL Pins)
Input Leakage I
— — ±1 µA SCL = SDA = V
LI
SCL = SDA = V
Pin Capacitance C
—— 3 pF (Note 5)
PIN
EEPROM
EEPROM Write Time T
WRITE
—2550ms
Data Retention — 200 — Years At +25°C, (Note 1)
Endurance 1 — — Million
At +25°C, (Note 1)
Cycles
Note 1: This parameter is ensured by design and is not 100% tested.
2: This gain error does not include offset error. See Section 2 for more details in plots.
3: Within 1/2 LSb of final value when code changes from 1/4 to 3/4 of FSR. (Example: 400h to C00h in 12- bit device).
4: The power-up ramp rate affects on uploading the EEPROM contents to the DAC register. It measures the rise of V
over time.
5: This parameter is ensured by characterization, and not 100% tested.
6: The PD1:PD0 = ‘10’, and ‘11’ configurations should have the same current.
7: V
= 5.5V.
DD
to GND, CL = 100 pF , TA
OUT
or
SS
DD
DD
© 2011 Microchip Technology Inc. DS22272A-page 7
MCP4706/4716/4726
1.1 I2C Mode Timing Waveforms and Requirements
VDD
t
PORD
V
POR
t
BORD
(V
BOR
)
SCL
SDA
V
OUT
V
IH
2
I
C Interface is operational
FIGURE 1-1: Power-On and Brown-Out Reset Waveforms.
ACK Stop Start ACK
SDA
SCL
t
t
PDE
V
OUT
FIGURE 1-2: I2C Power-Down Command Timing.
V
pulled down by internal
OUT
500 kΩ (typical) resistor
PDD
V
IH
TABLE 1-1: RESET TIMING
Standard Operating Conditions (unless otherwise specified)
Timing Characteristics
Operating Temperature –40°C ≤ T
All parameters apply across the specified operating ranges unless noted.
= +2.7V to 5.5V, 5 kΩ, 10 kΩ, 50 kΩ, 100kΩ devices.
V
DD
Typical specifications represent values for V
≤ +125°C (extended)
A
= 5.5V, TA = +25°C.
DD
Parameters Sym Min Typ Max Units Conditions
Power Up Reset
Delay
Brown Out Reset
Delay
Power Down Disable
Time Delay
t
— 60 — µs Monitor ACK bit response to ensure device
PORD
responds to command.
—1—µsVDD transitions from V
t
BORD
—2.5— µsVDD = 5V
T
PDD
V
OUT
driven to V
PD1:PD0 → ‘00’ (from ‘01’, ‘10’, or ‘11’),
from falling edge SCL at end of ACK bit.
—5—µsV
DD
= 3V
PD1:PD0 → ‘00’ (from ‘01’, ‘10’, or ‘11’),
from falling edge SCL at end of ACK bit.
Power Down Enable
Time Delay
— 10.5 — µs PD1:PD0 → ‘01’, ‘10’, or ‘11’ (from ‘00’),
T
PDE
from falling edge SCL at end of ACK bit.
OUT
DD(MIN)
disabled
→ > V
POR
DS22272A-page 8 © 2011 Microchip Technology Inc.
MCP4706/4716/4726
VIH
SCL
91
90
SDA
VIL
START
Condition
FIGURE 1-3: I2C Bus Start/Stop Bits Timing Waveforms.
TABLE 1-2: I
I2C AC Characteristics
Param.
No.
D102 C
Symbol Characteristic Min Max Units Conditions
90 T
91 T
92 T
93 T
94 T
95 T
2
C BUS START/STOP BITS REQUIREMENTS
Standard Operating Conditions (unless otherwise specified)
Operating Temperature –40°C ≤ T
Operating Voltage V
SCL pin Frequency Standard Mode 0 100 kHz Cb = 400 pF, 2.7V - 5.5V
F
SCL
DD range is described in Electrical characteristics
Fast Mode 0 400 kHz Cb = 400 pF, 2.7V - 5.5V
High-S pe ed 1.7 0 1.7 MHz C
High-S pe ed 3.4 0 3.4 MHz Cb = 100 pF, 4.5V - 5.5V
Bus capaciti v e
b
loading
100 kHz mode — 400 pF
400 kH z mode — 400 pF
1.7 MHz mode — 400 pF
3.4 MHz mode — 100 pF
SU:STA START condition 100 kHz mode 4700 — ns Only relevant for repeated
Setup time 400 kHz mode 600 — ns
1.7 MHz mode 160 — ns
3.4 MHz mode 160 — ns
HD:STA START condition 100 kHz mode 4000 — ns After this period the first
Hold time 400 kHz mode 600 — ns
1.7 MHz mode 160 — ns
3.4 MHz mode 160 — ns
SU:STO STOP condition 100 kHz mode 4000 — ns
Setup time 400 kHz mode 600 — ns
1.7 MHz mode 160 — ns
3.4 MHz mode 160 — ns
HD:STO STOP condition 100 kHz mode 4000 — ns
Hold time 400 kHz mode 600 — ns
1.7 MHz mode 160 — ns
3.4 MHz mode 160 — ns
HVC to SCL Setup time 25 — uS High Voltage Commands
HVCSU
SCL to HVC Hold time 25 — uS High Voltage Commands
HVCHD
93
92
111
STOP
Condition
A ≤ +125°C (Extended)
= 400 pF, 4.5V - 5.5V
b
START condition
clock pulse is generated
© 2011 Microchip Technology Inc. DS22272A-page 9
MCP4706/4716/4726
103
100
101
SCL
90
91 92
106
107
SDA
In
109
SDA
Out
109
FIGURE 1-4: I2C Bus Data Timing.
TABLE 1-3: I2C BUS DATA REQUIREMENTS (SLAVE MODE)
I2C AC Characteristics
Param.
Sym Characteristic Min Max Units Conditions
No.
100 T
101 T
HIGH
LOW Clock low time 100 kHz mode 4700 — ns 2.7V-5.5V
Clock high time 100 k Hz mode 4000 — ns 2.7V-5.5V
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid uninten ded gene ration of START or STOP conditions.
2: A fast-mode (400 kHz) I
requirement t
≥ 250 ns must then be met. This will automatically be the case if the device does not
SU;DAT
stretch the LOW period of the SCL signal . If suc h a de vic e do es stretc h the LO W peri od of the SCL sig nal ,
it must output the next data bit to the SDA line.
max.+t
T
R
= 1000 + 250 = 1250 ns (according to the standard-mode I2C bus specification) before
SU;DAT
the SCL line is released.
3: The MCP47X6 device must provide a data hold time to bridge the undefined part between V
the falling edge of the SCL s ignal. This specificati on is not a p art of the I
in order to ensure that the output data will meet the setup and hold specifications for the receiving device.
4: Use C
in pF for the calculations.
b
5: Not Tested. This parameter ensured by characterization.
6: A Master Transmitter must provide a delay to ensure that difference between SDA and SCL fall times do
not unintentionally create a Start or Stop condition.
If this parameter is too short, it can create an unintentional Start or Stop condition to other devices on the
2
I
C bus line. If this parameter is too long, the Data Input Setup (T
affected.
Data Input: This parameter must be longer than t
Data Output: This parameter is characterized, and tested indirectly by testing T
7: Ensured by the T
3.4 MHz specification test.
AA
8: The specification is not part of the I
Standard Operating Conditions (unless otherwise specified)
Operating Temperature –40°C ≤ T
Operating Voltage V
range is described in Electrical characteristics
DD
A ≤ +125°C (Extended)
400 kHz mode 600 — ns 2.7V-5.5V
1.7 MHz mode 120 ns 4.5V-5.5V
3.4 MHz mode 60 — ns 4.5V-5.5V
400 kHz mode 1300 — ns 2.7V-5. 5V
1.7 MHz mode 320 ns 4.5V-5.5V
3.4 MHz mode 160 — ns 4.5V-5.5V
2
C-bus device can be used in a standard-mode (100 kHz) I2C-bus system, but the
2
C specification, but m ust be tested
) or Clock Low time (T
SU:DAT
.
SP
2
C specification. TAA = T
HD:DAT
+ T
FSDA
(or T
102
RSDA
110
).
and VIL of
IH
LOW
parameter.
AA
) can be
DS22272A-page 10 © 2011 Microchip Technology Inc.
MCP4706/4716/4726
TABLE 1-3: I2C BUS DATA REQUIREMENTS (SLAVE MODE) (CONTINUED)
I2C AC Characteristics
Param.
Sym Characteristic Min Max Units Conditions
No.
(5)
T
SCL rise time 100 kHz mo de — 1000 ns Cb is specified to be from
102A
102B
103A
103B
(5)
(5)
(5)
RSCL
T
SDA rise time 100 kHz mode — 1000 ns Cb is specified to be from
RSDA
T
SCL fall time 100 kH z mode — 300 ns Cb is specified to be from
FSCL
T
SDA fall time 100 kHz mode — 300 ns Cb is specified to be from
FSDA
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid uninten ded gene ration of START or STOP conditions.
2: A fast-mode (400 kHz) I
requirement t
≥ 250 ns must then be met. This will automatically be the case if the device does not
SU;DAT
stretch the LOW period of the SCL sig nal . If such a de vic e do es stretch the LOW period of the SCL signal,
it must output the next data bit to the SDA line.
max.+t
T
R
= 1000 + 250 = 1250 ns (according to the standard-mode I2C bus specification) before
SU;DAT
the SCL line is released.
3: The MCP47X6 device must provide a data hold time to bridge the undefined part between V
the falling edge of the SCL s ignal. This specificati on is not a p art of the I
in order to ensure that the output data will meet the setup and hold specifications for the receiving device.
4: Use C
in pF for the calculations.
b
5: Not Tested. This parameter ensured by characterization.
6: A Master Transmitter must provide a delay to ensure that difference between SDA and SCL fall times do
not unintentionally create a Start or Stop condition.
If this parameter is too short, it can create an unintentional Start or Stop condition to other devices on the
2
C bus line. If this parameter is too long, the Data Input Setup (T
I
affected.
Data Input: This parameter must be longer than t
Data Output: This parameter is characterized, and tested indirectly by testing T
7: Ensured by the T
3.4 MHz specification test.
AA
8: The specification is not part of the I2C specification. TAA = T
Standard Operating Conditions (unless otherwise specified)
Operating Temperature –40°C ≤ T
Operating Voltage V
range is described in Electrical characteristics
DD
400 kHz mode 20 + 0.1Cb 300 ns
1.7 MHz mode 20 80 ns
A ≤ +125°C (Extended)
10 to 400 pF (100 pF
maximum for 3.4 MHz
mode)
1.7 MHz mode 20 160 ns After a Repeated Start
condition or an
Acknowledge bit
3.4 MHz mode 10 40 ns
3.4 MHz mode 10 80 ns After a Repeated Start
condition or an
Acknowledge bit
400 kHz mode 20 + 0.1Cb 300 ns
1.7 MHz mode 20 160 ns
10 to 400 pF (100 pF max
for 3.4 MHz mode)
3.4 MHz mode 10 80 ns
400 kHz mode 20 + 0.1Cb 300 ns
1.7 MHz mode 20 80 ns
10 to 400 pF (100 pF max
for 3.4 MHz mode)
3.4 MHz mode 10 40 ns
(4)
400 kHz mode 20 + 0.1Cb
300 ns
1.7 MHz mode 20 160 ns
10 to 400 pF (100 pF max
for 3.4 MHz mode)
3.4 MHz mode 10 80 ns
2
C-bus device can be used in a standard-mode (100 kHz) I2C-bus system, but the
and VIL of
AA
).
IH
) can be
LOW
parameter.
.
SP
HD:DAT
2
C specification, but m ust be tested
) or Clock Low time (T
SU:DAT
+ T
FSDA
(or T
RSDA
© 2011 Microchip Technology Inc. DS22272A-page 11
MCP4706/4716/4726
TABLE 1-3: I2C BUS DATA REQUIREMENTS (SLAVE MODE) (CONTINUED)
I2C AC Characteristics
Param.
Sym Characteristic Min Max Units Conditions
No.
106 T
HD:DAT
Data input hold
time
107 T
SU:DAT
Data input setup
time
109 T
AA
Output valid
from clock
110 T
BUF Bus free time 100 kHz mode 4700 — ns Time the bus must be free
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid uninten ded gene ration of START or STOP conditions.
2: A fast-mode (400 kHz) I
requirement t
≥ 250 ns must then be met. This will automatically be the case if the device does not
SU;DAT
stretch the LOW period of the SCL signal . If suc h a de vic e do es stretc h the LO W peri od of the SCL sig nal ,
it must output the next data bit to the SDA line.
max.+t
T
R
= 1000 + 250 = 1250 ns (according to the standard-mode I2C bus specification) before
SU;DAT
the SCL line is released.
3: The MCP47X6 device must provide a data hold time to bridge the undefined part between V
the falling edge of the SCL s ignal. This specificati on is not a p art of the I
in order to ensure that the output data will meet the setup and hold specifications for the receiving device.
4: Use C
in pF for the calculations.
b
5: Not Tested. This parameter ensured by characterization.
6: A Master Transmitter must provide a delay to ensure that difference between SDA and SCL fall times do
not unintentionally create a Start or Stop condition.
If this parameter is too short, it can create an unintentional Start or Stop condition to other devices on the
I2C bus line. If this parameter is too long, the Data Input Setup (T
affected.
Data Input: This parameter must be longer than t
Data Output: This parameter is characterized, and tested indirectly by testing T
7: Ensured by the TAA 3.4 MHz specification test.
8: The specification is not part of the I
Standard Operating Conditions (unless otherwise specified)
Operating Temperature –40°C ≤ T
Operating Voltage V
range is described in Electrical characteristics
DD
A ≤ +125°C (Extended)
100 kHz mode 0 — ns 2.7V-5.5V, Note 6
400 kHz mode 0 — ns 2.7V-5.5V, Note 6
1.7 MHz mode 0 — ns 4.5V-5.5V, Note 6
3.4 MHz mode 0 — ns 4.5V-5.5V, Note 6
100 kHz mode 250 — ns Note 2
400 kHz mode 100 — ns
1.7 MHz mode 10 — ns
3.4 MHz mode 10 — ns
100 kHz mode — 3750 ns Note 1, Note 8
400 kHz mode — 1200 ns
1.7 MHz mode — 150 ns Cb = 100 pF,
Note 1, Note 7, Note 8
— 310 ns Cb = 400 pF,
Note 1, Note 5, Note 8
3.4 MHz mode — 150 ns Cb = 100 pF,
Note 1, Note 8
400 kHz mode 1300 — ns
1.7 MHz mode N.A. — ns
before a new transmission
can start
3.4 MHz mode N.A. — ns
2
C-bus device can be used in a standard-mode (100 kHz) I2C-bus system, but the
and VIL of
AA
).
IH
) can be
LOW
parameter.
2
C specification. TAA = T
.
SP
HD:DAT
2
C specification, but m ust be tested
) or Clock Low time (T
SU:DAT
+ T
FSDA
(or T
RSDA
DS22272A-page 12 © 2011 Microchip Technology Inc.
MCP4706/4716/4726
TABLE 1-3: I2C BUS DATA REQUIREMENTS (SLAVE MODE) (CONTINUED)
I2C AC Characteristics
Param.
Sym Characteristic Min Max Units Conditions
No.
111 TSP Input filter spike
suppression
(SDA and SCL)
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid uninten ded gene ration of START or STOP conditions.
2: A fast-mode (400 kHz) I
requirement t
≥ 250 ns must then be met. This will automatically be the case if the device does not
SU;DAT
stretch the LOW period of the SCL sig nal . If such a de vic e do es stretch the LOW period of the SCL signal,
it must output the next data bit to the SDA line.
max.+t
T
R
= 1000 + 250 = 1250 ns (according to the standard-mode I2C bus specification) before
SU;DAT
the SCL line is released.
3: The MCP47X6 device must provide a data hold time to bridge the undefined part between V
the falling edge of the SCL s ignal. This specificati on is not a p art of the I
in order to ensure that the output data will meet the setup and hold specifications for the receiving device.
4: Use C
in pF for the calculations.
b
5: Not Tested. This parameter ensured by characterization.
6: A Master Transmitter must provide a delay to ensure that difference between SDA and SCL fall times do
not unintentionally create a Start or Stop condition.
If this parameter is too short, it can create an unintentional Start or Stop condition to other devices on the
2
C bus line. If this parameter is too long, the Data Input Setup (T
I
affected.
Data Input: This parameter must be longer than t
Data Output: This parameter is characterized, and tested indirectly by testing T
7: Ensured by the T
3.4 MHz specification test.
AA
8: The specification is not part of the I2C specification. TAA = T
Standard Operating Conditions (unless otherwise specified)
Operating Temperature –40°C ≤ T
Operating Voltage V
range is described in Electrical characteristics
DD
A ≤ +125°C (Extended)
100 kHz mode — 50 ns NXP Spec states N.A.
400 kHz mode — 50 ns
1.7 MHz mode — 10 ns Spike suppression
3.4 MHz mode — 10 ns Spike suppression
— — — ns Standard Mode,
(Not Applicable)
50 (typ) — — ns Fast Mode
10 (typ) — — ns High Speed Mode 1.7
10 (typ) — — ns High Speed Mode 3.4
2
C-bus device can be used in a standard-mode (100 kHz) I2C-bus system, but the
and VIL of
AA
).
IH
) can be
LOW
parameter.
.
SP
HD:DAT
2
C specification, but m ust be tested
) or Clock Low time (T
SU:DAT
+ T
FSDA
(or T
RSDA
© 2011 Microchip Technology Inc. DS22272A-page 13
MCP4706/4716/4726
TEMPERATURE CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, VDD= +2.7V to +5.5V, VSS= GND.
Parameters Symbol Min Typical Max Units Conditions
Temperature Ranges
Specified Temperature Range T
Operating Temperature Range T
Storage Temperature Range T
Thermal Package Resistances
Thermal Resistance, 6L-SOT-23 θ
Thermal Resistance, 6L-DFN (2 x 2) θ
Note 1: The MCP47X6 devices operate over this extended temperature range, but with reduced performance.
Operation in this range must not cause T
A
A
A
JA
JA
-40 — +125 °C
-40 — +125 °C Note 1
-65 — +150 °C
—190—°C/W
—91—°C/W
to exceed the Maximum Junction Temperature of +150°C.
J
DS22272A-page 14 © 2011 Microchip Technology Inc.
MCP4706/4716/4726
2.0 TYPICAL PERFORMANCE CURVES
Note: The graphs and tables provided fol lowing this note are a st atistical summary b as ed on a l im ite d n um ber of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note: Unless otherwise indicate d, TA = +25°C, VDD = 5V , VSS = 0V, VRL = Internal, Gain = x1, R
12
-40C
+25C
+85C
8
+125C
4
0
-4
INL Error (LSb)
-8
-12
0 1024 2048 3072 4096
Volatile DAC Register Code
FIGURE 2-1: INL vs. Code (code = 100 to
4000) and Temperature (MCP4726).
V
DD
-1
INL Error (LSb)
= 5V, V
3
-40C
+25C
+85C
2
+125C
1
0
REF1:VREF0
= ‘00’.
12
-40C
+25C
+85C
8
+125C
4
0
-4
INL Error (LSb)
-8
-12
0 1024 2048 3072 4096
Volatile DAC Register Code
FIGURE 2-4: INL vs. Code (code = 100 to
4000) and Temperature (MCP4726).
V
DD
-1
INL Error (LSb)
= 2.7V, V
3
-40C
+25C
+85C
2
+125C
1
0
REF1:VREF0
= ‘00’.
= 5 kΩ, C
L
= 100 pF .
L
-2
-3
0 128 256 384 512 640 768 896 1024
Volatile DAC Register Code
FIGURE 2-2: INL vs. Code (code = 25 to
1000) and Temperature (MCP4716).
V
= 5V, V
DD
INL Error (LSb)
-0.5
-1.0
1.0
0.5
0.0
REF1:VREF0
-40C
+25C
+85C
+125C
0 32 64 96 128 160 192 224 256
= ‘00’.
Volatile DAC Register Code
FIGURE 2-3: INL vs. Code (code = 6 to
250) and Temperature (MCP4706).
V
= 5V, V
DD
REF1:VREF0
= ‘00’.
-2
-3
0 128 256 384 512 640 768 896 1024
Volatile DAC Register Code
FIGURE 2-5: INL vs. Code (code = 25 to
1000) and Temperature (MCP4716).
V
= 2.7V, V
DD
1.0
0.5
0.0
INL Error (LSb)
-0.5
-1.0
0 32 64 96 128 160 192 224 256
REF1:VREF0
-40C
+25C
+85C
+125C
Volatile DAC Register Code
= ‘00’.
FIGURE 2-6: INL vs. Code (code = 6 to
250) and Temperature (MCP4706).
V
= 2.7V, V
DD
REF1:VREF0
= ‘00’.
© 2011 Microchip Technology Inc. DS22272A-page 15
MCP4706/4716/4726
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V, VRL = Internal, Gain = x1, RL = 5 kΩ, CL = 100 pF.
0.4
0.3
0.2
0.1
0.0
-0.1
DNL Error (LSb)
-0.2
-40C
+25C
-0.3
+85C
+125C
-0.4
0 1024 2048 3072 4096
Volatile DAC Register Code
FIGURE 2-7: DNL vs. Code (code = 100
to 4000) and Temperature (MCP4726).
V
DD
= 5V, V
0.3
REF1:VREF0
= ‘00’.
0.4
0.3
0.2
0.1
0.0
-0.1
DNL Error (LSb)
-0.2
-40C
+25C
-0.3
+85C
+125C
-0.4
0 1024 2048 3072 4096
Volatile DAC Register Code
FIGURE 2-10: DNL vs. Code (code = 100
to 4000) and Temperature (MCP4726).
V
DD
= 2.7V, V
0.3
REF1:VREF0
= ‘00’.
0.2
0.1
0.0
-0.1
DNL Error (LSb)
-40C
-0.2
+25C
+85C
+125C
-0.3
0 128 256 384 512 640 768 896 1024
Volatile DAC Register Code
FIGURE 2-8: DNL vs. Code (code = 25 to
1000) and Temperature (MCP4716).
V
= 5V, V
DD
0.20
0.15
0.10
0.05
0.00
-0.05
DNL Error (LSb)
-0.10
-0.15
-0.20
REF1:VREF0
-40C
+25C
+85C
+125C
0 32 64 96 128 160 192 224 256
= ‘00’.
Volatile DAC Register Code
FIGURE 2-9: DNL vs. Code (code = 6 to
250) and Temperature (MCP4706).
V
= 5V, V
DD
REF1:VREF0
= ‘00’.
0.2
0.1
0.0
-0.1
DNL Error (LSb)
-40C
-0.2
+25C
+85C
+125C
-0.3
0 128 256 384 512 640 768 896 1024
Volatile DAC Register Code
FIGURE 2-11: DNL vs. Code (code = 25 to
1000) and Temperature (MCP4716).
V
= 2.7V, V
DD
0.20
0.15
0.10
0.05
0.00
-0.05
DNL Error (LSb)
-0.10
-0.15
-0.20
REF1:VREF0
-40C
+25C
+85C
+125C
0 32 64 96 128 160 192 224 256
Volatile DAC Register Code
= ‘00’.
FIGURE 2-12: DNL vs. Code (code = 6 to
250) and Temperature (MCP4706).
V
= 2.7V, V
DD
REF1:VREF0
= ‘00’.
DS22272A-page 16 © 2011 Microchip Technology Inc.
MCP4706/4716/4726
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V, VRL = Internal, Gain = x1, RL = 5 kΩ, CL = 100 pF.
2.0
2.7V
5.0V
5.5V
1.5
1.0
Zero Scale Error (LSb)
0.5
0.0
-40 -20 0 20 40 60 80 100 120
Temperature (°C)
FIGURE 2-13: Zero Scale Error (ZSE) vs.
Temperature (MCP4726).
V
= 5V, V
DD
0.5
0.4
0.3
0.2
Zero Scale Error (LSb)
0.1
0.0
REF1:VREF0
2.7V
5.0V
5.5V
-40 -20 0 20 40 60 80 100 120
= ‘00’.
Temperature (°C)
FIGURE 2-14: Zero Scale Error (ZSE) vs.
Temperature (MCP4716).
V
DD
= 5V, V
0.20
0.15
REF1:VREF0
2.7V
5.0V
5.5V
= ‘00’.
-18.0
-20.0
-22.0
-24.0
-26.0
Full Scale Error (LSb)
-28.0
2.7V
-30.0
5.0V
5.5V
-32.0
-40 -20 0 20 40 60 80 100 120
Temperature (°C)
FIGURE 2-16: Full Scale Error (FSE) vs.
Temperature (MCP4726).
V
= 2.7V, V
DD
-4.0
-5.0
-6.0
Full Scale Error (LSb)
-7.0
-8.0
-40 -20 0 20 40 60 80 100 120
REF1:VREF0
2.7V
5.0V
5.5V
= ‘00’.
Temperature (°C)
FIGURE 2-17: Full Scale Error (FSE) vs.
Temperature (MCP4716).
V
DD
-0.5
= 2.7V, V
0.0
REF1:VREF0
= ‘00’.
0.10
Zero Scale Error (LSb)
0.05
0.00
-40 -20 0 20 40 60 80 100 120
Temperature (°C)
FIGURE 2-15: Zero Scale Error (ZSE) vs.
Temperature (MCP4706).
V
= 5V, V
DD
REF1:VREF0
= ‘00’.
-1.0
Full Scale Error (LSb)
-1.5
2.7V
5.0V
5.5V
-2.0
-40 -20 0 20 40 60 80 100 120
Temperature (°C)
FIGURE 2-18: Full Scale Error (FSE) vs.
Temperature (MCP4706).
V
= 2.7V, V
DD
REF1:VREF0
= ‘00’.
© 2011 Microchip Technology Inc. DS22272A-page 17
MCP4706/4716/4726
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V, VRL = Internal, Gain = x1, RL = 5 kΩ, CL = 100 pF.
12
-40C
+25C
+85C
8
+125C
4
12
-40C
+25C
+85C
8
+125C
4
0
-4
INL Error (LSb)
-8
-12
0 1024 2048 3072 4096
Volatile DAC Register Code
FIGURE 2-19: INL vs. Code (code = 100 to
4000) and Temperature (MCP4726).
V
= 5V, V
DD
V
REF
3
2
1
0
-1
INL Error (LSb)
-2
-3
= VDD.
REF1:VREF0
-40C
+25C
+85C
+125C
0 128 256 384 512 640 768 896 1024
= ‘10’, G = ‘0’,
Volatile DAC Register Code
FIGURE 2-20: INL vs. Code (code = 25 to
1000) and Temperature (MCP4716).
V
V
DD
REF
= 5V, V
= VDD.
1.0
-40C
+25C
+85C
+125C
0.5
REF1:VREF0
= ‘10’, G = ‘0’,
0
-4
INL Error (LSb)
-8
-12
0 1024 2048 3072 4096
Volatile DAC Register Code
FIGURE 2-22: INL vs. Code (code = 100 to
4000) and Temperature (MCP4726).
V
= 2.7V, V
DD
V
= VDD.
REF
3
2
1
0
-1
INL Error (LSb)
-2
-3
0 128 256 384 512 640 768 896 1024
-40C
+25C
+85C
+125C
REF1:VREF0
Volatile DAC Register Code
= ‘10’, G = ‘0’,
FIGURE 2-23: INL vs. Code (code = 25 to
1000) and Temperature (MCP4716).
V
V
DD
REF
= 2.7V, V
= VDD.
1.0
-40C
+25C
+85C
+125C
0.5
REF1:VREF0
= ‘10’, G = ‘0’,
0.0
INL Error (LSb)
-0.5
-1.0
0 32 64 96 128 160 192 224 256
Volatile DAC Register Code
FIGURE 2-21: INL vs. Code (code = 6 to
250) and Temperature (MCP4706).
V
V
DD
REF
= 5V, V
= VDD.
REF1:VREF0
= ‘10’, G = ‘0’,
0.0
INL Error (LSb)
-0.5
-1.0
0 32 64 96 128 160 192 224 256
Volatile DAC Register Code
FIGURE 2-24: INL vs. Code (code = 6 to
250) and Temperature (MCP4706).
V
V
DD
REF
= 2.7V, V
= VDD.
REF1:VREF0
= ‘10’, G = ‘0’,
DS22272A-page 18 © 2011 Microchip Technology Inc.
MCP4706/4716/4726
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V, VRL = Internal, Gain = x1, RL = 5 kΩ, CL = 100 pF.
0.4
0.3
0.2
0.1
0.0
-0.1
DNL Error (LSb)
-0.2
-40C
+25C
-0.3
+85C
+125C
-0.4
0 1024 2048 3072 4096
Volatile DAC Register Code
FIGURE 2-25: DNL vs. Code (code = 100
to 4000) and Temperature (MCP4726).
V
V
DD
REF
= 5V, V
= VDD.
0.3
REF1:VREF0
= ‘10’, G = ‘0’,
0.4
0.3
0.2
0.1
0.0
-0.1
DNL Error (LSb)
-0.2
-40C
+25C
-0.3
+85C
+125C
-0.4
0 1024 2048 3072 4096
Volatile DAC Register Code
FIGURE 2-28: DNL vs. Code (code = 100
to 4000) and Temperature (MCP4726).
V
V
DD
REF
= 2.7V, V
= VDD.
0.3
REF1:VREF0
= ‘10’, G = ‘0’,
0.2
0.1
0.0
-0.1
DNL Error (LSb)
-40C
-0.2
+25C
+85C
+125C
-0.3
0 128 256 384 512 640 768 896 1024
Volatile DAC Register Code
FIGURE 2-26: DNL vs. Code (code = 25 to
1000) and Temperature (MCP4716).
V
= 5V, V
DD
V
REF
0.20
0.15
0.10
0.05
0.00
-0.05
DNL Error (LSb)
-0.10
-0.15
-0.20
= VDD.
REF1:VREF0
-40C
+25C
+85C
+125C
0 32 64 96 128 160 192 224 256
= ‘10’, G = ‘0’,
Volatile DAC Register Code
FIGURE 2-27: DNL vs. Code (code = 6 to
250) and Temperature (MCP4706).
V
V
DD
REF
= 5V, V
= VDD.
REF1:VREF0
= ‘10’, G = ‘0’,
0.2
0.1
0.0
-0.1
DNL Error (LSb)
-40C
-0.2
+25C
+85C
+125C
-0.3
0 128 256 384 512 640 768 896 1024
Volatile DAC Register Code
FIGURE 2-29: DNL vs. Code (code = 25 to
1000) and Temperature (MCP4716).
V
= 2.7V, V
DD
V
REF
0.20
0.15
0.10
0.05
0.00
-0.05
DNL Error (LSb)
-0.10
-0.15
-0.20
= VDD.
REF1:VREF0
-40C
+25C
+85C
+125C
0 32 64 96 128 160 192 224 256
Volatile DAC Register Code
= ‘10’, G = ‘0’,
FIGURE 2-30: DNL vs. Code (code = 6 to
250) and Temperature (MCP4706).
V
V
DD
REF
= 2.7V, V
= VDD.
REF1:VREF0
= ‘10’, G = ‘0’,
© 2011 Microchip Technology Inc. DS22272A-page 19
MCP4706/4716/4726
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V, VRL = Internal, Gain = x1, RL = 5 kΩ, CL = 100 pF.
2.0
2.7V
5.0V
5.5V
1.5
1.0
Zero Scale Error (LSb)
0.5
0.0
-40 -20 0 20 40 60 80 100 120
Temperature (°C)
FIGURE 2-31: Zero Scale Error (ZSE) vs.
Temperature (MCP4726).
V
= 5V, V
DD
V
= VDD.
REF
0.5
0.4
0.3
0.2
Zero Scale Error (LSb)
0.1
0.0
REF1:VREF0
2.7V
5.0V
5.5V
-40 -20 0 20 40 60 80 100 120
= ‘10’, G = ‘0’,
Temperature (°C)
FIGURE 2-32: Zero Scale Error (ZSE) vs.
Temperature (MCP4716).
V
V
DD
REF
= 5V, V
= VDD.
0.20
0.15
REF1:VREF0
2.7V
5.0V
5.5V
= ‘10’, G = ‘0’,
-18.0
-20.0
-22.0
-24.0
-26.0
Full Scale Error (LSb)
-28.0
2.7V
-30.0
5.0V
5.5V
-32.0
-40 -20 0 20 40 60 80 100 120
Temperature (°C)
FIGURE 2-34: Full Scale Error (FSE) vs.
Temperature (MCP4726).
V
= 2.7V, V
DD
V
= VDD.
REF
-4.0
-5.0
-6.0
Full Scale Error (LSb)
-7.0
-8.0
-40 -20 0 20 40 60 80 100 120
REF1:VREF0
2.7V
5.0V
5.5V
= ‘10’, G = ‘0’,
Temperature (°C)
FIGURE 2-35: Full Scale Error (FSE) vs.
Temperature (MCP4716).
V
V
DD
REF
-0.5
= 2.7V, V
= VDD.
0.0
REF1:VREF0
= ‘10’, G = ‘0’,
0.10
Zero Scale Error (LSb)
0.05
0.00
-40 -20 0 20 40 60 80 100 120
Temperature (°C)
FIGURE 2-33: Zero Scale Error (ZSE) vs.
Temperature (MCP4706).
V
V
DD
REF
= 5V, V
= VDD.
REF1:VREF0
= ‘10’, G = ‘0’,
-1.0
Full Scale Error (LSb)
-1.5
2.7V
5.0V
5.5V
-2.0
-40 -20 0 20 40 60 80 100 120
Temperature (°C)
FIGURE 2-36: Full Scale Error (FSE) vs.
Temperature (MCP4706).
V
V
DD
REF
= 2.7V, V
= VDD.
REF1:VREF0
= ‘10’, G = ‘0’,
DS22272A-page 20 © 2011 Microchip Technology Inc.
MCP4706/4716/4726
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V, VRL = Internal, Gain = x1, RL = 5 kΩ, CL = 100 pF.
12
-40C
+25C
+85C
8
+125C
4
12
-40C
+25C
+85C
8
+125C
4
0
-4
INL Error (LSb)
-8
-12
0 1024 2048 3072 4096
Volatile DAC Register Code
FIGURE 2-37: INL vs. Code (code = 100 to
4000) and Temperature (MCP4726).
V
= 5V, V
DD
V
REF
-1
INL Error (LSb)
-2
-3
= VDD.
3
2
1
0
REF1:VREF0
-40C
+25C
+85C
+125C
0 128 256 384 512 640 768 896 1024
= ‘11’, G = ‘0’,
Volatile DAC Register Code
FIGURE 2-38: INL vs. Code (code = 25 to
1000) and Temperature (MCP4716).
V
V
DD
REF
= 5V, V
= VDD.
1.0
-40C
+25C
+85C
+125C
0.5
REF1:VREF0
= ‘11’, G = ‘0’,
0
-4
INL Error (LSb)
-8
-12
0 1024 2048 3072 4096
Volatile DAC Register Code
FIGURE 2-40: INL vs. Code (code = 100 to
4000) and Temperature (MCP4726).
V
= 2.7V, V
DD
V
= VDD.
REF
3
2
1
0
-1
INL Error (LSb)
-2
-3
0 128 256 384 512 640 768 896 1024
-40C
+25C
+85C
+125C
REF1:VREF0
Volatile DAC Register Code
= ‘11’, G = ‘0’,
FIGURE 2-41: INL vs. Code (code = 25 to
1000) and Temperature (MCP4716).
V
V
DD
REF
= 2.7V, V
= VDD.
1.0
-40C
+25C
+85C
+125C
0.5
REF1:VREF0
= ‘11’, G = ‘0’,
0.0
INL Error (LSb)
-0.5
-1.0
0 32 64 96 128 160 192 224 256
Volatile DAC Register Code
FIGURE 2-39: INL vs. Code (code = 6 to
250) and Temperature (MCP4706).
V
V
DD
REF
= 5V, V
= VDD.
REF1:VREF0
= ‘11’, G = ‘0’,
0.0
INL Error (LSb)
-0.5
-1.0
0 32 64 96 128 160 192 224 256
Volatile DAC Register Code
FIGURE 2-42: INL vs. Code (code = 6 to
250) and Temperature (MCP4706).
V
V
DD
REF
= 2.7V, V
= VDD.
REF1:VREF0
= ‘11’, G = ‘0’,
© 2011 Microchip Technology Inc. DS22272A-page 21
MCP4706/4716/4726
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V, VRL = Internal, Gain = x1, RL = 5 kΩ, CL = 100 pF.
0.4
0.3
0.2
0.1
0.0
-0.1
DNL Error (LSb)
-0.2
-40C
+25C
-0.3
+85C
+125C
-0.4
0 1024 2048 3072 4096
Volatile DAC Register Code
FIGURE 2-43: DNL vs. Code (code = 100
to 4000) and Temperature (MCP4726).
V
V
DD
REF
= 5V, V
= VDD.
0.3
REF1:VREF0
= ‘11’, G = ‘0’,
0.4
0.3
0.2
0.1
0.0
-0.1
DNL Error (LSb)
-0.2
-40C
+25C
-0.3
+85C
+125C
-0.4
0 1024 2048 3072 4096
Volatile DAC Register Code
FIGURE 2-46: DNL vs. Code (code = 100
to 4000) and Temperature (MCP4726).
V
V
DD
REF
= 2.7V, V
= VDD.
0.3
REF1:VREF0
= ‘11’, G = ‘0’,
0.2
0.1
0.0
-0.1
DNL Error (LSb)
-40C
-0.2
+25C
+85C
+125C
-0.3
0 128 256 384 512 640 768 896 1024
Volatile DAC Register Code
FIGURE 2-44: DNL vs. Code (code = 25 to
1000) and Temperature (MCP4716).
V
= 5V, V
DD
V
REF
0.20
0.15
0.10
0.05
0.00
-0.05
DNL Error (LSb)
-0.10
-0.15
-0.20
= VDD.
REF1:VREF0
-40C
+25C
+85C
+125C
0 32 64 96 128 160 192 224 256
= ‘11’, G = ‘0’,
Volatile DAC Register Code
FIGURE 2-45: DNL vs. Code (code = 6 to
250) and Temperature (MCP4706).
V
V
DD
REF
= 5V, V
= VDD.
REF1:VREF0
= ‘11’, G = ‘0’,
0.2
0.1
0.0
-0.1
DNL Error (LSb)
-40C
-0.2
+25C
+85C
+125C
-0.3
0 128 256 384 512 640 768 896 1024
Volatile DAC Register Code
FIGURE 2-47: DNL vs. Code (code = 25 to
1000) and Temperature (MCP4716).
V
= 2.7V, V
DD
V
REF
0.20
0.15
0.10
0.05
0.00
-0.05
DNL Error (LSb)
-0.10
-0.15
-0.20
= VDD.
REF1:VREF0
-40C
+25C
+85C
+125C
0 32 64 96 128 160 192 224 256
Volatile DAC Register Code
= ‘11’, G = ‘0’,
FIGURE 2-48: DNL vs. Code (code = 6 to
250) and Temperature (MCP4706).
V
V
DD
REF
= 2.7V, V
= VDD.
REF1:VREF0
= ‘11’, G = ‘0’,
DS22272A-page 22 © 2011 Microchip Technology Inc.
MCP4706/4716/4726
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V, VRL = Internal, Gain = x1, RL = 5 kΩ, CL = 100 pF.
2.0
2.7V
5.0V
5.5V
1.5
1.0
Zero Scale Error (LSb)
0.5
0.0
-40 -20 0 20 40 60 80 100 120
Temperature (°C)
FIGURE 2-49: Zero Scale Error (ZSE) vs.
Temperature (MCP4726).
V
= 5V, V
DD
V
= VDD.
REF
0.5
0.4
0.3
0.2
Zero Scale Error (LSb)
0.1
0.0
REF1:VREF0
2.7V
5.0V
5.5V
-40 -20 0 20 40 60 80 100 120
= ‘11’, G = ‘0’,
Temperature (°C)
FIGURE 2-50: Zero Scale Error (ZSE) vs.
Temperature (MCP4716).
V
V
DD
REF
= 5V, V
= VDD.
0.20
0.15
REF1:VREF0
2.7V
5.0V
5.5V
= ‘11’, G = ‘0’,
-18.0
-20.0
-22.0
-24.0
-26.0
Full Scale Error (LSb)
-28.0
2.7V
-30.0
5.0V
5.5V
-32.0
-40 -20 0 20 40 60 80 100 120
Temperature (°C)
FIGURE 2-52: Full Scale Error (FSE) vs.
Temperature (MCP4726).
V
= 2.7V, V
DD
V
= VDD.
REF
-4.0
-5.0
-6.0
Full Scale Error (LSb)
-7.0
-8.0
-40 -20 0 20 40 60 80 100 120
REF1:VREF0
2.7V
5.0V
5.5V
= ‘11’, G = ‘0’,
Temperature (°C)
FIGURE 2-53: Full Scale Error (FSE) vs.
Temperature (MCP4716).
V
V
DD
REF
-0.5
= 2.7V, V
= VDD.
0.0
REF1:VREF0
= ‘11’, G = ‘0’,
0.10
Zero Scale Error (LSb)
0.05
0.00
-40 -20 0 20 40 60 80 100 120
Temperature (°C)
FIGURE 2-51: Zero Scale Error (ZSE) vs.
Temperature (MCP4706).
V
V
DD
REF
= 5V, V
= VDD.
REF1:VREF0
= ‘11’, G = ‘0’,
-1.0
Full Scale Error (LSb)
-1.5
2.7V
5.0V
5.5V
-2.0
-40 -20 0 20 40 60 80 100 120
Temperature (°C)
FIGURE 2-54: Full Scale Error (FSE) vs.
Temperature (MCP4706).
V
V
DD
REF
= 2.7V, V
= VDD.
REF1:VREF0
= ‘11’, G = ‘0’,
© 2011 Microchip Technology Inc. DS22272A-page 23
MCP4706/4716/4726
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V, VRL = Internal, Gain = x1, RL = 5 kΩ, CL = 100 pF.
16
2.7V
5.0V
5.5V
12
8
4
0
INL Error (LSb)
-4
-8
0 1024 2048 3072 4096
Volatile DAC Register Code
FIGURE 2-55: INL vs. Code (code = 100 to
4000) and V
V
REF1:VREF0
(2.7V, 5V, 5.5V) (MCP4726).
DD
= ‘10’, G = ‘1’, V
= VDD/2,
REF
Temp = +25°C.
3
2.7V
5.0V
5.5V
2
1
0
-1
INL Error (LSb)
-2
-3
0 128 256 384 512 640 768 896 1024
Volatile DAC Register Code
FIGURE 2-56: INL vs. Code (code = 25 to
1000) and V
V
REF1:VREF0
(2.7V, 5V, 5.5V) (MCP4716).
DD
= ‘10’, G = ‘1’, V
= VDD/2,
REF
Temp = +25°C.
1.0
2.7V
5.0V
5.5V
0.5
0.0
INL Error (LSb)
-0.5
-1.0
0 32 64 96 128 160 192 224 256
Volatile DAC Register Code
FIGURE 2-57: INL vs. Code (code = 6 to
250) and V
V
REF1:VREF0
(2.7V, 5V, 5.5V) (MCP4706).
DD
= ‘10’, G = ‘1’, V
= VDD/2,
REF
Temp = +25°C.
0.5
0.4
0.3
0.2
0.1
0.0
-0.1
-0.2
DNL Error (LSb)
-0.3
2.7V
5.0V
-0.4
5.5V
-0.5
0 1024 2048 3072 4096
Volatile DAC Register Code
FIGURE 2-58: DNL vs. Code (code = 100
to 4000) and V
V
REF1:VREF0
(2.7V, 5V, 5.5V) (MCP4726).
DD
= ‘10’, G = ‘1’, V
= VDD/2,
REF
Temp = +25°C.
0.4
0.3
0.2
0.1
0.0
DNL Error (LSb)
-0.1
2.7V
-0.2
5.0V
5.5V
-0.3
0 128 256 384 512 640 768 896 1024
Volatile DAC Register Code
FIGURE 2-59: DNL vs. Code (code = 25 to
1000) and V
V
REF1:VREF0
(2.7V, 5V, 5.5V) (MCP4716).
DD
= ‘10’, G = ‘1’, V
= VDD/2,
REF
Temp = +25°C.
0.30
0.25
0.20
0.15
0.10
0.05
0.00
-0.05
-0.10
DNL Error (LSb)
-0.15
2.7V
-0.20
5.0V
-0.25
5.5V
-0.30
0 32 64 96 128 160 192 224 256
Volatile DAC Register Code
FIGURE 2-60: DNL vs. Code (code = 6 to
250) and V
V
REF1:VREF0
(2.7V, 5V, 5.5V) (MCP4706).
DD
= ‘10’, G = ‘1’, V
= VDD/2,
REF
Temp = +25°C.
DS22272A-page 24 © 2011 Microchip Technology Inc.
MCP4706/4716/4726
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V, VRL = Internal, Gain = x1, RL = 5 kΩ, CL = 100 pF.
16
2.7V
5.0V
5.5V
12
8
4
0
INL Error (LSb)
-4
-8
0 1024 2048 3072 4096
Volatile DAC Register Code
FIGURE 2-61: INL vs. Code (code = 100 to
4000) and V
V
REF1:VREF0
(2.7V, 5V, 5.5V) (MCP4726).
DD
= ‘11’, G = ‘1’, V
= VDD/2,
REF
Temp = +25°C.
3
2.7V
5.0V
5.5V
2
1
0
-1
INL Error (LSb)
-2
-3
0 128 256 384 512 640 768 896 1024
Volatile DAC Register Code
FIGURE 2-62: INL vs. Code (code = 25 to
1000) and V
V
REF1:VREF0
(2.7V, 5V, 5.5V) (MCP4716).
DD
= ‘11’, G = ‘1’, V
= VDD/2,
REF
Temp = +25°C.
1.0
2.7V
5.0V
5.5V
0.5
0.0
INL Error (LSb)
-0.5
-1.0
0 32 64 96 128 160 192 224 256
Volatile DAC Register Code
FIGURE 2-63: INL vs. Code (code = 6 to
250) and V
V
REF1:VREF0
(2.7V, 5V, 5.5V) (MCP4706).
DD
= ‘11’, G = ‘1’, V
= VDD/2,
REF
Temp = +25°C.
0.5
0.4
0.3
0.2
0.1
0.0
-0.1
-0.2
DNL Error (LSb)
-0.3
2.7V
5.0V
-0.4
5.5V
-0.5
0 1024 2048 3072 4096
Volatile DAC Register Code
FIGURE 2-64: DNL vs. Code (code = 100
to 4000) and V
V
REF1:VREF0
(2.7V, 5V, 5.5V) (MCP4726).
DD
= ‘11’, G = ‘1’, V
= VDD/2,
REF
Temp = +25°C.
0.4
0.3
0.2
0.1
0.0
DNL Error (LSb)
-0.1
2.7V
-0.2
5.0V
5.5V
-0.3
0 128 256 384 512 640 768 896 1024
Volatile DAC Register Code
FIGURE 2-65: DNL vs. Code (code = 25 to
1000) and V
V
REF1:VREF0
(2.7V, 5V, 5.5V) (MCP4716).
DD
= ‘11’, G = ‘1’, V
= VDD/2,
REF
Temp = +25°C.
0.30
0.25
0.20
0.15
0.10
0.05
0.00
-0.05
-0.10
DNL Error (LSb)
-0.15
-0.20
2.7V
5.0V
-0.25
5.5V
-0.30
0 32 64 96 128 160 192 224 256
Volatile DAC Register Code
FIGURE 2-66: DNL vs. Code (code = 6 to
250) and V
V
REF1:VREF0
(2.7V, 5V, 5.5V) (MCP4706).
DD
= ‘11’, G = ‘1’, V
= VDD/2,
REF
Temp = +25°C.
© 2011 Microchip Technology Inc. DS22272A-page 25
MCP4706/4716/4726
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V, VRL = Internal, Gain = x1, RL = 5 kΩ, CL = 100 pF.
16
1V
2V
3V
12
4V
5V
8
1.0
1V 2V 3V
4V 5V
0.5
4
0
INL Error (LSb)
-4
-8
0 1024 2048 3072 4096
Volatile DAC Register Code
FIGURE 2-67: INL vs. Code (code = 100 to
4000) and V
V
= 5V, V
DD
V
= 1V, 2V, 3V, 4V, and 5V, Temp = +25°C.
REF
4
1V
2V
3V
3
4V
5V
2
1
0
INL Error (LSb)
-1
-2
0 128 256 384 512 640 768 896 1024
(MCP4726).
REF
REF1:VREF0
Volatile DAC Register Code
= ‘10’, G = ‘0’,
FIGURE 2-68: INL vs. Code (code = 25 to
1000) and V
V
= 5V, V
DD
V
= 1V, 2V, 3V, 4V, and 5V, Temp = +25°C.
REF
1.0
0.5
0.0
INL Error (LSb)
-0.5
1V
2V
3V
4V
5V
-1.0
0 32 64 96 128 160 192 224 256
(MCP4716).
REF
REF1:VREF0
Volatile DAC Register Code
= ‘10’, G = ‘0’,
FIGURE 2-69: INL vs. Code (code = 6 to
250) and V
V
= 5V, V
DD
V
= 1V, 2V, 3V, 4V, and 5V, Temp = +25°C.
REF
(MCP4706).
REF
REF1:VREF0
= ‘10’, G = ‘0’,
0.0
DNL Error (LSb)
-0.5
-1.0
0 1024 2048 3072 4096
Volatile DAC Register Code
FIGURE 2-70: DNL vs. Code (code = 100
to 4000) and V
V
= 5V, V
DD
V
= 1V, 2V, 3V, 4V, and 5V, Temp = +25°C.
REF
0.5
1V 2V 3V
4V 5V
0.4
0.3
0.2
0.1
0.0
-0.1
-0.2
DNL Error (LSb)
-0.3
-0.4
-0.5
0 128 256 384 512 640 768 896 1024
(MCP4726).
REF
REF1:VREF0
Volatile DAC Register Code
= ‘10’, G = ‘0’,
FIGURE 2-71: DNL vs. Code (code = 25 to
1000) and V
V
= 5V, V
DD
V
= 1V, 2V, 3V, 4V, and 5V, Temp = +25°C.
REF
0.5
0.4
0.3
0.2
0.1
0.0
-0.1
-0.2
DNL Error (LSb)
-0.3
-0.4
-0.5
0 32 64 96 128 160 192 224 256
(MCP4716).
REF
REF1:VREF0
1V 2V 3V
4V 5V
Volatile DAC Register Code
= ‘10’, G = ‘0’,
FIGURE 2-72: DNL vs. Code (code = 6 to
250) and V
V
= 5V, V
DD
V
= 1V, 2V, 3V, 4V, and 5V, Temp = +25°C.
REF
(MCP4706).
REF
REF1:VREF0
= ‘10’, G = ‘0’,
DS22272A-page 26 © 2011 Microchip Technology Inc.
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