Datasheet MCP41010T, MCP41050, MCP41050T, MCP41100, MCP41100T Specification

M

MCP41XXX/42XXX

Single/Dual Digital Potentiometer with SPI™ Interface

Features

• 256 taps for each potentiometer

• Potentiometer values for 10 kΩ, 50 kΩ and
100 kΩ

• Single and dual versions

• SPI™ serial interface (mode 0,0 and 1,1)

• ±1 LSB max INL & DNL

• Low power CMOS technology

• 1 µA maximum supply current in static operation

• Multiple devices can be daisy-chained together
(MCP42XXX only)

• Shutdown feature open circuits of all resistors for
maximum power savings

• Hardware shutdown pin available on MCP42XXX
only

• Single supply operation (2.7V - 5.5V)

• Industrial temperature range: -40°C to +85°C

• Extended temperature range: -40°C to +125°C

Block Diagram

SHDN

RS

V

DD

V

SS

S0

Wiper
Register

Wiper

Register

Resistor
Array 1*

Control

Logic

CS

SI

SCK

*Potentiometer P1 is only available on the dual

MCP42XXX version.

16-Bit

Shift

Register

PB0

Resistor
Array 0

PA0
PW0

PB1
PA1

PW1

Description

The MCP41XXX and MCP42XXX devices are 256­position, digital potentiometers available in 10 kΩ,
50 kΩ and 100 kΩ resistance versions. The
MCP41XXX is a single-channel device and is offered in
an 8-pin PDIP or SOIC package. The MCP42XXX con­tains two independent channels in a 14-pin PDIP, SOIC
or TSSOP package. The wiper position of the
MCP41XXX/42XXX varies linearly and is controlled via
an industry-standard SPI interface. The devices con­sume <1 µA during static operation. A software shut­down feature is provided that disconnects the “A”
terminal from the resistor stack and simultaneously con­nects the wiper to the “B” terminal. In addition, the dual
MCP42XXX has a SHDN
function in hardware. During shutdown mode, the con­tents of the wiper register can be changed and the
potentiometer returns from shutdown to the new value.
The wiper is reset to the mid-scale position (80h) upon
power-up. The RS
reset and also returns the wiper to mid-scale. The
MCP42XXX SPI interface includes both the SI and SO
pins, allowing daisy-chaining of multiple devices. Chan­nel-to-channel resistance matching on the MCP42XXX
varies by less than 1%. These devices operate from a
single 2.7 - 5.5V supply and are specified over the
extended and industrial temperature ranges.

pin that performs the same

(reset) pin implements a hardware

Package Types

PDIP/SOIC

CS

SCK

SI

V

SS

PDIP/SOIC/TSSOP

CS

SCK

SI

V

SS

PB1

PW1

PA1

MCP41XXX

1

2

3

4

1

MCP42XXX

2

3

4

5

6

7

14

13

12

11

10

V

8

DD

7

PB0

6

PW0

5

PA0

V

DD

SO

SHDN

RS

PB0

PW0

9

PA0

8

 2003 Microchip Technology Inc. DS11195C-page 1

MCP41XXX/42XXX

1.0 ELECTRICAL CHARACTERISTICS

DC CHARACTERISTICS: 10 kΩ VERSION

Electrical Characteristics: Unless otherwise indicated, V

+85°C). Typical specifications represent values for V

Parameters Sym Min Typ Max Units Conditions

Rheostat Mode

Nominal Resistance R 8 10 12 kΩ T

Rheostat Differential Non Linearity R-DNL -1 ±1/4 +1 LSB Note 2

Rheostat Integral Non Linearity R-INL -1 ±1/4 +1 LSB Note 2
Rheostat Tempco ∆R

Wiper Resistance R

Wiper Current I

/∆T — 800 — ppm/°C

AB

W

R

W

W

Nominal Resistance Match ∆R/R — 0.2 1 % MCP42010 only, P0 to P1; T

Potentiometer Divider

Resolution N 8 — — Bits

Monotonicity N 8 — — Bits

Differential Non-Linearity DNL -1 ±1/4 +1 LSB Note 3

Integral Non-Linearity INL -1 ±1/4 +1 LSB Note 3
Voltage Divider Tempco ∆V

Full Scale Error V

Zero Scale Error V

/∆T — 1 — ppm/°C Code 80h

W

WFSE

V

WFSE

WZSE

V

WZSE

Resistor Terminals

Voltage Range V

Capacitance (C

or CB) — 15 — pF f = 1 MHz, Code = 80h, see Figure 2-30

A

Capacitance C

A,B,W

W

Dynamic Characteristics (All dynamic characteristics use V

Bandwidth -3dB BW — 1 — MHz V

Settling Time t

Resistor Noise Voltage e

Crosstalk C

Digital Inputs/Outputs (CS

, SCK, SI, SO) See Figure 2-12 for RS and SHDN pin operation

Schmitt Trigger High-Level Input Voltage V

Schmitt Trigger Low-Level Input Voltage V

Hysteresis of Schmitt Trigger Inputs V

Low-Level Output Voltage V

High-Level Output Voltage V

Input Leakage Current I

Pin Capacitance (All inputs/outputs) C

S

NWB

T

IH

IL

HYS

OL

OH

LI

, C

IN

OUT

Power Requirements

Operating Voltage Range V

Supply Current, Active I

Supply Current, Static I

DD

— 340 500 µA VDD = 5.5V, CS = VSS, f

DDA

DDS

Power Supply Sensitivity PSS — 0.0015 0.0035 %/% V

PSS — 0.0015 0.0035 %/% V

Note 1: V

= VDD, no connection on wiper.

AB

2: Rheostat position non-linearity R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum

resistance wiper positions. R-DNL measures the relative step change from the ideal between successive tap positions. I

= 3V and IW = 400 µA for VDD = 5V for 10 kΩ version. See Figure 2-26 for test circuit.

V

DD

3: INL and DNL are measured at V

specification limits of ±1 LSB max are specified monotonic operating conditions. See Figure 2-25 for test circuit.

4: Resistor terminals A,B and W have no restrictions on polarity with respect to each other. Full-scale and zero-scale error were measured

using Figure 2-25.

5: Measured at V
6: Supply current is independent of current through the potentiometers.

pin where the voltage on the adjacent VW pin is swinging full-scale.

W

with the device configured in the voltage divider or potentiometer mode. VA = VDD and VB = 0V. DNL

W

= +2.7V to 5.5V, TA = -40°C to +85°C (TSSOP devices are only specified at +25°C and

DD

= 5V, VSS = 0V, VB = 0V, TA = +25°C.

DD

= +25°C (Note 1)

A

— 52 100 Ω VDD = 5.5V, IW = 1 mA, code 00h
— 73 125 Ω VDD = 2.7V, IW = 1 mA, code 00h

-1 — +1 mA

A

-2 -0.7 0 LSB Code FFh, VDD = 5V, see Figure 2-25

-2 -0.7 0 LSB Code FFh, VDD = 3V, see Figure 2-25

0 +0.7 +2 LSB Code 00h, VDD = 5V, see Figure 2-25

0 +0.7 +2 LSB Code 00h, VDD = 3V, see Figure 2-25

0—V

DD

Note 4

— 5.6 — pF f = 1 MHz, Code = 80h, see Figure 2-30

= 5V)

DD

—2—µSV

= 0V, Measured at Code 80h,

B

Output Load = 30

= VDD,VB = 0V, ±1% Error Band, Transition

A

from Code 00h to Code 80h, Output Load = 30 pF

F

P

—9—nV/√Hz VA = Open, Code 80h, f =1 kHz

—-95—dBV

0.7V

— — 0.3V

——V

DD

DD

V

= VDD, VB = 0V (Note 5)

A

—0.05VDD—

— — 0.40 V IOL = 2.1 mA, VDD = 5V

VDD - 0.5 — — V IOH = -400 µA, VDD = 5V

-1 — +1 µA CS = VDD, VIN = VSS or VDD, includes VA SHDN=0

—10—pFVDD = 5.0V, TA = +25°C, fc = 1 MHz

2.7 — 5.5 V

= 10 MHz,

SO = Open, Code FFh (Note 6)

SCK

—0.01 1 µACS, SHDN, RS = VDD = 5.5V, SO = Open (Note 6)

= 4.5V - 5.5V, VA = 4.5V, Code 80h

DD

= 2.7V - 3.3V, VA = 2.7V, Code 80h

DD

= +25°C

= 50 µA for

W

DS11195C-page 2  2003 Microchip Technology Inc.

MCP41XXX/42XXX

DC CHARACTERISTICS: 50 kΩ VERSION

Electrical Characteristics: Unless otherwise indicated, V

+85°C). Typical specifications represent values for V

Parameters Sym Min Typ Max Units Conditions

Rheostat Mode

Nominal Resistance R 35 50 65 kΩ T

Rheostat Differential Non-Linearity R-DNL -1 ±1/4 +1 LSB Note 2

Rheostat Integral Non-Linearity R-INL -1 ±1/4 +1 LSB Note 2
Rheostat Tempco ∆R

Wiper Resistance R

Wiper Current I

/∆T — 800 — ppm/°C

AB

W

R

W

W

Nominal Resistance Match ∆R/R — 0.2 1 % MCP42050 only, P0 to P1;T

Potentiometer Divider

Resolution N 8 — — Bits

Monotonicity N 8 — — Bits

Differential Non-Linearity DNL -1 ±1/4 +1 LSB Note 3

Integral Non-Linearity INL -1 ±1/4 +1 LSB Note 3
Voltage Divider Tempco ∆V

Full-Scale Error V

Zero-Scale Error V

/∆T — 1 — ppm/°C Code 80h

W

WFSE

V

WFSE

WZSE

V

WZSE

Resistor Terminals

Voltage Range V

Capacitance (C

or CB) — 11 — pF f =1 MHz, Code = 80h, see Figure 2-30

A

Capacitance C

A,B,W

W

Dynamic Characteristics (All dynamic characteristics use V

Bandwidth -3dB BW — 280 — MHz V

Settling Time t

Resistor Noise Voltage e

Crosstalk C

Digital Inputs/Outputs (CS

, SCK, SI, SO) See Figure 2-12 for RS and SHDN pin operation.

Schmitt Trigger High-Level Input Voltage V

Schmitt Trigger Low-Level Input Voltage V

Hysteresis of Schmitt Trigger Inputs V

Low-Level Output Voltage V

High-Level Output Voltage V

Input Leakage Current I

Pin Capacitance (All inputs/outputs) C

S

NWB

T

IH

IL

HYS

OL

OH

LI

, C

IN

OUT

Power Requirements

Operating Voltage Range V

Supply Current, Active I

Supply Current, Static I

DD

— 340 500 µA VDD = 5.5V, CS = VSS, f

DDA

DDS

Power Supply Sensitivity PSS — 0.0015 0.0035 %/% V

PSS — 0.0015 0.0035 %/% V

Note 1: V

= VDD, no connection on wiper.

AB

2: Rheostat position non-linearity R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum

resistance wiper positions. R-DNL measures the relative step change from the ideal between successive tap positions. I
+3V or +5V for 50 kΩ version. See Figure 2-26 for test circuit.

3: INL and DNL are measured at V

specification limits of ±1 LSB max are specified monotonic operating conditions. See Figure 2-25 for test circuit.

4: Resistor terminals A,B and W have no restrictions on polarity with respect to each other. Full-scale and zero-scale error were measured

using Figure 2-25.

5: Measured at V
6: Supply current is independent of current through the potentiometers.

pin where the voltage on the adjacent VW pin is swinging full scale.

W

with the device configured in the voltage divider or potentiometer mode. VA = VDD and VB = 0V. DNL

W

= +2.7V to 5.5V, TA = -40°C to +85°C (TSSOP devices are only specified at +25°C and

DD

= 5V, VSS = 0V, VB = 0V, TA = +25°C.

DD

= +25°C (Note 1)

A

— 125 175 Ω VDD = 5.5V, IW = 1 mA, code 00h
— 175 250 Ω VDD = 2.7V, IW = 1 mA, code 00h

-1 — +1 mA

A

-1 -0.25 0 LSB Code FFh, VDD = 5V, see Figure 2-25

-1 -0.35 0 LSB Code FFh, VDD = 3V, see Figure 2-25

0 +0.25 +1 LSB Code 00h, VDD = 5V, see Figure 2-25

0 +0.35 +1 LSB Code 00h, VDD = 3V, see Figure 2-25

0—V

DD

Note 4

— 5.6 — pF f =1 MHz, Code = 80h, see Figure 2-30

= 5V)

DD

—8—µSV

= 0V, Measured at Code 80h,

B

Output Load = 30

= VDD,VB = 0V, ±1% Error Band, Transition

A

from Code 00h to Code 80h, Output Load = 30 pF

F

P

—20—nV/√Hz VA = Open, Code 80h, f =1 kHz

—-95—dBV

0.7V

— — 0.3V

——V

DD

DD

V

= VDD, VB = 0V (Note 5)

A

—0.05VDD—

— — 0.40 V IOL = 2.1 mA, VDD = 5V

VDD - 0.5 — — V IOH = -400 µA, VDD = 5V

-1 — +1 µA CS = VDD, VIN = VSS or VDD, includes VA SHDN=0

—10—pFVDD = 5.0V, TA = +25°C, fc = 1 MHz

2.7 — 5.5 V

= 10 MHz,

SO = Open, Code FFh (Note 6)

SCK

—0.01 1 µACS, SHDN, RS = VDD = 5.5V, SO = Open (Note 6)

= 4.5V - 5.5V, VA = 4.5V, Code 80h

DD

= 2.7V - 3.3V, VA = 2.7V, Code 80h

DD

= +25°C

W

= VDD/R for

 2003 Microchip Technology Inc. DS11195C-page 3

MCP41XXX/42XXX

DC CHARACTERISTICS: 100 kΩ VERSION

Electrical Characteristics: Unless otherwise indicated, V

+85°C). Typical specifications represent values for V

Parameters Sym Min Typ Max Units Conditions

Rheostat Mode

Nominal Resistance R 70 100 130 kΩ T

Rheostat Differential Non-Linearity R-DNL -1 ±1/4 +1 LSB Note 2

Rheostat Integral Non-Linearity R-INL -1 ±1/4 +1 LSB Note 2
Rheostat Tempco ∆R

Wiper Resistance R

Wiper Current I

/∆T — 800 — ppm/°C

AB

W

R

W

W

Nominal Resistance Match ∆R/R — 0.2 1 % MCP42010 only, P0 to P1;T

Potentiometer Divider

Resolution N 8 — — Bits

Monotonicity N 8 — — Bits

Differential Non-Linearity DNL -1 ±1/4 +1 LSB Note 3

Integral Non-Linearity INL -1 ±1/4 +1 LSB Note 3
Voltage Divider Tempco ∆V

Full-Scale Error V

Zero-Scale Error V

/∆T — 1 — ppm/°C Code 80h

W

WFSE

V

WFSE

WZSE

V

WZSE

Resistor Terminals

Voltage Range V

or CB) — 11 — pF f =1 MHz, Code = 80h, see Figure 2-30

Capacitance (C

A

Capacitance C

A,B,W

W

Dynamic Characteristics (All dynamic characteristics use V

Bandwidth -3dB BW — 145 — MHz V

Settling Time t

Resistor Noise Voltage e

Crosstalk C

Digital Inputs/Outputs (CS

, SCK, SI, SO) See Figure 2-12 for RS and SHDN pin operation.

Schmitt Trigger High-Level Input Voltage V

Schmitt Trigger Low-Level Input Voltage V

Hysteresis of Schmitt Trigger Inputs V

Low-Level Output Voltage V

High-Level Output Voltage V

Input Leakage Current I

Pin Capacitance (All inputs/outputs) C

S

NWB

T

IH

IL

HYS

OL

OH

LI

, C

IN

OUT

Power Requirements

Operating Voltage Range V

Supply Current, Active I

Supply Current, Static I

DD

— 340 500 µA VDD = 5.5V, CS = VSS, f

DDA

DDS

Power Supply Sensitivity PSS — 0.0015 0.0035 %/% V

PSS — 0.0015 0.0035 %/% V

Note 1: V

= VDD, no connection on wiper.

AB

2: Rheostat position non-linearity R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum

resistance wiper positions. R-DNL measures the relative step change from the ideal between successive tap positions. I

= 3V and IW = 400 µA for VDD = 5V for 10 kΩ version. See Figure 2-26 for test circuit.

V

DD

3: INL and DNL are measured at V

specification limits of ±1 LSB max are specified monotonic operating conditions. See Figure 2-25 for test circuit.

4: Resistor terminals A,B and W have no restrictions on polarity with respect to each other. Full-scale and zero-scale error were measured

using Figure 2-25.

5: Measured at V
6: Supply current is independent of current through the potentiometers.

pin where the voltage on the adjacent VW pin is swinging full-scale.

W

with the device configured in the voltage divider or potentiometer mode. VA = VDD and VB = 0V. DNL

W

= +2.7V to 5.5V, TA = -40°C to +85°C (TSSOP devices are only specified at +25°C and

DD

= 5V, VSS = 0V, VB = 0V, TA = +25°C.

DD

= +25°C (Note 1)

A

— 125 175 Ω VDD = 5.5V, IW = 1 mA, code 00h
— 175 250 Ω VDD = 2.7V, IW = 1 mA, code 00h

-1 — +1 mA

A

-1 -0.25 0 LSB Code FFh, VDD = 5V, see Figure 2-25

-1 -0.35 0 LSB Code FFh, VDD = 3V, see Figure 2-25

0 +0.25 +1 LSB Code 00h, VDD = 5V, see Figure 2-25

0 +0.35 +1 LSB Code 00h, VDD = 3V, see Figure 2-25

0—V

DD

Note 4

— 5.6 — pF f =1 MHz, Code = 80h, see Figure 2-30

= 5V.)

DD

—18—µSV

= 0V, Measured at Code 80h,

B

Output Load = 30

= VDD,VB = 0V, ±1% Error Band, Transition

A

from Code 00h to Code 80h, Output Load = 30 pF

F

P

—29—nV/√Hz VA = Open, Code 80h, f =1 kHz

—-95—dBV

0.7V

— — 0.3V

——V

DD

DD

V

= VDD, VB = 0V (Note 5)

A

—0.05VDD—

— — 0.40 V IOL = 2.1 mA, VDD = 5V

VDD - 0.5 — — V IOH = -400 µA, VDD = 5V

-1 — +1 µA CS = VDD, VIN = VSS or VDD, includes VA SHDN=0

—10—pFVDD = 5.0V, TA = +25°C, fc = 1 MHz

2.7 — 5.5 V

= 10 MHz,

SO = Open, Code FFh (Note 6)

SCK

—0.01 1 µACS, SHDN, RS = VDD = 5.5V, SO = Open (Note 6)

= 4.5V - 5.5V, VA = 4.5V, Code 80h

DD

= 2.7V - 3.3V, VA = 2.7V, Code 80h

DD

= +25°C

W

= 50 µA for

DS11195C-page 4  2003 Microchip Technology Inc.

MCP41XXX/42XXX

Absolute Maximum Ratings †

VDD...................................................................................7.0V

All inputs and outputs w.r.t. V

............... -0.6V to VDD +1.0V

SS

Storage temperature .....................................-60°C to +150°C

Ambient temp. with power applied ................-60°C to +125°C

ESD protection on all pins ..................................................≥ 2kV

† Notice:

ings” may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at
those or any other conditions above those indicated in the
operational listings of this specification is not implied. Expo­sure to maximum rating conditions for extended periods may
affect device reliability.

AC TIMING CHARACTERISTICS

Electrical Characteristics: Unless otherwise indicated, V

Parameter Sym Min. Typ. Max. Units Conditions

Clock Frequency F

Clock High Time t

Clock Low Time t

CS

Fall to First Rising CLK Edge t

Data Input Setup Time t

Data Input Hold Time t

SCK Fall to SO Valid Propagation Delay t

SCK Rise to CS

SCK Rise to CS

CS

Rise to CLK Rise Hold t

CS

High Time t

Reset Pulse Width t

RS

Rising to CS Falling Delay Time t

CS

rising to RS or SHDN falling delay time t

CS

low time t

Shutdown Pulse Width t

Note 1: When using the device in the daisy-chain configuration, maximum clock frequency is determined by a combination of propagation delay

Rise Hold Time t

Fall Delay t

time (t

) and data input setup time (tSU). Max. clock frequency is therefore ~ 5.8 MHz based on SCK rise and fall times of 5 ns, tHI =

DO

40 ns, t

2: Applies only to the MCP42XXX devices.
3: Applies only when using hardware pins to exit software shutdown mode, MCP42XXX only.

= 80 ns and t

DO

SU

= 40 ns.

= +2.7V to 5.5V, TA = -40°C to +85°C.

DD

CLK

HI

LO

CSSR

SU

HD

DO

CHS

CS0

CS1

CSH

RS

RSCS

SE

CSL

SH

——10MHzVDD = 5V (Note 1)

40 — — ns

40 — — ns

40 — — ns

40 — — ns

10 — — ns

30 — — ns

10 — — ns

100 — — ns

40 — — ns

150 — — ns Note 2

150 — — ns Note 2

40 — — ns Note 3

100 — — ns Note 3

150 — — ns Note 3

Stresses above those listed under “maximum rat-

—80 nsC

= 30 pF (Note 2)

L

 2003 Microchip Technology Inc. DS11195C-page 5

MCP41XXX/42XXX

t

CSH

CS

t

CSSR

t

CSO

SCK

t

SU

t

HD

V

SI

SO

OUT

msb in

(First 16 bits out are always zeros)

FIGURE 1-1: Detailed Serial interface Timing.

Wiper position is changed to
mid-scale (80h) if RS
low for 150 ns

is held

CS

RS

t

RS

1/F

CLK

t

t

HI

LO

Code 80h is latched
on rising edge of RS

t

RSCS

t

CHS

t

DO

±1% Error Band

t

CS1

t

±1%

S

t

S

V

OUT

±1% Error Band

FIGURE 1-2: Reset Timing.

t

CSL

CS

t

SE

RS

t

SE

SHDN

FIGURE 1-3: Software Shutdown Exit Timing.

t

t

±1%

RS

SH

DS11195C-page 6  2003 Microchip Technology Inc.

MCP41XXX/42XXX

2.0 TYPICAL PERFORMANCE CURVES

Note: The graphs and tables provided following this note are a statistical summary based on a limited number of

samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.

Note: Unless otherwise indicated, curve represents 10 kΩ, 50 kΩ and 100 kΩ devices, V

= 0V.

V

B

= 5V, VSS = 0V, TA = +25°C,

DD

1

)

Ω

0.8

0.6

0.4

0.2

Normalized Resistance (

0

R

WB

0 32 64 96 128 160 192 224 256

VDD = +3V to +5V

Code (Decimal)

R

WA

FIGURE 2-1: Normalized Wiper to End
Terminal Resistance vs. Code.

0.5

0.4

0.3

0.2

0.1
0

-0.1

-0.2

-0.3

-0.4

Potentiometer INL Error (LSB)

-0.5

0 32 64 96 128 160 192 224 256

Code (Decimal)

TA = -40°C to +85°C
Refer to Figure 2-25

14

)

12

Ω

10

8

6

4

Nominal Resistance (k

2

MCP41010, MCP42010 (10 kΩ potentiometers)

0

-40 -25 -10 5 20 35 50 65 80 95 110 125

Temperature (°C)

R

AB

R

WB

Code = 80h

FIGURE 2-4: Nominal Resistance 10 kΩ
vs. Temperature.

70

)

Ω

60

50

40

30

20

10

Nominal Resistance (k

MCP41050, MCP42050 (50 kΩ potenti ometers)

0

-40 -25 -10 5 20 35 50 65 80 95 110 125

Temperature ( °C)

R

AB

R

WB

Code = 80h

FIGURE 2-2: Potentiometer INL Error vs.
Code.

70

60

50

40

30

20

(ppm / °C)

10

0

Potentiometer Mode TempCo

-10
0 32 64 96 128 160 192 224 256

Code (Decimal)

TA = -40°C to +85°C
V

= 3V

A

FIGURE 2-3: Potentiometer Mode
Tempco vs. Code.

FIGURE 2-5: Nominal Resistance 50 kΩ
vs. Temperature.

140

)

Ω

120

100

80

60

40

20

Nominal Resistance (k

MCP41100, MCP42100 (100 kΩ potenti ometers)

0

-40 -25 -10 5 20 35 50 65 80 95 110 125

Temperature ( °C)

R

R

WB

Code = 80h

AB

FIGURE 2-6: Nominal Resistance 100 kΩ
vs. Temperature.

 2003 Microchip Technology Inc. DS11195C-page 7

MCP41XXX/42XXX

Note: Unless otherwise indicated, curve represents 10 kΩ, 50 kΩ and 100 kΩ devices, V

VB = 0V.

0.5

0.4

0.3

0.2

0.1
0

-0.1

-0.2

-0.3

Rheostat INL Error (LSB)

-0.4

-0.5
0 32 64 96 128 160 192 224 256

TA = -40°C

Code (Decimal)

Refer to Figure 2-27

TA = +85°C

TA = +25°C

FIGURE 2-7: Rheostat INL Error vs.
Code.

3000

2500

2000

1500

1000

(ppm / °C)

500

Rheostat Mode TempCo

0

0 32 64 96 128 160 192 224 256

Code (Decimal)

TA = -40°C to +85°C,
V

= no connect,

A

R

measured

WB

280

230

180

130

80

Active Supply Current (µA)

30

-40 -25 -10 5 20 35 50 65 80 95 110 125

FIGURE 2-10: Active Supply Current vs.
Temperature.

1000

A - V

= 5.5V, Code = AAh

900

800

700

600

500

400

300

200

Active Supply Current (mA)

100

DD

B - V

= 3.3V, Code = AAh

DD

C - V

= 5.5V, Code = FFh

DD

D - V

= 3.3V, Code = FFh

DD

0

1k 10k 100k 1M 10M

= 5V, VSS = 0V, TA = +25°C,

DD

VDD = 5V

VDD = 3V

F

= 3 MHz

CLK

Code = FFh

Temperature (°C)

Clock Frequency (Hz)

B

A

C

D

FIGURE 2-8: Rheostat Mode Tempco vs.
Code.

1000

100

10

Static Current (nA)

1

-40 -25 -10 5 20 35 50 65 80 95 11012

Temperature (°C)

5

FIGURE 2-9: Static Current vs.
Temperature.

FIGURE 2-11: Active Supply Current vs.
Clock Frequency.

1

0

-1

-2

-3

-4

-5

-6

-7

RS & SHDN Sink Current (mA)

0246

RS & SHDN Pin Voltage (V)

VDD = 5.5V

FIGURE 2-12: Reset & Shutdown Pins
Current vs. Voltage.

DS11195C-page 8  2003 Microchip Technology Inc.

MCP41XXX/42XXX

M

Note: Unless otherwise indicated, curve represents 10 kΩ, 50 kΩ and 100 kΩ devices, V

VB = 0V.

180

MCP41010,MCP42010

160

Code = 00h,
Sample Size = 400

140

120

100

80

60

40

Number of Occurrences

20

0

47 48 49 50 51 52 53 54 55 56 57 58 59

Wiper Resistance (Ω)

FIGURE 2-13: 10 kΩ Device Wiper

V

OUT

FFh

00h

CS

FIGURE 2-16: Full-Scale Settling Time.

Resistance Histogram.

140

120

100

80

60

40

20

Number of Occurrences

0

115 117 119 121 123 125 127 129 131 133

Wiper Resistance (Ω)

MCP41050, MCP41100,
MCP42050, MCP42100
Code = 00h,
Sample Size = 796

V

CS

OUT

= 5V, VSS = 0V, TA = +25°C,

DD

CL = 27 pF

CL = 27 pF

Code = 80h

FIGURE 2-14: 50 kΩ, 100 kΩ Device Wiper
Resistance Histogram.

C

= 17 pF

L

V

OUT

Code = 7Fh Code = 80h

CS

FIGURE 2-15: One Position Settling Time.

FIGURE 2-17: Digital Feed through vs.

Time.

6

0

-6

-12

-18

-24

-30

Gain (dB)

-36

-42

-48

CL = 30pF, Refer to Figure 2-29

-54

MCP41010, MCP42010 (10kΩ potentiometers)

-60
100 1k 10k 100k 1M 10

Code = FFh

Code = 80h

Code = 40h

Code = 20h

Code = 10h

Code = 08h

Code = 04h

Code = 02h

Code = 01h

Frequency (Hz)

FIGURE 2-18: Gain vs. Frequency for
10 kΩ Potentiometer.

 2003 Microchip Technology Inc. DS11195C-page 9

MCP41XXX/42XXX

M

M

Note: Unless otherwise indicated, curve represents 10 kΩ, 50 kΩ and 100 kΩ devices, V

VB = 0V.

6

0

-6

-12

-18

-24

-30

Gain (dB)

-36

-42

-48

CL = 30pF, Refer to Figure 2-29

-54

MCP41050, MCP42050 (50kΩ potentiometers)

-60
100 1k 10k 100k 1M 10M

Code = FFh

Code = 80h

Code = 40h

Code = 20h

Code = 10h

Code = 08h

Code = 04h

Code = 02h

Code = 01h

Frequency (Hz)

FIGURE 2-19: Gain vs. Frequency for
50kΩ Potentiometer.

6

0

-6

-12

-18

-24

-30

Gain (dB)

-36

-42

-48

CL = 30pF, Refer to Figure 2-29

-54

MCP41100, MCP42100 (100kΩ potentiometers)

-60

100 1k

Code = FFh

Code = 80h

Code = 40h

Code = 20h

Code = 10h

Code = 08h

Code = 04h

Code = 02h

Code = 01h

10k 100k 1M

Frequency (Hz)

40

35

10 kΩ Potentiometer

30

25

20

15

PSRR (dB)

10

100 kΩ Potentiometer

5

0

1k 10k 100k 1M 10

FIGURE 2-22: Power Supply Rejection
Ratio vs. Frequency.

700

600

)

Ω

500

400

300

200

Wiper Resistance (

100

0

012345

Terminal B Voltage (V)

= 5V, VSS = 0V, TA = +25°C,

DD

VDD = 4.5V to 5.5V,
Code = 80h,

= 27 pF,

C

L

V

= 4V

A

Refer to Figure 2-28

50 kΩ Potentiometer

Frequency (Hz)

MCP41010, MCP42010
Iw = 1 mA, Code = 00h,

VDD = 2.7V

Refer to Figure 2-27

VDD = 5V

FIGURE 2-20: Gain vs. Frequency for
100kΩ Potentiometer.

0

-6

-12

145 kHz

279 kHz

-18

Gain (dB)

-24

-30

CL = 30 pF, Code = 80h
Refer to Figure 2-29

-36

1k 10k 100k 1M 10

Frequency (Hz)

1.06 MHz

10 kΩ

50 kΩ

100 kΩ

FIGURE 2-21: -3 dB Bandwidths.

FIGURE 2-23: 10 kΩ Wiper Resistance vs.

Voltage.

450

400

)

Ω

350

300

VDD = 2.7V

250

200

150

100

Wiper Resistance (

50

0

012345

Terminal B Voltage (V)

Code = 00h
Refer to Figure 2-27

VDD = 5V

FIGURE 2-24: 50 kΩ & 100 kΩ Wiper
Resistance vs. Voltage.

DS11195C-page 10  2003 Microchip Technology Inc.

MCP41XXX/42XXX

2.1 Parametric Test Circuits

V+ = V

DD

1LSB = V+/256

A

B

DUT

A

B
DUT

W

W

+

V

*

MEAS

-

I

W

+

-

V

MEAS

*

V+

*Assume infinite input impedance

FIGURE 2-25: Potentiometer Divider Non­Linearity Error Test Circuit (DNL, INL).

No Connection

*Assume infinite input impedance

FIGURE 2-26: Resistor Position Non­Linearity Error Test Circuit (Rheostat operation
DNL, INL).

V

A

V

A

V+

V+ = VDD ± 10%

PSRR (dB) = 20LOG

PSS (%/%) = ∆V

*Assume infinite input impedance

DD

∆V

B

DUT

DD

MEAS

∆V

(

W

∆V

DD

MEAS

+

V

MEAS

-

)

FIGURE 2-28: Power Supply Sensitivity
Test Circuit (PSS, PSRR).

V

OFFSET

GND

A

IN

~

2.5V DC

W

DUT

B

+

-

+5V

V

*

OUT

Rsw = 0.1V

Isw

Code = 00h

+

0.1V

-

DUT

A

W

I

V

SS

SW

= 0 to V

DD

B

FIGURE 2-27: Wiper Resistance Test
Circuit.

FIGURE 2-29: Gain vs. Frequency Test
Circuit.

DUT

A

V

IN

~

2.5V DC

Offset

+5V

-

+

B

V

MCP601

OUT

FIGURE 2-30: Capacitance Test Circuit.

 2003 Microchip Technology Inc. DS11195C-page 11

MCP41XXX/42XXX

3.0 PIN DESCRIPTIONS

3.1 PA0, PA1

Potentiometer Terminal A Connection.

3.2 PB0, PB1

Potentiometer Terminal B Connection.

3.3 PW0, PW1

Potentiometer Wiper Connection.

3.4 Chip Select (CS)

This is the SPI port chip select pin and is used to exe­cute a new command after it has been loaded into the
shift register. This pin has a Schmitt Trigger input.

3.5 Serial Clock (SCK)

This is the SPI port clock pin and is used to clock-in
new register data. Data is clocked into the SI pin on the
rising edge of the clock and out the SO pin on the falling
edge of the clock. This pin is gated to the CS
the device will not draw any more current if the SCK pin
is toggling when the CS pin is high). This pin has a
Schmitt Trigger input.

pin (i.e.,

3.9 Shutdown (SHDN)
(MCP42XXX devices only)

The Shutdown pin has a Schmitt Trigger input. Pulling
this pin low will put the device in a power-saving mode
where A terminal is opened and the B and W terminals
are connected for all potentiometers. This pin should
not be toggled low when the CS
minimize power consumption, this pin has an active
pull-up circuit. The performance of this circuit is shown
in Figure 2-12. This pin will draw negligible current at
logic level ‘0’ and logic level ‘1’. Do not leave this pin
floating.

TABLE 3-1: MCP41XXX Pins

Pin # Name Function

SS

DD

Chip Select

Ground

Power

1CS

2 SCK Serial Clock

3 SI Serial Data Input

4V

5 PA0 Terminal A Connection For Pot 0

6 PW0 Wiper Connection For Pot 0

7 PB0 Terminal B Connection For Pot 0

8V

pin is low. In order to

3.6 Serial Data Input (SI)

This is the SPI port serial data input pin. The command
and data bytes are clocked into the shift register using
this pin. This pin is gated to the CS pin (i.e., the device
will not draw any more current if the SI pin is toggling
when the CS
input.

pin is high). This pin has a Schmitt Trigger

3.7 Serial Data Output (SO)
(MCP42XXX devices only)

This is the SPI port serial data output pin used for
daisy-chaining more than one device. Data is clocked
out of the SO pin on the falling edge of clock. This is a
push-pull output and does not go to a high-impedance
state when CS
is high.

is high. It will drive a logic-low when CS

3.8 Reset (RS)
(MCP42XXX devices only)

The Reset pin will set all potentiometers to mid-scale
(Code 80h) if this pin is brought low for at least 150 ns.
This pin should not be toggled low when the CS
low. It is possible to toggle this pin when the SHDN
is low. In order to minimize power consumption, this pin
has an active pull-up circuit. The performance of this
circuit is shown in Figure 2-12. This pin will draw negli­gible current at logic level ‘0’ and logic level ‘1’. Do not
leave this pin floating.

pin is

pin

TABLE 3-2: MCP42XXX Pins

Pin # Name Function

1CSChip Select

2 SCK Serial Clock

3 SI Serial Data Input

4V

5 PB1 Terminal B Connection For Pot 1

6 PW1 Wiper Connection For Pot 1

7 PA1 Terminal A Connection For Pot 1

8 PA0 Terminal A Connection For Pot 0

9 PW0 Wiper Connection For Pot 0

10 PB0 Terminal B Connection For Pot 0

11 R S

12 SHDN Shutdown Input

13 SO Data Out for Daisy-Chaining

14 V

SS

DD

Ground

Reset Input

Power

DS11195C-page 12  2003 Microchip Technology Inc.

4.0 APPLICATIONS INFORMATION

The MCP41XXX/42XXX devices are 256 position
single and dual digital potentiometers that can be used
in place of standard mechanical pots. Resistance val­ues of 10 kΩ, 50 kΩ and 100 kΩ are available. As
shown in Figure 4-1, each potentiometer is made up of
a variable resistor and an 8-bit (256 position) data reg­ister that determines the wiper position. There is a
nominal wiper resistance of 52Ω for the 10 kΩ version,
125Ω for the 50 kΩ and 100 kΩ versions. For the dual
devices, the channel-to-channel matching variation is
less than 1%. The resistance between the wiper and
either of the resistor endpoints varies linearly according
to the value stored in the data register. Code 00h
effectively connects the wiper to the B terminal. At

PA0 PB0

PW0

MCP41XXX/42XXX

power-up, all data registers will automatically be loaded
with the mid-scale value (80h). The serial interface pro­vides the means for loading data into the shift register,
which is then transferred to the data registers. The
serial interface also provides the means to place indi­vidual potentiometers in the shutdown mode for maxi­mum power savings. The SHDN
to put all potentiometers in shutdown mode and the RS
pin is provided to set all potentiometers to mid-scale
(80h).

PA1 PB1

PW1

pin can also be used

RDAC2

Data Register 1

D7

D0

SOSI

D0

SHDN

RS

CS

SCK

RDAC1

Data Register 0

D7

Decode

Logic

16-bit Shift Register

D0

D7

FIGURE 4-1: Block diagram showing the MCP42XXX dual digital potentiometer. Data register 0 and
data register 1 are 8-bit registers allowing 256 positions for each wiper. Standard SPI pins are used with
the addition of the Shutdown (SHDN

) and Reset (RS) pins. As shown, reset affects the data register and
wipers, bringing them to mid-scale. Shutdown disconnects the A terminal and connects the wiper to B,
without changing the state of the data registers.

When laying out the circuit for your digital potentiome­ter, bypass capacitors should be used. These capaci­tors should be placed as close as possible to the device
pin. A bypass capacitor value of 0.1 µF is recom­mended. Digital and analog traces should be separated
as much as possible on the board, with no traces run­ning underneath the device or the bypass capacitor.
Extra precautions should be taken to keep traces with
high-frequency signals (such as clock lines) as far as
possible from analog traces. Use of an analog ground
plane is recommended in order to keep the ground
potential the same for all devices on the board.

µC

V

DD

Data Lines

0.1 uF

V

DD

B

W

MCP4XXXX

A

To Application

Circuit

0.1 uF

 2003 Microchip Technology Inc. DS11195C-page 13

MCP41XXX/42XXX

4.1 Modes of Operation

Digital potentiometer applications can be divided into
two categories: rheostat mode and potentiometer, or
voltage divider, mode.

4.1.1 RHEOSTAT MODE

In the rheostat mode, the potentiometer is used as a
two-terminal resistive element. The unused terminal
should be tied to the wiper, as shown in Figure 4-2.
Note that reversing the polarity of the A and B terminals
will not affect operation.

A

W

B

MCP4XXXX

FIGURE 4-2: Two-terminal or rheostat
configuration for the digital potentiometer. Acting
as a resistive element in the circuit, resistance is
controlled by changing the wiper setting.

Using the device in this mode allows control of the total
resistance between the two nodes. The total measured
resistance would be the least at code 00h, where the
wiper is tied to the B terminal. The resistance at this
code is equal to the wiper resistance, typically 52Ω for
the 10 kΩ MCP4X010 devices, 125Ω for the 50 kΩ
(MCP4X050), and 100 kΩ (MCP4X100) devices. For
the 10 kΩ device, the LSB size would be 39.0625Ω
(assuming 10 kΩ total resistance). The resistance
would then increase with this LSB size until the total
measured resistance at code FFh would be 9985.94Ω.
The wiper will never directly connect to the A terminal
of the resistor stack.

In the 00h state, the total resistance is the wiper resis­tance. To avoid damage to the internal wiper circuitry in
this configuration, care should be taken to ensure the
current flow never exceeds 1 mA.

For dual devices, the variation of channel-to-channel
matching of the total resistance from A to B is less than
1%. The device-to-device matching, however, can vary
up to 30%. In the rheostat mode, the resistance has a
positive temperature coefficient. The change in wiper­to-end terminal resistance over temperature is shown
in Figure 2-8. The most variation over temperature will
occur in the first 6% of codes (code 00h to 0Fh) due to
the wiper resistance coefficient affecting the total resis­tance. The remaining codes are dominated by the total
resistance tempco R

, typically 800 ppm/°C.

AB

Resistor

4.1.2 POTENTIOMETER MODE

In the potentiometer mode, all three terminals of the
device are tied to different nodes in the circuit. This
allows the potentiometer to output a voltage propor­tional to the input voltage. This mode is sometimes
called voltage divider mode. The potentiometer is used
to provide a variable voltage by adjusting the wiper
position between the two endpoints as shown in
Figure 4-3. Note that reversing the polarity of the A and
B terminals will not affect operation.

V

1

A

V

W

B

MCP4XXXX

2

FIGURE 4-3: Three terminal or voltage
divider mode.

In this configuration, the ratio of the internal resistance
defines the temperature coefficient of the device. The
resistor matching of the R
performs with a typical temperature coefficient of
1 ppm/°C (measured at code 80h). At lower codes, the
wiper resistance temperature coefficient will dominate.
Figure 2-3 shows the effect of the wiper. Above the
lower codes, this figure shows that 70% of the states
will typically have a temperature coefficient of less than
5 ppm/°C. 30% of the states will typically have a
ppm/°C of less than 1.

resistor to the RAB resistor

WB

DS11195C-page 14  2003 Microchip Technology Inc.

MCP41XXX/42XXX

4.2 Typical Applications

4.2.1 PROGRAMMABLE SINGLE-ENDED

AMPLIFIERS

Potentiometers are often used to adjust system refer­ence levels or gain. Programmable gain circuits using
digital potentiometers can be realized in a number of
different ways. An example of a single-supply, inverting
gain amplifier is shown in Figure 4-4. Due to the high
input impedance of the amplifier, the wiper resistance
is not included in the transfer function. For a single-sup­ply, non-inverting gain configuration, the circuit in
Figure 4-5 can be used.

.

MCP41010

B

V

IN

FIGURE 4-4: Single-supply,
programmable, inverting gain amplifier using a
digital potentiometer.

A

W

-IN

REF

OUT

+IN

V

V

Where:

RAB256 D

R

---------------------------------------= R

A

R

AB

Total Resistance of pot=

DnWiper setting forDn0 to 255==

-

MCP606

+

R

B



V

-------

IN



R

A

–()

256

V

DD

V

OUT

V

SS

R

B



V

1

+–=

REF

n

-------+



R

A

RABD

n

------------------=

B

256

In order for these circuits to work properly, care must be
taken in a few areas. For linear operation, the analog
input and output signals must be in the range of VSS to

for the potentiometer and input and output rails of

V

DD

the op-amp. The circuit in Figure 4-4 requires a virtual
ground or reference input to the non-inverting input of
the amplifier. Refer to Application Note 682, “Using

Single-Supply Operational Amplifiers in Embedded
Systems” (DS00682), for more details. At power-up or

reset (RS)

, the resistance is set to mid-scale, with R
and RB matching. Based on the transfer function for the
circuit, the gain is -1 V/V. As the code is increased and
the wiper moves towards the A terminal, the gain
increases. Conversely, when the wiper is moved
towards the B terminal, the gain decreases. Figure 4-6
shows this relationship. Notice the pseudo-logarithmic
gain around decimal code 128. As the wiper
approaches either terminal, the step size in the gain
calculation increases dramatically. Due to the
mismatched ratio of R

and RB at the extreme high and

A

low codes, small increments in wiper position can
dramatically affect the gain. As shown in Figure 4-3,
recommended gains lie between 0.1 and 10 V/V.

10

1

Absolute Gain (V/V)

0.1

0 64 128 192 256

Decimal code (0-255)

FIGURE 4-6: Gain vs. Code for inverting
and differential amplifier circuits.

A

V

DD

V

IN

+IN

-IN

W

RBRA

+

MCP606

-

V

SS

V

OUT

4.2.2 PROGRAMMABLE DIFFERENTIAL

AMPLIFIER

An example of a differential input amplifier using digital
potentiometers is shown in Figure 4-7. For the transfer
function to hold, both pots must be programmed to the
same code. The resistor-matching from channel-to­channel within a dual device can be used as an advan­tage in this circuit. This circuit will also show stable

Where:

RAB256 D

R

---------------------------------------= R

A

R

D

AB

n

Total Resistance of pot=

Wiper setting forDn0 to 255==

MCP41010

–()

n

256

V

OUTVIN

RABD

------------------=

B

256



1

=



n

R

B

-------+

R

A

operation over temperature due to the low potentiome­ter temperature coefficient. Figure 4-6 also shows the
relationship between gain and code for this circuit. As
the wiper approaches either terminal, the step size in
the gain calculation increases dramatically. This circuit
is recommended for gains between 0.1 and 10 V/V.

FIGURE 4-5: Single-supply,
programmable, non-inverting gain amplifier.

 2003 Microchip Technology Inc. DS11195C-page 15

MCP41XXX/42XXX

1/2

MCP42010

V

B

AB

(SIG -)

V

A

(SIG +)

A

1/2

B

MCP42010

V

REF

-IN

+IN

+

MCP601

-

V

V

V

SS

OUT

DD

–()

VAV

B

V

R

-------=

R

OUT

B

A

Where:

RAB256 D

R

---------------------------------------= R

A

R

D

AB

n

Total Resistance of pot=

Wiper setting forDn0 to 255==

–()

n

256

RABD

n

------------------=

B

256

NOTE: Potentiometer values must be equal

FIGURE 4-7: Single Supply
programmable differential amplifier using digital
potentiometers.

4.2.3 PROGRAMMABLE OFFSET TRIM

For applications requiring only a programmable voltage
reference, the circuit in Figure 4-8 can be used. This
circuit shows the device used in the potentiometer
mode along with two resistors and a buffered output.
This creates a circuit with a linear relationship between
voltage-out and programmed code. Resistors R
R2 can be used to increase or decrease the output volt­age step size. The potentiometer in this mode is stable
over temperature. The operation of this circuit over
temperature is shown in Figure 2-3. The worst perfor­mance over temperature will occur at the lower codes
due to the dominating wiper resistance. R

1

also be used to affect the boundary voltages, thereby
eliminating the use of these lower codes.

V

R

MCP41010

R

2

DD

1

-IN

A

+IN

B

0.1 uF

V

SS

V

-

MCP606

+

V

DD

OUT

SS

and

1

and R2 can

4.3 Calculating Resistances

When programming the digital potentiometer settings,
the following equations can be used to calculate the
resistances. Programming code 00h effectively brings
the wiper to the B terminal, leaving only the wiper resis­tance. Programming higher codes will bring the wiper
closer to the A terminal of the potentiometer. The equa­tions in Figure 4-9 can be used to calculate the terminal
resistances. Figure 4-10 shows an example calculation
using a 10 kΩ potentiometer.

PA

PW

PB

()256 D

R

()

RWAD

R

Where:
PA is the A terminal
PB is the B terminal
PW is the wiper terminal

is resistance between Terminal A and wiper

R

WA

is resistance between Terminal B and Wiper

R

WB

is overall resistance for pot (10 kΩ, 50 kΩ or 100 kΩ)

R

AB

is wiper resistance

R

W

is 8-bit value in data register for pot number n

D

n

()

WBDn

n

AB

-------------------------------------------- RW+=

()Dn()

R

AB

---------------------------- R

256

FIGURE 4-9: Potentiometer resistances
are a function of code. It should be noted that,
when using these equations for most feedback
amplifier circuits (see Figure 4-4 and Figure 4-5),
the wiper resistance can be omitted due to the
high impedance input of the amplifier.

PA

10 kΩ

R

WADn

R

WA

R

WA

R

R

WB

R

WB

WBDn

()

C0h()
C0h()2552

()

C0h()
C0h()7552

PW

PB

()256 D

R

AB

-------------------------------------------- R

256

Ω

()256 192–()

10k

--------------------------------------------------- 52

Ω

=

()Dn()

R

AB

---------------------------- R

256

Ω

()192()

10k

----------------------------------- 52

256

Ω

=

–()

n

256

+=

W

Example:
R = 10 kΩ
Code = C0h = 192d

–()

n

+=

W

256

+=

+=

W

Ω

+=

Ω

FIGURE 4-8: By changing the values of
R

and R2, the voltage output resolution of this

1

programmable voltage reference circuit is
affected.

DS11195C-page 16  2003 Microchip Technology Inc.

Note: All values shown are typical and

actual results will vary.

FIGURE 4-10: Example Resistance
calculations.

MCP41XXX/42XXX

5.0 SERIAL INTERFACE

Communications from the controller to the
MCP41XXX/42XXX digital potentiometers is accom­plished using the SPI serial interface. This interface
allows three commands:

1. Write a new value to the potentiometer data
register(s).

2. Cause a channel to enter low power shutdown
mode.

NOP

3.

Executing any command is accomplished by setting
CS
by a data byte into the 16-bit shift register. The com­mand is executed when CS
in on the rising edge of clock and out the SO pin on the
falling edge of the clock (see Figure 5-1). The device
will track the number of clocks (rising edges) while CS
is low and will abort all commands if the number of
clocks is not a multiple of 16.

5.1 Command Byte

The first byte sent is always the command byte, fol­lowed by the data byte. The command byte contains
two command select bits and two potentiometer select
bits. Unused bits are ‘don’t care’ bits. The command
select bits are summarized in Figure 5-2. The com­mand select bits C1 and C0 (bits 4:5) of the command
byte determine which command will be executed. If the
command bits are both 0’s or 1’s, then a NOP com­mand will be executed once all 16 bits have been
loaded. This command is useful when using the daisy­chain configuration. When the command bits are 0,1, a
write command will be executed with the 8 bits sent in
the data byte. The data will be written to the potentiom­eter(s) determined by the potentiometer select bits. If
the command bits are 1,0, then a shutdown command
will be executed on the potentiometers determined by
the potentiometer select bits.

For the MCP42XXX devices, the potentiometer select
bits P1 and P0 (bits 0:1) determine which potentiome­ters are to be acted upon by the command. A corre­sponding ‘1’ in the position signifies that the command
for that potentiometer will get executed, while a ‘0’ sig­nifies that the command will not effect that
potentiometer (see Figure 5-2).

5.2 Writing Data Into Data Registers

When new data is written into one or more of the poten­tiometer data registers, the write command is followed
by the data byte for the new value. The command
select bits C1, C0 are set to 0,1. The potentiometer
selection bits P1 and P0 allow new values to be written
to potentiometer 0, potentiometer 1 (or both) with a sin­gle command. A ‘1’ for either P1 or P0 will cause the
data to be written to the respective data register and a
‘0’ for P1 or P0 will cause no change. See Figure 5-2
for the command format summary.

(No Operation) command.

low and then clocking-in a command byte followed

is raised. Data is clocked-

5.3 Using The Shutdown Command

The shutdown command allows the user to put the
application circuit into a power-saving mode. In this
mode, the A terminal is open-circuited and the B and W
terminals are shorted together. The command select
bits C1, C0 are set to 1,0. The potentiometer selection
bits P1 and P0 allow each potentiometer to be shut­down independently. If either P1 or P0 are high, the
respective potentiometer will enter shutdown mode. A
‘0’ for P1 or P0 will have no effect. The eight data bits
following the command byte still need to be transmitted
for the shutdown command, but they are ‘don’t care’
bits. See Figure 5-2 for command format summary.
Once a particular potentiometer has entered the shut­down mode, it will remain in this mode until:

• A new value is written to the potentiometer data
register, provided that the SHDN
device will remain in the shutdown mode until the
rising edge of the CS
the device will come out of shutdown mode and
the new value will be written to the data regis­ter(s). If the SHDN
is received, the registers will still be set to the new
value, but the device will remain in shutdown
mode. This scenario assumes that a valid com­mand was received. If an invalid command was
received, the command will be ignored and the
device will remain in the shutdown mode.

It is also possible to use the hardware shutdown pin
and reset pin to remove a device from software shut­down. To do this, a low pulse on the chip select line
must first be sent. For multiple devices, sharing a single

or RESET line allows you to pick an individual

SHDN
device on that chain to remove from software shutdown
mode. See Figure 1-3 for timing. With a preceding chip
select pulse, either of these situations will also remove
a device from software shutdown:

• A falling edge is seen on the RS
for at least 150 ns, provided that the SHDN pin is
high. If the SHDN pin is low, the registers will still
be set to mid-scale, but the device will remain in
shutdown mode. This condition assumes that CS
is high, as bringing the RS pin low while CS is low
is an invalid state and results are indeterminate.

• A rising edge on the SHDN
low for at least 100 ns, provided that the CS
high. Toggling the SHDN pin low while CS is low
is an invalid state and results are indeterminate.

• The device is powered-down and back up.

Note: The hardware SHDN

the device in shutdown regardless of
whether a potentiometer has already been
put in the shutdown mode using the
software command.

is detected, at which time

pin is low when the new value

pin is high. The

pin and held low

pin is seen after being

pin is

pin will always put

 2003 Microchip Technology Inc. DS11195C-page 17

MCP41XXX/42XXX

CS

SCK

SO

Data is always latched
in on the rising edge
of SCK.

†

2345678 9101

COMMAND Byte Data Byte

Don’t

Care

Command

Bits

X

X

SI

‡

There must always be multiples of 16 clocks while CS is low or commands will abort.

†

The serial data out pin (SO) is only available on the MCP42XXX device.

‡

P1 is a ‘don’t care’ bit for the MCP41XXX.

*

C1

Don’t

Channel

Bits

Care

X

C0

First 16 bits shifted out will always be zeros

Bits

Select

Bits

P1*

X

P0

Data is always clocked out
of the SO pin after the
falling edge of SCK.

11 12 13 14 15 16

New Register Data

D7 D6 D5 D4 D3 D2 D1 D0

Data Registers are
loaded on rising
edge of CS. Shift
register is loaded
with zeros at this time.

SO pin will always
drive low when CS
goes high.

X

FIGURE 5-1: Timing Diagram for Writing Instructions or Data to a Digital Potentiometer.

COMMAND BYTE

P0P1*XXXXC1C0

Command

Selection

Bits

Potentiometer

Selection

Bits

C1 C0 Command Command Summary

0 0 None No Command will be executed.

0 1 Write Data Write the data contained in Data Byte to the

potentiometer(s) determined by the potenti­ometer selection bits.

1 0 Shutdown Potentiometer(s) determined by potentiome-

ter selection bits will enter Shutdown Mode.
Data bits for this command are ‘don’t cares’.

1 1 None No Command will be executed.

FIGURE 5-2: Command Byte Format.

P1* P0 Potentiometer Selections

0 0 Dummy Code: Neither Potentiometer

affected.

0 1 Command executed on

Potentiometer 0.

1 0 Command executed on

Potentiometer 1.

1 1 Command executed on both

Potentiometers.

DS11195C-page 18  2003 Microchip Technology Inc.

MCP41XXX/42XXX

5.4 Daisy-Chain Configuration

Multiple MCP42XXX devices can be connected in a
daisy-chain configuration, as shown in Figure 5-4, by
connecting the SO pin from one device to the SI pin on
the next device. The data on the SO pin is the output of
the 16-bit shift register. The daisy-chain configuration
allows the system designer to communicate with sev­eral devices without using a separate CS
device. The example shows a daisy-chain configura­tion with three devices, although any number of
devices (with or without the same resistor values) can
be configured this way. While it is not possible to use a
MCP41XXX at the beginning or middle of a daisy-chain
(because it does not provide the serial data out (SO)
pin), it is possible to use the device at the end of a
chain. As shown in the timing diagram in Figure 5-3,
data will be clocked-out of the SO pin on the falling
edge of the clock. The SO pin has a CMOS push-pull
output and will drive low when CS
not go to a high-impedance state when CS

When using the daisy-chain configuration, the maxi­mum clock speed possible is reduced to ~5.8 MHz,
because of the propagation delay of the data coming
out of the SO pin.

line for each

goes high. SO will

is held high.

When using the daisy-chain configuration, keep in mind
that the shift register of each device is automatically
loaded with zeros whenever a command is executed

= high). Because of this, the first 16 bits that come

(CS
out of the SO pin once the CS line goes low will always
be zeros. This means that when the first command is
being loaded into a device, it will always shift a NOP
command into the next device on the chain because
the command bits (and all the other bits) will be zeros.
This feature makes it necessary only to send command
and data bytes to the device farthest down the chain
that needs a new command. For example, if there were
three devices on the chain and it was desired to send a
command to the device in the middle, only 32 bytes of
data need to be transmitted. The last device on the
chain will have a NOP loaded from the previous device
so no registers will be affected when the CS

pin is

raised to execute the command. The user must

always ensure that multiples of 16 clocks are
always provided (while CS is low), as all commands
will abort if the number of clocks provided is not a
multiple of 16.

CS

111213141516

Data Byte

for Device 2

DPP

DPPXCXXXC DDDDDDD

SCK

SI

SO

23456789101

Command Byte

for Device 3

X C XXX

C DDDDDDD

First 16 bits shifted out

will always be zeros

†

There must always be multiples of 16 clocks while CS is low or commands will abort.

‡

DPP

The serial data out pin (SO) is only available on the MCP42XXX device.

111213141516

Data Byte

for Device 3

23456789101

Command Byte

for Device 2

X C XXX

C DDDDDDD

Command and Data for Device 3

start shifting out after the first 16 clocks

FIGURE 5-3: Timing Diagram for Daisy-Chain Configuration.

Data Registers for all
devices are loaded
on Rising Edge of CS

23456789101

Command Byte

for Device 1

X C XXX C DDDDDDD

Command and Data for Device 2

start shifting out after the first 32 clocks

111213141516

Data Byte

for Device 1

DPP

DPPXCXXX C DD DDDD D

 2003 Microchip Technology Inc. DS11195C-page 19

MCP41XXX/42XXX

CS
SCK

SO

Microcontroller

CS

SCK

SI

Device 1

EXAMPLE:

If you want to load the following
command/data into each part
in the chain.

SO

CS

SCK

SI

Device 2

SO

CS

SCK

SI

Device 3*

c

Start by setting CS low and
clocking in the command and
data that will end up in Device
3 (16 clocks).

d

Clock-In the command and
data for Device 2 (16 more
clocks). The data that was pre­viously loaded gets shifted to
the next device on the chain.

e

Clock-In the data for Device 1
(16 more clocks). The data that
was previously loaded into
Device 1 gets shifted into
Device 2 and Device 3 contains
the first byte loaded. Raise the
CS

line to execute the com­mands for all 3 devices at the
same time.

Device 1

XX10XX11

XX10XX00

XX01XX10

XX10XX11

11001100

Device 1

10101010

Device 1

11110000

Device 1

11001100

Last device on a daisy-chain may be a single channel MCP41XXX device.

*

Device 2

XX01XX10

Device 2

00000000

Device 2

XX10XX00

Device 2

XX01XX10

11110000

00000000

10101010

11110000

Device 3

XX10XX00

After 16 clocks, Device 2 and
Device 3 will both have all
zeros clocked in from the
previous part’s shift register.

Device 3

00000000

After 32 clocks, Device 2 has
the data previously loaded
into Device 1 and Device 3
gets 16 more zeros.

Device 3

00000000

After 48 clocks, all 3 devices
have the proper command/
data loaded into their shift
registers.

Device 3

XX10XX00

10101010

00000000

00000000

10101010

FIGURE 5-4: Daisy-Chain Configuration.

DS11195C-page 20  2003 Microchip Technology Inc.

MCP41XXX/42XXX

5.5 Reset (RS) Pin Operation

The Reset pin (RS) will automatically set all potentiom­eter data latches to mid-scale (Code 80h) when pulled
low (provided that the pin is held low at least 150 ns
and CS
the position of the SCK, SHDN

is high). The reset will execute regardless of

and SI pins. It is possi­ble to toggle RS low and back high while SHDN is low.
In this case, the potentiometer registers will reset to
mid-scale, but the potentiometer will remain in
shutdown mode until the SHDN

Note: Bringing the RS

pin is raised.

pin low while the CS pin is
low constitutes an invalid operating state
and will result in indeterminate results
when RS

and/or CS are brought high.

5.6 Shutdown (SHDN) Pin Operation

When held low, the shutdown pin causes the applica­tion circuit to go into a power-saving mode by open-cir­cuiting the A terminal and shorting the B and W
terminals for all potentiometers. Data register contents
are not affected by entering shutdown mode (i.e., when
the SHDN

pin is raised, the data register contents are

the same as before the shutdown mode was entered).

While in shutdown mode, it is still possible to clock in
new values for the data registers, as well as toggling

pin to cause all data registers to go to mid-scale.

the RS
The new values will take affect when the SHDN

pin is

raised.

If the device is powered-up with the SHDN

pin held low,
it will power-up in the shutdown mode with the data reg­isters set to mid-scale.

Note: Bringing the SHDN

pin low while the CS
pin is low constitutes an invalid operating
state and will result in indeterminate
results when SHDN

and/or CS are brought
high.

5.7 Power-up Considerations

When the device is powered on, the data registers will
be set to mid-scale (80h). A power-on reset circuit is
utilized to ensure that the device powers up in this
known state.

TABLE 5-1: TRUTH TABLE FOR LOGIC

INPUTS

SCK CS RS SHDN Action

X Ø H H Communication is initiated with

L L H H No action. Device is waiting for

¦ L H X Shift one bit into shift register.

Ø L H X Shift one bit out of shift register

X ¦ H H Based on command bits, either

X H H H Static Operation.

X H Ø H All data registers set and

X H Ø L All data registers set and

X H H Ø All potentiometers put into

X H H ¦ All potentiometers exit hard-

device. Device comes out of
standby mode.

data to be clocked into shift
register or CS
execute command.

The shift register can be loaded
while the SHDN

on the SO pin. The SO pin is
active while the SHDN
low.

load data from shift register into
data latches or execute shut­down command. Neither com­mand executed unless
multiples of 16 clocks have
been entered while CS
SO pin goes to a logic low.

latched to code 80h.

latched to code 80h. Device is
in hardware shutdown mode
and will remain in this mode.

hardware shutdown mode;
terminal A is open and W is
shorted to B.

ware shutdown mode. Potenti­ometers will also exit software
shutdown mode if this rising
edge occurs after a low pulse
on CS
latches are restored.

to go high to

pin is low.

pin is

is low.

. Contents of data

 2003 Microchip Technology Inc. DS11195C-page 21

MCP41XXX/42XXX

5.8 Using the MCP41XXX/42XXX in
SPI Mode 1,1

It is possible to operate the devices in SPI modes 0,0
and 1,1. The only difference between these two modes
is that, when using mode 1,1, the clock idles in the high
state, while in mode 0,0, the clock idles in the low state.
In both modes, data is clocked into the devices on the
rising edge of SCK and data is clocked out the SO pin
once the falling edge of SCK. Operations using mode
0,0 are shown in Figure 5-1. The example in
Figure 5-5 shows mode 1,1.

Data is always clocked out the SO
pin after the falling edge of SCK.

11 12 13 14 15 16

New Register Data

CS†

SCK

SO‡

Data is always latched in
on the rising edge of SCK.

2345678 9101

COMMAND BYTE DATA BYTE

Don’t

Care

Command

Bits

SI

X

†

There must always be multiples of 16 clocks while CS is low or commands will abort.

‡

The serial data out pin (SO) is only available on the MCP42XXX device.

Bits

X

C1

Don’t

Channel

Care

Bits

X

C0

First 16 bits Shifted out will always be zeros

Select

Bits

P1*

X

D7 D6 D5 D4 D3 D2 D1 D0

P0

FIGURE 5-5: Timing Diagram for SPI Mode 1,1 Operation.

Data Registers are
loaded on rising
edge of CS. Shift
register is loaded
with zeros at this time.

SO pin will always
drive low when CS

X

goes high.

DS11195C-page 22  2003 Microchip Technology Inc.

6.0 PACKAGING INFORMATION

6.1 Package Marking Information

MCP41XXX/42XXX

8-Lead PDIP (300 mil)

XXXXXXXX
XXXXXNNN

YYWW

8-Lead SOIC (150 mil)

XXXXXXXX
XXXXYYWW

Example:

MCP41010

I/P256

0313

Example:

MCP41050

I/SN0313

NNN

14-Lead PDIP (300 mil) Example:

XXXXXXXXXXXXXX
XXXXXXXXXXXXXX

YYWWNNN

14-Lead SOIC (150 mil)

Example:

256

MCP42010

I/P

0313256

XXXXXXXXXXX
XXXXXXXXXXX

YYWWNNN

14-Lead TSSOP (4.4mm) *

XXXXXXXX

Example:

42100I

YYWW

NNN

Legend: XX...X Customer specific information*

YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code

Note: In the event the full Microchip part number cannot be marked on one line, it will

be carried over to the next line thus limiting the number of available characters
for customer specific information.

* Standard marking consists of Microchip part number, year code, week code, facility code, mask rev#,

and assembly code.

42050ISL

XXXXXXXXXXX

0313256

0313

256

 2003 Microchip Technology Inc. DS11195C-page 23

MCP41XXX/42XXX

8-Lead Plastic Dual In-line (P) – 300 mil (PDIP)

E1

D

2

n

E

β

eB

Number of Pins
Pitch
Top to Seating Plane A .140 .155 .170 3.56 3.94 4.32
Molded Package Thickness
Base to Seating Plane A1 .015 0.38
Shoulder to Shoulder Width E .300 .313 .325 7.62 7.94 8.26
Molded Package Width E1 .240 .250 .260 6.10 6.35 6.60
Overall Length D .360 .373 .385 9.14 9.46 9.78
Tip to Seating Plane L .125 .130 .135 3.18 3.30 3.43
Lead Thickness
Upper Lead Width B1 .045 .058 .070 1.14 1.46 1.78
Lower Lead Width B .014 .018 .022 0.36 0.46 0.56
Overall Row Spacing §
Mold Draft Angle Top
Mold Draft Angle Bottom
* Controlling Parameter

§ Significant Characteristic

Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-001
Drawing No. C04-018

Dimension Limits MIN NOM MAX MIN NOM MAX

1

α

A

c

Units INCHES* MILLIMETERS

n
p

A2

c

eB

α

β

.115 .130 .145 2.92 3.30 3.68

.008 .012 .015 0.20 0.29 0.38

.310 .370 .430 7.87 9.40 10.92

A1

B1

B

88

.100 2.54

5 10 15 5 10 15
5 10 15 5 10 15

A2

L

p

DS11195C-page 24  2003 Microchip Technology Inc.

8-Lead Plastic Small Outline (SN) – Narrow, 150 mil (SOIC)

E

E1

p

D

2

MCP41XXX/42XXX

B

Number of Pins
Pitch

Molded Package Thickness

Foot Angle
Lead Thickness

Mold Draft Angle Top
Mold Draft Angle Bottom

* Controlling Parameter

§ Significant Characteristic

Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-012
Drawing No. C04-057

n

45°

c

β

n
p

A2

φ

c

α
β

1

h

A

φ

L

048048

A1

MILLIMETERSINCHES*Units

1.27.050

α

A2

MAXNOMMINMAXNOMMINDimension Limits

88

1.751.551.35.069.061.053AOverall Height

1.551.421.32.061.056.052

0.250.180.10.010.007.004A1Standoff §

6.206.025.79.244.237.228EOverall Width

3.993.913.71.157.154.146E1Molded Package Width

5.004.904.80.197.193.189DOverall Length

0.510.380.25.020.015.010hChamfer Distance

0.760.620.48.030.025.019LFoot Length

0.250.230.20.010.009.008

0.510.420.33.020.017.013BLead Width
1512015120
1512015120

 2003 Microchip Technology Inc. DS11195C-page 25

MCP41XXX/42XXX

14-Lead Plastic Dual In-line (P) – 300 mil (PDIP)

E1

D

2

n

E

β

eB

Number of Pins
Pitch
Top to Seating Plane A .140 .155 .170 3.56 3.94 4.32
Molded Package Thickness A2 .115 .130 .145 2.92 3.30 3.68
Base to Seating Plane A1 .015 0.38
Shoulder to Shoulder Width E .300 .313 .325 7.62 7.94 8.26
Molded Package Width E1 .240 .250 .260 6.10 6.35 6.60
Overall Length D .740 .750 .760 18.80 19.05 19.30
Tip to Seating Plane L .125 .130 .135 3.18 3.30 3.43
Lead Thickness
Upper Lead Width B1 .045 .058 .070 1.14 1.46 1.78
Lower Lead Width B .014 .018 .022 0.36 0.46 0.56
Overall Row Spacing § eB .310 .370 .430 7.87 9.40 10.92
Mold Draft Angle Top
Mold Draft Angle Bottom
* Controlling Parameter

§ Significant Characteristic
Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.

JEDEC Equivalent: MS-001
Drawing No. C04-005

1

A

c

A1

Dimension Limits MIN NOM MAX MIN NOM MAX

Units INCHES* MILLIMETERS

n
p

c

α

β

.008 .012 .015 0.20 0.29 0.38

5 10 15 5 10 15
5 10 15 5 10 15

B1

B

14 14

.100 2.54

α

A2

L

p

DS11195C-page 26  2003 Microchip Technology Inc.

14-Lead Plastic Small Outline (SL) – Narrow, 150 mil (SOIC)

E

E1

p

D

2

B

n

1

MCP41XXX/42XXX

45°

c

β

Number of Pins
Pitch

Foot Angle
Lead Thickness

Mold Draft Angle Top
Mold Draft Angle Bottom

* Controlling Parameter

§ Significant Characteristic

Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-012
Drawing No. C04-065

h

A

φ

L

n
p

φ

c

α
β

A1

048048

α

MILLIMETERSINCHES*Units

1.27.050

A2

MAXNOMMINMAXNOMMINDimension Limits

1414

1.751.551.35.069.061.053AOverall Height

1.551.421.32.061.056.052A2Molded Package Thickness

0.250.180.10.010.007.004A1Standoff §

6.205.995.79.244.236.228EOverall Width

3.993.903.81.157.154.150E1Molded Package Width

8.818.698.56.347.342.337DOverall Length

0.510.380.25.020.015.010hChamfer Distance

1.270.840.41.050.033.016LFoot Length

0.250.230.20.010.009.008

0.510.420.36.020.017.014BLead Width
1512015120
1512015120

 2003 Microchip Technology Inc. DS11195C-page 27

MCP41XXX/42XXX

14-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm (TSSOP)

E

E1

p

D

2

n

B

1

A

c

φ

β

Number of Pins
Pitch

Standoff §

Foot Angle
Lead Thickness

Mold Draft Angle Top
Mold Draft Angle Bottom

* Controlling Parameter

§ Significant Characteristic

Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.005” (0.127mm) per side.
JEDEC Equivalent: MO-153
Drawing No. C04-087

n
p

A1

φ

c

α

β

L

MILLIMETERS*INCHESUnits

0.65.026

α

A2A1

MAXNOMMINMAXNOMMINDimension Limits

1414

1.10.043AOverall Height

0.950.900.85.037.035.033A2Molded Package Thickness

0.150.100.05.006.004.002

6.506.386.25.256.251.246EOverall Width

4.504.404.30.177.173.169E1Molded Package Width

5.105.004.90.201.197.193DMolded Package Length

0.700.600.50.028.024.020LFoot Length
840840

0.200.150.09.008.006.004

0.300.250.19.012.010.007BLead Width

10501050
10501050

DS11195C-page 28  2003 Microchip Technology Inc.

PRODUCT IDENTIFICATION SYSTEM

MCP41XXX/42XXX

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office

PART NO. X /XX

Device

PackageTemperature

Range

Device: MCP41010: Single Digital Potentiometer (10 kΩ)

Temperature Range: I = -40°C to +85°C

Package: P = Plastic DIP (300 mil Body), 8-lead, 14-lead

MCP41010T: Single Digital Potentiometer (10 kΩ)

MCP41050: Single Digital Potentiometer (50 kΩ)

MCP41050T: Single Digital Potentiometer (50 kΩ)
MCP41100: Single Digital Potentiometer (100 kΩ)

MCP41100T: Single Digital Potentiometer (100 kΩ)

MCP42010: Dual Digital Potentiometer (10 kΩ)
MCP42010T: Dual Digital Potentiometer (10 kΩ)

MCP42050: Dual Digital Potentiometer (50 kΩ)
MCP42050T: Dual Digital Potentiometer (50 kΩ)

MCP42100: Dual Digital Potentiometer (100 kΩ)
MCP42100T: Dual Digital Potentiometer (100 kΩ)

E = -40°C to +125°C

SN = Plastic SOIC (150 mil Body), 8-lead
SL = Plastic SOIC (150 mil Body), 14-lead
ST = TSSOP (4.4mm Body), 14-lead

(Tape and Reel)

(Tape and Reel)

(Tape and Reel)

(Tape and Reel)

(Tape and Reel)

(Tape and Reel)

Examples:

a) MCP41010-I/SN: I-Temp., 8LD SOIC pkg.
b) MCP41010-E/P: E-Temp., 8LD PDIP pkg.
c) MCP41010T-I/SN: Tape and Reel, I-Temp.,

8LD SOIC pkg.
d) MCP41050-E/SN: E-Temp., 8LD SOIC pkg.
e) MCP41050-I/P: I-Temp., 8LD PDIP pkg.
f) MCP41050-E/SN: E-Temp., 8LD SOIC pkg.
g) MCP41100-I/SN: I-Temp., 8LD SOIC

h) MCP41100-E/P: E-Temp., 8LD PDIP pkg.
i) MCP41100T-I/SN: I-Temp., 8LD SOIC pkg.

a) MCP42010-E/P: E-Temp., 14LD PDIP pkg.
b) MCP42010-I/SL: I-Temp., 14LD SOIC pkg.
c) MCP42010-E/ST: E-Temp., 14LD TSSOP

d) MCP42010T-I/ST: Tape and Reel, I-Temp.,

e) MCP42050-E/P: E-Temp., 14LD PDIP pkg.
f) MCP42050T-I/SL: Tape and Reel, I-Temp.,

g) MCP42050-E/SL: E-Temp., 14LD SOIC pkg.
h) MCP42050-I/ST: I-Temp., 14LD TSSOP

i) MCP42050T-I/SL: Tape and Reel, I-Temp.,

j) MCP42050T-I/ST: Tape and Reel, I-Temp.,

k) MCP42100-E/P: E-Temp., 14LD PDIP pkg.
l) MCP42100-I/SL: I-Temp., 14LD SOIC pkg.
m) MCP42100-E/ST: E-Temp., 14LD TSSOP

n) MCP42100T-I/SL: Tape and Reel, I-Temp.,

o) MCP42100T-I/ST: Tape and Reel, I-Temp.,

.

package.

pkg.

14LD TSSOP pkg.

14LD SOIC pkg.

pkg.

14LD SOIC pkg.

14LD TSSOP pkg.

pkg.

14LD SOIC pkg.

14LD TSSOP pkg.

Sales and Support

Data Sheets

Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and
recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:

1. Your local Microchip sales office

2. The Microchip Corporate Literature Center U.S. FAX: [phone]

3. The Microchip Worldwide Site (www.microchip.com)

Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.

Customer Notification System

Register on our web site (www.microchip.com/cn) to receive the most current information on our products.

 2003 Microchip Technology Inc. DS11195C-page 29

MCP41XXX/42XXX

NOTES:

DS11195C-page 30  2003 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device
applications and the like is intended through suggestion only
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
No representation or warranty is given and no liability is
assumed by Microchip Technology Incorporated with respect
to the accuracy or use of such information, or infringement of
patents or other intellectual property rights arising from such
use or otherwise. Use of Microchip’s products as critical
components in life support systems is not authorized except
with express written approval by Microchip. No licenses are
conveyed, implicitly or otherwise, under any intellectual
property rights.

Trademarks

The Microchip name and logo, the Microchip logo, dsPIC,
K

EELOQ

, MPLAB, PIC, PICmicro, PICSTART, PRO MATE and
PowerSmart are registered trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.

FilterLab, microID, MXDEV, MXLAB, PICMASTER, SEEVAL
and The Embedded Control Solutions Company are
registered trademarks of Microchip Technology Incorporated
in the U.S.A.

Accuron, Application Maestro, dsPICDEM, dsPICDEM.net,
ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In­Circuit Serial Programming, ICSP, ICEPIC, microPort,
Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM,
PICC, PICkit, PICDEM, PICDEM.net, PowerCal, PowerInfo,
PowerMate, PowerTool, rfLAB, rfPIC, Select Mode,
SmartSensor, SmartShunt, SmartTel and Total Endurance are
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.

Serialized Quick Turn Programming (SQTP) is a service mark
of Microchip Technology Incorporated in the U.S.A.

All other trademarks mentioned herein are property of their
respective companies.

© 2003, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.

Printed on recycled paper.

Microchip received QS-9000 quality system
certification for its worldwide headquarters,
design and wafer fabrication facilities in
Chandler and Tempe, Arizona in July 1999
and Mountain View, California in March 2002.
The Company’s quality system processes and
procedures are QS-9000 compliant for its
PICmicro
devices, Serial EEPROMs, microperipherals,
non-volatile memory and analog products. In
addition, Microchip’s quality system for the
design and manufacture of development
systems is ISO 9001 certified.

®

8-bit MCUs, KEEL

®

code hopping

OQ

 2003 Microchip Technology Inc. DS11195C-page 31

M

WORLDWIDE SALES AND SERVICE

AMERICAS

Corporate Office

2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: [phone]
Fax: [phone]
Technical Support: 480-792-7627
Web Address: http://www.microchip.com

Atlanta

3780 Mansell Road, Suite 130
Alpharetta, GA 30022
Tel: [phone]
Fax: [phone]

Boston

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Tel: [phone]
Fax: [phone]

Chicago

333 Pierce Road, Suite 180
Itasca, IL 60143
Tel: [phone]
Fax: [phone]

Dallas

4570 Westgrove Drive, Suite 160
Addison, TX 75001
Tel: [phone]
Fax: [phone]

Detroit

Tri-Atria Office Building
32255 Northwestern Highway, Suite 190
Farmington Hills, MI 48334
Tel: [phone]
Fax: [phone]

Kokomo

2767 S. Albright Road
Kokomo, IN 46902
Tel: [phone]
Fax: [phone]

Los Angeles

18201 Von Karman, Suite 1090
Irvine, CA 92612
Tel: [phone]
Fax: [phone]

Phoenix

2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: [phone]
Fax: [phone]

San Jose

2107 North First Street, Suite 590
San Jose, CA 95131
Tel: [phone]
Fax: [phone]

Toronto

6285 Northam Drive, Suite 108
Mississauga, Ontario L4V 1X5, Canada
Tel: [phone]
Fax: [phone]

ASIA/PACIFIC

Australia

Suite 22, 41 Rawson Street
Epping 2121, NSW
Australia
Tel: [phone]
Fax: [phone]

China - Beijing

Unit 915
Bei Hai Wan Tai Bldg.
No. 6 Chaoyangmen Beidajie
Beijing, 100027, No. China
Tel: [phone]
Fax: [phone]

China - Chengdu

Rm. 2401-2402, 24th Floor,
Ming Xing Financial Tower
No. 88 TIDU Street
Chengdu 610016, China
Tel: [phone]
Fax: [phone]

China - Fuzhou

Unit 28F, World Trade Plaza
No. 71 Wusi Road
Fuzhou 350001, China
Tel: [phone]
Fax: [phone]

China - Hong Kong SAR

Unit 901-6, Tower 2, Metroplaza
223 Hing Fong Road
Kwai Fong, N.T., Hong Kong
Tel: [phone]
Fax: [phone]

China - Shanghai

Room 701, Bldg. B
Far East International Plaza
No. 317 Xian Xia Road
Shanghai, 200051
Tel: [phone]
Fax: [phone]

China - Shenzhen

Rm. 1812, 18/F, Building A, United Plaza
No. 5022 Binhe Road, Futian District
Shenzhen 518033, China
Tel: [phone]
Fax: [phone]

China - Shunde

Room 401, Hongjian Building
No. 2 Fengxiangnan Road, Ronggui Town
Shunde City, Guangdong 528303, China
Tel: [phone] Fax: [phone]

China - Qingdao

Rm. B505A, Fullhope Plaza,
No. 12 Hong Kong Central Rd.
Qingdao 266071, China
Tel: [phone] Fax: [phone]

India

Divyasree Chambers
1 Floor, Wing A (A3/A4)
No. 11, O’Shaugnessey Road
Bangalore, 560 025, India
Tel: [phone] Fax: [phone]

Japan

Benex S-1 6F
3-18-20, Shinyokohama
Kohoku-Ku, Yokohama-shi
Kanagawa, 222-0033, Japan
Tel: [phone] Fax: [phone]

Korea

168-1, Youngbo Bldg. 3 Floor
Samsung-Dong, Kangnam-Ku
Seoul, Korea 135-882
Tel: [phone] Fax: [phone] or
82-2-558-5934

Singapore

200 Middle Road
#07-02 Prime Centre
Singapore, 188980
Tel: [phone] Fax: [phone]

Tai wan

Kaohsiung Branch
30F - 1 No. 8
Min Chuan 2nd Road
Kaohsiung 806, Taiwan
Tel: [phone]
Fax: [phone]

Tai wan

Taiwan Branch
11F-3, No. 207
Tung Hua North Road
Taipei, 105, Taiwan
Tel: [phone] Fax: [phone]

EUROPE

Austria

Durisolstrasse 2
A-4600 Wels
Austria
Tel: [phone]
Fax: [phone]

Denmark

Regus Business Centre
Lautrup hoj 1-3
Ballerup DK-2750 Denmark
Tel: [phone] Fax: [phone]

France

Parc d’Activite du Moulin de Massy
43 Rue du Saule Trapu
Batiment A - ler Etage
91300 Massy, France
Tel: [phone]
Fax: [phone]

Germany

Steinheilstrasse 10
D-85737 Ismaning, Germany
Tel: [phone]
Fax: [phone]

Italy

Via Quasimodo, 12
20025 Legnano (MI)
Milan, Italy
Tel: [phone]
Fax: [phone]

Netherlands

P. A. De Biesbosch 14
NL-5152 SC Drunen, Netherlands
Tel: [phone]
Fax: [phone]

United Kingdom

505 Eskdale Road
Winnersh Triangle
Wokingham
Berkshire, England RG41 5TU
Tel: [phone]
Fax: [phone]

07/28/03

DS11195C-page 32  2003 Microchip Technology Inc.