Datasheet MCP2561FD, MCP2562FD Datasheet

MCP2561/2FD

MCP2562FD

PDIP, SOIC

VDD

VSS

RXD

CANH

CANL

1

2

3

4

8

7

6

5

VIO

STBYTXD

MCP2561FD

PDIP, SOIC

VDD

VSS

RXD

CANH

CANL

1

2

3

4

8

7

6

5

SPLIT

STBYT

XD

MCP2561FD

3x3 DFN*

VDD

VSS

RXD

CANH

CANL

1

2

3

4

8

7

6

5

SPLIT

STBYT

XD

EP

9

MCP2562FD

3x3 DFN*

VDD

VSS

RXD

CANH

CANL

1

2

3

4

8

7

6

5

VIO

STBYTXD

EP

9

* Includes Exposed Thermal Pad (EP); see Table 1-2

High-Speed CAN Flexible Data Rate Transceiver

Features:

• Optimized for CAN FD (Flexible Data rate) at 2, 5
and 8 Mbps Operation

- Maximum Propagation Delay: 120 ns

- Loop Delay Symmetry: -10%/+10% (2 Mbps)

• Implements ISO-11898-2 and ISO-11898-5
S

tandard Physical Layer Requirements

• Very Low Standby Current (5 µA, typical)

•V

IO Supply Pin to Interface Directly to 

CAN Controllers and Microcontrollers with 

1.8V to 5.5V I/O

• SPLIT Output Pin to Stabilize Common Mode in
Bi

ased Split Termination Schemes

• CAN Bus Pins are Disconnected when Device is
Unpowered

- An Unpowered Node or Brown-Out Event will

N

ot Load the CAN Bus

• Detection of Ground Fault:

- Permanent Dominant Detection on T

- Permanent Dominant Detection on Bus

• Power-on Reset and Voltage Brown-Out
P

rotection on V

• Protection Against Damage Due to Short-Circuit
C

onditions (Positive or Negative Battery Voltage)

• Protection Against High-Voltage Transients in
Au

tomotive Environments

• Automatic Thermal Shutdown Protection

• Suitable for 12V and 24V Systems

• Meets or exceeds stringent automotive design
re

quirements including “Hardware Requirements
for LIN, CAN and FlexRay Interfaces in
Automotive Applications”, Version 1.3, May 2012

- Radiated emissions @ 2 Mbps with Common

Mode Choke (CMC)

-DPI @ 2 Mbps with CMC

• High ESD Protection on CANH and CANL,
me

eting IEC61000-4-2 up to ±14 kV

• Available in PDIP-8L, SOIC-8L and 3x3 DFN-8L

• Temperature ranges:

- Extended (E): -40°C to +125°C

- High (H): -40°C to +150°C

MCP2561/2FD Family Members

Device Feature Description

MCP2561FD SPLIT pin Common mode stabilization

MCP2562FD V

Note: For ordering information, see the “Product Identification System” section on page 29.

 2014 Microchip Technology Inc. DS20005284A-page 1

DD Pin

Description:

The MCP2561/2FD is a second generation high-speed
CAN transceiver from Microchip Technology Inc. It
offers the same features as the MCP2561/2.
Additionally, it guarantees Loop Delay Symmetry in
order to support the higher data rates required for CAN
FD. The maximum propagation delay was improved to
support longer bus length.

The device meets the automotive requirements for

AN FD bit rates exceeding 2 Mbps, low quiescent

C
current, electromagnetic compatibility (EMC) and
electrostatic discharge (ESD).

Package Types

XD

IO pin Internal level shifter on digital I/O pins

MCP2561/2FD

Note 1: There is only one receiver implemented. The receiver can operate in Low-Power or High-Speed mode.

2: Only MCP2561FD has the SPLIT pin.

3: Only MCP2562FD has the V

IO pin. In MCP2561FD, the supply for the digital I/O is internally connected

to V

DD.

V

DD

CANH

CANL

T

XD

R

XD

Driver

and

Slope Control

Thermal

Protection

POR

UVLO

Digital I/O

Supply

V

IO

(3)

V

SS

STBY

Permanent

Dominant Detect

V

IO

V

IO

Mode

Control

VDD/2

SPLIT

(2 )

Wake-Up

Filter

CANH

CANL

CANH

CANL

Receiver

LP_RX

(1)

HS_RX

Block Diagram

DS20005284A-page 2  2014 Microchip Technology Inc.

MCP2561/2FD

1.0 DEVICE OVERVIEW

The MCP2561/2FD is a high-speed CAN device,
fault-tolerant device that serves as the interface
between a CAN protocol controller and the physical
bus. The MCP2561/2FD device provides differential
transmit and receive capability for the CAN protocol
controller, and is fully compatible with the ISO-11898-2
and ISO-11898-5 standards.

The Loop Delay Symmetry is guaranteed to support

ata rates that are up to 5 Mbps for CAN FD (Flexible

d
D

ata rate). The maximum propagation delay was

improved to support longer bus length.

Typically, each node in a CAN system must have a

evice to convert the digital signals generated by a

d
CAN controller to signals suitable for transmission over
the bus cabling (differential output). It also provides a
buffer between the CAN controller and the high-voltage
spikes that can be generated on the CAN bus by
outside sources.

1.1 Mode Control Block

The MCP2561/2FD supports two modes of operation:

• Normal Mode

• Standby Mode

These modes are summarized in Ta ble 1-1.

1.1.1 NORMAL MODE

Normal mode is selected by applying low-level voltage
to the STBY pin. The driver block is operational and
can drive the bus pins. The slopes of the output signals
on CANH and CANL are optimized to produce minimal
electromagnetic emissions (EME).

The high speed differential receiver is active.

1.1.2 STANDBY MODE

The device may be placed in Standby mode by
applying high-level voltage to the STBY pin. In Standby
mode, the transmitter and the high-speed part of the
receiver are switched off to minimize power
consumption. The low-power receiver and the wake-up
filter blocks are enabled to monitor the bus for activity.
The receive pin (R
representation of the CAN bus, due to the wake-up
filter.

The CAN controller gets interrupted by a negative edge

XD pin (Dominant state on the CAN bus). The

the R

on
CAN controller must put the MCP2561/2FD back into
Normal mode, using the STBY pin, in order to enable
high speed data communication.

The CAN bus wake-up function requires both supply

oltages, V

v

DD and VIO, to be in valid range.

XD) will show a delayed

TABLE 1-1: MODES OF OPERATION

Mode STBY Pin

Normal LOW Bus is Dominant Bus is Recessive

Standby HIGH Wake-up request is detected No wake-up request detected

1.2 Transmitter Function

The CAN bus has two states:

• Dominant State

• Recessive State

A Dominant state occurs when the differential voltage

etween CANH and CANL is greater than V

b
A Recessive state occurs when the differential voltage
is less than V
states correspond to the Low and High state of the T
input pin, respectively. However, a Dominant state
initiated by another CAN node will override a
Recessive state on the CAN bus.

DIFF(R)(I). The Dominant and Recessive

DIFF(D)(I).

LOW HIGH

1.4 Internal Protection

CANH and CANL are protected against battery
short-circuits and electrical transients that can occur on
the CAN bus. This feature prevents destruction of the
transmitter output stage during such a fault condition.

The device is further protected from excessive current

oading by thermal shutdown circuitry that disables the

l
output drivers when the junction temperature exceeds

XD

a nominal limit of +175°C. All other parts of the chip
remain operational, and the chip temperature is
lowered due to the decreased power dissipation in the
transmitter outputs. This protection is essential to
protect against bus line short-circuit-induced damage.

RXD Pin

1.3 Receiver Function

In Normal mode, the RXD output pin reflects the
differential bus voltage between CANH and CANL. The
Low and High states of the R
to the Dominant and Recessive states of the CAN bus,
respectively.

XD output pin correspond

 2014 Microchip Technology Inc. DS20005284A-page 3

MCP2561/2FD

1.5 Permanent Dominant Detection

The MCP2561/2FD device prevents two conditions:

• Permanent Dominant condition on T

• Permanent Dominant condition on the bus

In Normal mode, if the MCP2561/2FD detects an

tended Low state on the T

ex

XD input, it will disable the

CANH and CANL output drivers in order to prevent the
corruption of data on the CAN bus. The drivers will
remain disabled until T

XD goes High.

In Standby mode, if the MCP2561/2FD detects an

tended Dominant condition on the bus, it will set the

ex

XD pin to Recessive state. This allows the attached

R
controller to go to Low-Power mode until the Dominant
issue is corrected. RXD is latched High until a
Recessive state is detected on the bus, and the
wake-up function is enabled again.

Both conditions have a time-out of 1.25 ms (typical).

implies a maximum bit time of 69.44 µs

This
(14.4 kH
on t

z), allowing up to 18 consecutive dominant bits

he bus.

XD

1.6 Power-On Reset (POR) and 
Undervoltage Detection

The MCP2561/2FD has undervoltage detection on
both supply pins: V
thresholds are 1.2V for V

When the device is powered on, CANH and CANL

in in a high-impedance state until both V

rema
V

IO exceed their undervoltage levels. Once powered

on, CANH and CANL will enter a high-impedance state
if the voltage level at V
level, providing voltage brown-out protection during
normal operation.

In Normal mode, the receiver output is forced to

cessive state during an undervoltage condition on

Re
VDD. In Standby mode, the low-power receiver is only
enabled when both V
above their respective undervoltage thresholds. Once
these threshold voltages are reached, the low-power
receiver is no longer controlled by the POR comparator
and remains operational down to about 2.5V on the

DD supply (MCP2561/2FD). The MCP2562FD

V
transfers data to the R
supply.

DD and VIO. Typical undervoltage

IO and 4V for VDD.

DD and

DD drops below the undervoltage

DD and VIO supply voltages rise

XD pin down to 1.8V on the VIO

1.7 Pin Descriptions

Table 1-2 describes the pinout.

TABLE 1-2: MCP2561/2FD PIN DESCRIPTIONS

MCP2561FD

3x3 DFN

1 1 1 1 T

2 2 2 2 VSS Ground

3 3 3 3 VDD Supply Voltage

4 4 4 4 R

5 5 — — SPLIT Common Mode Stabilization - MCP2561FD only

— — 5 5 VIO Digital I/O Supply Pin - MCP2562FD only

6 6 6 6 CANL CAN Low-Level Voltage I/O

7 7 7 7 CANH CAN High-Level Voltage I/O

8 8 8 8 STBY Standby Mode Input

9 — 9 — EP Exposed Thermal Pad

MCP2561FD

PDIP, SOIC

MCP2562FD

3x3 DFN

MCP2562FD

PDIP, SOIC

Symbol Pin Function

XD Transmit Data Input

XD Receive Data Output

DS20005284A-page 4  2014 Microchip Technology Inc.

MCP2561/2FD

1.7.1 TRANSMITTER DATA 
INPUT PIN (T

The CAN transceiver drives the differential output pins
CANH and CANL according to T
connected to the transmitter data output of the CAN
controller device. When TXD is Low, CANH and CANL
are in the Dominant state. When T
and CANL are in the Recessive state, provided that
another CAN node is not driving the CAN bus with a
Dominant state. T
resistor (nominal 33 k) t
MCP2561FD or MCP2562FD, respectively.

XD is connected to an internal pull-up

XD)

XD. It is usually

XD is High, CANH

o VDD or VIO, in the

1.7.2 GROUND SUPPLY PIN (VSS)

Ground supply pin.

1.7.3 SUPPLY VOLTAGE PIN (VDD)

Positive supply voltage pin. Supplies transmitter and
receiver, including the wake-up receiver.

1.7.4 RECEIVER DATA 
OUTPUT PIN (R

RXD is a CMOS-compatible output that drives High or
Low depending on the differential signals on the CANH
and CANL pins, and is usually connected to the
receiver data input of the CAN controller device. R
High when the CAN bus is Recessive, and Low in the
Dominant state. RXD is supplied by VDD or VIO, in the
MCP2561FD or MCP2562FD, respectively.

XD)

XD is

1.7.5 SPLIT PIN (MCP2561FD ONLY)

Reference Voltage Output (defined as VDD/2). The pin
is only active in Normal mode. In Standby mode, or
when VDD is off, SPLIT floats.

1.7.6 VIO PIN (MCP2562FD ONLY)

Supply for digital I/O pins. In the MCP2561FD, the
supply for the digital I/O (T
internally connected to V

XD, RXD and STBY) is

DD.

1.7.7 CAN LOW PIN (CANL)

The CANL output drives the Low side of the CAN
differential bus. This pin is also tied internally to the
receive input comparator. CANL disconnects from the
bus when MCP2561/2FD is not powered.

1.7.8 CAN HIGH PIN (CANH)

The CANH output drives the high-side of the CAN
differential bus. This pin is also tied internally to the
receive input comparator. CANH disconnects from the
bus when MCP2561/2FD is not powered.

1.7.9 STANDBY MODE INPUT PIN (STBY)

This pin selects between Normal or Standby mode. In
Standby mode, the transmitter, high speed receiver and
SPLIT are turned off, only the low power receiver and
wake-up filter are active. STBY is connected to an
internal MOS pull-up resistor to VDD or VIO, in the
MCP2561FD or MCP2562FD, respectively. The value
of the MOS pull-up resistor depends on the supply volt­age. Typical values are 660 k for 5V
and 4.4 M for 1

.8V

, 1.1 M for 3.3V

1.7.10 EXPOSED THERMAL PAD (EP)

It is recommended that this pad is connected to VSS for
the enhancement of electromagnetic immunity and
thermal resistance.

 2014 Microchip Technology Inc. DS20005284A-page 5

MCP2561/2FD

5V LDO

VDD

VDD

TXD

RXD

STBY

CANTX

CANRX

RBX

V

SS VSS

PIC

®

MCU

MCP2561FD

SPLIT

CANH

CANL

4700 pF

0.1 μF

CANH

CANL

60

60

300

Optional

(1)

VBAT

Note 1: Optional resistor to allow communication during bus failure (CANL shorted to ground).

1.8V LDO

VDD VDD

TXD

RXD

STBY

CANTX

CANRX

RBX

V

SS Vss

PIC

®

MCU

MCP2562FD

CANH

CANL

5V LDO

VIO

0.1 μF

CANH

CANL

0.1 μF

120

VBAT

1.8 Typical Applications

In order to meet the EMC/EMI requirements, a
Common Mode Choke (CMC) might be required for
data rates greater than 1 Mbps.

FIGURE 1-1: MCP2561FD WITH SPLIT PIN

FIGURE 1-2: MCP2562FD WITH V

IO PIN

DS20005284A-page 6  2014 Microchip Technology Inc.

MCP2561/2FD

RIN

RIN

RDIFF

CIN CIN

CDIFF

CANL

CANH

GROUND

ECU

2.0 ELECTRICAL

CHARACTERISTICS

2.1 Terms and Definitions

A number of terms are defined in ISO-11898 that are
used to describe the electrical characteristics of a CAN
transceiver device. These terms and definitions are
summarized in this section.

2.1.1 BUS VOLTAGE

VCANL and VCANH denote the voltages of the bus line
wires CANL and CANH relative to ground of each
individual CAN node.

2.1.2 COMMON MODE BUS VOLTAGE
RANGE

Boundary voltage levels of VCANL and VCANH with
respect to ground, for which proper operation will occur,
if up to the maximum number of CAN nodes are
connected to the bus.

2.1.3 DIFFERENTIAL INTERNAL
CAPACITANCE, C
(OF A CAN NODE)

Capacitance seen between CANL and CANH during
the Recessive state, when the CAN node is
disconnected from the bus (see Figure 2-1).

DIFF 

2.1.5 DIFFERENTIAL VOLTAGE, VDIFF 
(OF CAN BUS)

Differential voltage of the two-wire CAN bus, value

DIFF = VCANH – VCANL.

V

2.1.6 INTERNAL CAPACITANCE, CIN 
(OF A CAN NODE)

Capacitance seen between CANL (or CANH) and
ground during the Recessive state, when the CAN
node is disconnected from the bus (see Figure 2-1).

2.1.7 INTERNAL RESISTANCE, RIN 
(OF A CAN NODE)

Resistance seen between CANL (or CANH) and
ground during the Recessive state, when the CAN
node is disconnected from the bus (see Figure 2-1).

FIGURE 2-1: PHYSICAL LAYER

DEFINITIONS

2.1.4 DIFFERENTIAL INTERNAL
RESISTANCE, R

DIFF 

(OF A CAN NODE)

Resistance seen between CANL and CANH during the
Recessive state when the CAN node is disconnected
from the bus (see Figure 2-1).

 2014 Microchip Technology Inc. DS20005284A-page 7

MCP2561/2FD

2.2 Absolute Maximum Ratings†

VDD.............................................................................................................................................................................7.0V

IO ..............................................................................................................................................................................7.0V

V

DC Voltage at T

DC Voltage at CANH, CANL and SPLIT ..................................................................................................

Transient Voltage on CANH, CANL (ISO-7637) (See Figure 2-5)............................................................ -150V to +100V

Storage temperature ...............................................................................................................

Operating ambient temperature ....................................................................................................

Virtual Junction Temperature, T

Soldering temperature of leads (10 seconds) ..........................................................................................

ESD protection on CANH and CANL pins for MC

ESD protection on CANH and CANL pins for MC

ESD protection on CANH and CANL pins (IEC 8

ESD protection on all other pins (IEC 801; Human Body Model)........................................................................

ESD protection on all pins (IEC 801; Machine Model) .............................................................................

ESD protection on all pins (IEC 801; Charge Device Model).........................................................................

XD, RXD, STBY and VSS.............................................................................................-0.3V to VIO + 0.3V

.... -58V to +58V

................-55°C to +150°C

..........-40°C to +150°C

VJ (IEC60747-1) ....................................................................................-40°C to +190°C

.............+300°C

P2561FD (IEC 61000-4-2)........................................................±14 kV

P2562FD (IEC 61000-4-2)..........................................................±8 kV

01; Human Body Model)..............................................................±8 kV

.....±4 kV

...............±300V

.........±750V

† NOTICE:
is a stress rating only and functional operation of the device at those or any other conditions above those indicated in
the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods
may affect device reliability.

Stresses above those listed under “Maximum ratings” may cause permanent damage to the device. This

DS20005284A-page 8  2014 Microchip Technology Inc.

MCP2561/2FD

2.3 DC Characteristics

Electrical Characteristics: Extended (E): TAMB = -40°C to +125°C and High (H): TAMB = -40°C to +150°C; 

V

DD = 4.5V to 5.5V, VIO = 1.8V to 5.5V (Note 2), RL = 60, CL = 100 pF; unless otherwise specified.

Characteristic Sym Min Typ Max Units Conditions

SUPPLY

DD Pin

V

Voltage Range

Supply Current

Standby Current

High Level of the POR 

V

I

PORH

V

DD

IDD

DDS

Comparator

Low Level of the POR 

V

PORL

Comparator

Hysteresis of POR 

VPORD

Comparator

VIO Pin

Digital Supply Voltage Range

Supply Current on V

IO

Standby Current

Undervoltage detection on V

IO

IO

V

IIO

DDS

I

VUVD(IO)

BUS LINE (CANH; CANL) TRANSMITTER

CANH; CANL: 

V

O(R)

Recessive Bus Output Voltage

CANH; CANL: 

VO(S)

Bus Output Voltage in Standby

Recessive Output Current I

CANH: Dominant 

O(R) -5 — +5 mA -24V < VCAN < +24V

O(D)

V

Output Voltage

CANL: Dominant 
Output Voltage

Symmetry of Dominant 

V

O(D)(M)

Output Voltage

DD – VCANH – VCANL)

(V

Dominant: Differential 

VO(DIFF) 1.5 2.0 3.0 V VTXD = VSS; RL = 50 to 65

Output Voltage

Recessive: 
Differential Output Voltage

Note 1: C

haracterized; not 100% tested.

2: Only MCP2562FD has VIO pin. For the MCP2561FD, VIO is internally connected to VDD.
3: -12V to 12V is ensured by characterization, tested from -2V to 7V.

4.5 — 5.5

— 5 10

Recessive; VTXD = VDD

mA

— 45 70 Dominant; VTXD = 0V

— 5 15

— 5 15 MCP2562FD; In

3.8 — 4.3

3.4 — 4.0

0.3 — 0.8

1.8 — 5.5

— 4 30

MCP2561FD

µA

V

V

V

V

Recessive; VTXD = VIO

µA

cludes IIO

— 85 500 Dominant; VTXD = 0V

— 0.3 1

— 1.2 —

2.0 0.5V

DD 3.0

-0.1 0.0 +0.1

2.75 3.50 4.50

0.50 1.50 2.25 R

-400 0 +400 mV V

(Note 1)

µA

(Note 1)

V

VTXD = VDD; No load

V

STBY = V

V

T

XD = 0; RL = 50 to 65

V

L = 50 to 65

TXD = VSS (Note 1)

TXD = VDD; No load

Figure 2-2, Figure 2-4

-120 0 12 mV V

TXD = VDD

Figure 2-2, Figure 2-4

-500 0 50 mV V

TXD = VDD

no load.

,

Figure 2-2, Figure 2-4

 2014 Microchip Technology Inc. DS20005284A-page 9

MCP2561/2FD

2.3 DC Characteristics (Continued)

Electrical Characteristics: Extended (E): TAMB = -40°C to +125°C and High (H): TAMB = -40°C to +150°C; 

DD = 4.5V to 5.5V, VIO = 1.8V to 5.5V (Note 2), RL = 60, CL = 100 pF; unless otherwise specified.

V

Characteristic Sym Min Typ Max Units Conditions

CANH: Short Circuit 
Output Current

CANL: Short Circuit 
Output Current

BUS LINE (CANH; CANL) RECEIVER

Recessive Differential 
Input Voltage

Dominant Differential 
Input Voltage

Differential 
Receiver Threshold

Differential 
Input Hysteresis

Common Mode 
Input Resistance

Common Mode 
Resistance Matching

Differential Input 
Resistance

Common Mode 
Input Capacitance

Differential 
Input Capacitance

CANH, CANL: 
Input Leakage

Note 1: Characterized; not 100% tested.

2: Only MCP2562FD has V
3: -12V to 12V is ensured by characterization, tested from -2V to 7V.

IO(SC) -120 85 — mA VTXD = VSS; VCANH = 0V;

CANL: floating

-100 — — mA same as above, but

DD=5V, TAMB = 25°C (Note 1)

V

— 75 +120 mA V

TXD = VSS; VCANL = 18V;

CANH: floating

— — +100 mA same as above, but

VDD=5V, TAMB = 25°C (Note 1)

DIFF(R)(I) -1.0 — +0.5 V Normal Mode;

V

-12V < V(

CANH, CANL) < +12V;

See Figure 2-6 (Note 3)

-1.0 — +0.4 Standby Mode;

-12V < V(

CANH, CANL) < +12V;

See Figure 2-6 (Note 3)

DIFF(D)(I) 0.9 — VDD V Normal Mode;

V

-12V < V(

CANH, CANL) < +12V;

See Figure 2-6 (Note 3)

1.0 — V

DD Standby Mode;

-12V < V(

CANH, CANL) < +12V;

See Figure 2-6 (Note 3)

TH(DIFF) 0.5 0.7 0.9 V Normal Mode;

V

-12V < V(

CANH, CANL) < +12V;

See Figure 2-6 (Note 3)

0.4 — 1.15 Standby Mode;

-12V < V(

CANH, CANL) < +12V;

See Figure 2-6 (Note 3)

HYS(DIFF) 50 — 200 mV Normal mode, see Figure 2-6,

V

(Note 1)

IN 10 — 30 k (Note 1)

R

R

IN(M) -1 0 +1 % VCANH = VCANL, (Note 1)

R

IN(DIFF) 10 — 100 k (Note 1)

IN(CM) — — 20 pF VTXD = VDD; (Note 1)

C

C

IN(DIFF) — — 10 VTXD = VDD; (Note 1)

I

LI -5 — +5 µA VDD = VTXD = VSTBY = 0V.

P2562FD, VIO = 0V.

For MC

CANH = VCANL = 5 V.

V

IO pin. For the MCP2561FD, VIO is internally connected to VDD.

DS20005284A-page 10  2014 Microchip Technology Inc.

MCP2561/2FD

2.3 DC Characteristics (Continued)

Electrical Characteristics: Extended (E): TAMB = -40°C to +125°C and High (H): TAMB = -40°C to +150°C; 

DD = 4.5V to 5.5V, VIO = 1.8V to 5.5V (Note 2), RL = 60, CL = 100 pF; unless otherwise specified.

V

Characteristic Sym Min Typ Max Units Conditions

COMMON MODE STABILIZATION OUTPUT (SPLIT)

Output Voltage Vo 0.3VDD 0.5VDD 0.7VDD V Normal mode; 

SPLIT = -500 µA to +500 µA

I

DD 0.5VDD 0.55VDD V Normal mode; RL  1 M

0.45V

Leakage Current I

DIGITAL INPUT PINS (T

XD, STBY)

High-Level Input Voltage V

Low-Level Input Voltage V

High-Level Input Current I

TXD: Low-Level Input Current I

STBY: Low-Level Input Current I

RECEIVE DATA (R

XD) OUTPUT

High-Level Output Voltage V

Low-Level Output Voltage V

L

IH

IL

IH

IL(TXD)

IL(STBY)

OH

OL

THERMAL SHUTDOWN

Shutdown 

T

J(SD)

Junction Temperature

Shutdown 

T

J(HYST)

Temperature Hysteresis

Note 1: Characterized; not 100% tested.

2: Only MCP2562FD has V

IO pin. For the MCP2561FD, VIO is internally connected to VDD.

3: -12V to 12V is ensured by characterization, tested from -2V to 7V.

-5 — +5 µA Standby mode; 

SPLIT = -24V to + 24V 

V
(ISO 11898: -12V ~ +12V)

0.7VIO — VIO + 0.3 V

-0.3 — 0.3VIO V

-1 — +1 µA

-270 -150 -30 µA

-30 — -1 µA

VDD - 0.4 — — V IOH = -2 mA (MCP2561FD);

typical -4 mA

IO - 0.4 — — IOH = -1 mA (MCP2562FD);

V

typical -2 mA

— — 0.4 V IOL = 4 mA; typical 8 mA

165 175 185 °C -12V < V(CANH, CANL) < +12V,

(Note 1)

20 — 30 °C -12V < V(CANH, CANL) < +12V,

(Note 1)

 2014 Microchip Technology Inc. DS20005284A-page 11

MCP2561/2FD

CANH, CANL, SPLIT

Time

CANH

CANL

SPLIT

Normal Mode Standby Mode

Recessive RecessiveDominant

SPLIT

floating

CANL

CANH

V

DD

/2

R

XD

V

DD

Normal

Standby

Mode

FIGURE 2-2: PHYSICAL BIT REPRESENTATION AND SIMPLIFIED BIAS IMPLEMENTATION

DS20005284A-page 12  2014 Microchip Technology Inc.

MCP2561/2FD

VDD/2

CL

RL

Pin Pin

V

SS

VSS

CL

RL = 464 

C

L = 50 pF for all digital pins

Load Condition 1 Load Condition 2

2.4 AC Characteristics

Electrical Characteristics: Extended (E): TAMB = -40°C to +125°C and High (H): TAMB = -40°C to +150°C; 

DD = 4.5V to 5.5V, VIO = 1.8V to 5.5V (Note 2), RL = 60CL = 100 pF; unless otherwise specified.

V

Param.

No.

1 t

2 fBIT Bit Frequency 14.4 — 5000 kHz

3 tTXD-BUSON Delay TXD Low to Bus Dominant — 65 — ns (Note 1)

4 t

5 tBUSON-RXD Delay Bus Dominant to RXD — 60 — ns (Note 1)

6 tBUSOFF-RXD Delay Bus Recessive to RXD — 65 — ns (Note 1)

7 t

8a

8b

8c

9 t

10 t

11 t

12 tPDTR Permanent Dominant Timer Reset — 100 — ns The shortest Recessive

Note 1: C

Sym Characteristic Min Typ Max Units Conditions

BIT Bit Time 0.2 — 69.44 µs

TXD-BUSOFF Delay TXD High to Bus Recessive — 90 — ns (Note 1)

TXD - RXD Propagation Delay TXD to RXD — 90 120 ns

— 120 180 ns RL = 120CL = 200 pF,

(Note 1)

BIT(RXD),2M Recessive bit time on RXD -

t

2 Mbps, Loop Delay Symmetry

450 485 550

400 460 550

BIT(TXD) = 500 ns,

t

ns

see Figure 2-10

BIT(TXD) = 500 ns,

t

ns

see Figure 2-10, 
RL = 120CL = 200 pF,
(Note 1)

BIT(RXD),5M Recessive bit time on RXD -

t

5 Mbps, Loop Delay Symmetry

BIT(RXD),8M Recessive bit time on RXD -

t

8 Mbps, Loop Delay Symmetry

160 185 220

85 105 140

BIT(TXD) = 200 ns,

t

ns

see Figure 2-10

BIT(TXD) = 120 ns,

t

ns

see Figure 2-10
(Note 1)

FLTR(WAKE) Delay Bus Dominant to RXD 

0.5 1 4 µs Standby mode

(Standby mode)

WAKE Delay Standby 

5 25 40 µs Negative edge on STBY

to Normal Mode

PDT Permanent Dominant Detect Time — 1.25 — ms TXD = 0V

pulse on T
to reset Permanent
Dominant Timer

haracterized, not 100% tested.

XD or CAN bus

FIGURE 2-3: TEST LOAD CONDITIONS

 2014 Microchip Technology Inc. DS20005284A-page 13

MCP2561/2FD

GND

RXD

SPLIT

T

XD

RL

CL

15 pF

CANH

CANL

CAN

Transceiver

0.1 µF

V

DD

STBY

Note: On MCP2562FD, VIO is connected to VDD.

GND

RXD

SPLIT

T

XD

RL

500 pF

500 pF

Note 1: On MCP2562FD, VIO is connected to VDD.

2: The wave forms of the applied transients shall be in accordance with ISO-7637,

Part 1, test pulses 1, 2, 3a and 3b.

CANH

CANL

CAN

Transceiver

Transient

Generator

STBY

VOH

VOL

0.5 0.9

V

DIFF (h)(i)

VDIFF (V)

RXD (receive data
output voltage)

VDIFF (r)(i)

VDIFF (d)(i)

FIGURE 2-4: TEST CIRCUIT FOR ELECTRICAL CHARACTERISTICS

FIGURE 2-5: TEST CIRCUIT FOR AUTOMOTIVE TRANSIENTS

FIGURE 2-6: HYSTERESIS OF THE RECEIVER

DS20005284A-page 14  2014 Microchip Technology Inc.

2.5 Timing Diagrams and Specifications

3

7

4

7

0V

V

DD

TXD (transmit data
input voltage)

VDIFF (CANH,
CANL differential
voltage)

R

XD (receive data

output voltage)

5

6

VTXD = VDD

10

0V

V

DD

VSTBY

VCANH/VCANL

Input Voltage

0

V

DD/2

11

12

TXD

VDIFF (VCANH-VCANL)

Driver is off

Minimum pulse width until CAN bus goes to Dominant state after the falling edge.

FIGURE 2-7: TIMING DIAGRAM FOR AC CHARACTERISTICS

MCP2561/2FD

FIGURE 2-8: TIMING DIAGRAM FOR W

AKEUP FROM STANDBY

FIGURE 2-9: PERMANENT DOMINANT TIMER RESET DETECT

 2014 Microchip Technology Inc. DS20005284A-page 15

MCP2561/2FD

TXD

5*tBIT(TXD)

tBIT(TXD)

tBIT(RXD)

RXD

8

Note: The bit time of a recessive bit after five dominant bits is measured on the RXD pin. Due

to asymmetry of the loop delay, and the CAN transceiver not being a push pull driver,
the recessive bits tend to shorten.

FIGURE 2-10: TIMING DIAGRAM FOR LOOP DELAY SYMMETRY

2.6 Thermal Specifications

Parameter Symbol Min Typ Max Units Test Conditions

Temperature Ranges

Specified Temperature Range T

Operating Temperature Range T

Storage Temperature Range TA -65 — +155 C

Thermal Package Resistances

Thermal Resistance, 8L-DFN 3x3 

Thermal Resistance, 8L-PDIP JA — 89.3 — C/W

Thermal Resistance, 8L-SOIC JA — 149.5 — C/W

A -40 — +125 C

-40 — +150

A -40 — +150 C

JA — 56.7 — C/W

DS20005284A-page 16  2014 Microchip Technology Inc.

3.0 PACKAGING INFORMATION

8-Lead PDIP (300 mil)

Example:

8-Lead SOIC (150 mil)

Example:

Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
* This package is Pb-free. The Pb-free JEDEC designator ( )

can be found on the outer packaging for this package.

Note: In the event the full Microchip part number cannot be marked on one line, it will

be carried over to the next line, thus limiting the number of available
characters for customer-specific information.

3

e

3

e

Example:

8-Lead DFN (3x3 mm)

8-Lead PDIP (300 mil) Example:

XXXXXXXX
XXXXXNNN

YYWW

2561FD

E/P ^^256

1307

3

e

Part Number Code

MCP2561FD-E/MF DADY

MCP2561FDT-E/MF DADY

MCP2561FD-H/MF DADZ

MCP2561FDT-H/MF DADZ

MCP2562FD-E/MF DAEA

MCP2562FDT-E/MF DAEA

MCP2562FD-H/MF DAEB

MCP2562FDT-H/MF DAEB

DADY

1307

256

NNN

2561FDE

SN ^^1246

256

3

e

OR

2561FDH

SN ^^1246

256

3

e

OR

2561FD

H/P ^^256

1307

3

e

3.1 Package Marking Information

MCP2561/2FD

 2014 Microchip Technology Inc. DS20005284A-page 17

MCP2561/2FD

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

DS20005284A-page 18  2014 Microchip Technology Inc.

MCP2561/2FD

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

 2014 Microchip Technology Inc. DS20005284A-page 19

MCP2561/2FD

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

DS20005284A-page 20  2014 Microchip Technology Inc.

B

A

For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

Note:

Microchip Technology Drawing No. C04-018D Sheet 1 of 2

8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP]

eB

E

A

A1

A2

L

8X b

8X b1

D

E1

c

C

PLANE

.010 C

12

N

NOTE 1

TOP VIEW

END VIEWSIDE VIEW

e

MCP2561/2FD

 2014 Microchip Technology Inc. DS20005284A-page 21

MCP2561/2FD

Microchip Technology Drawing No. C04-018D Sheet 2 of 2

For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

Note:

8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP]

Units INCHES

Dimension Limits MIN NOM MAX
Number of Pins N 8
Pitch

e

.100 BSC
Top to Seating Plane A - - .210
Molded Package Thickness A2 .115 .130 .195
Base to Seating Plane A1 .015
Shoulder to Shoulder Width E .290 .310 .325
Molded Package Width E1 .240 .250 .280
Overall Length D .348 .365 .400
Tip to Seating Plane L .115 .130 .150
Lead Thickness

c

.008 .010 .015
Upper Lead Width b1 .040 .060 .070
Lower Lead Width

b

.014 .018 .022
Overall Row Spacing eB - - .430

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

3.

1.

protrusions shall not exceed .010" per side.

2.

4.

Notes:

§

--

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or

Pin 1 visual index feature may vary, but must be located within the hatched area.

§ Significant Characteristic

Dimensioning and tolerancing per ASME Y14.5M

e

DATUM A DATUM A

e

b

e
2

b

e
2

ALTERNATE LEAD DESIGN

(VENDOR DEPENDENT)

DS20005284A-page 22  2014 Microchip Technology Inc.

MCP2561/2FD

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

 2014 Microchip Technology Inc. DS20005284A-page 23

MCP2561/2FD

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

DS20005284A-page 24  2014 Microchip Technology Inc.

MCP2561/2FD

 !"#$%

& !"#$%&"'""($)%

*++&&&!!+$

 2014 Microchip Technology Inc. DS20005284A-page 25

MCP2561/2FD

NOTES:

DS20005284A-page 26  2014 Microchip Technology Inc.

APPENDIX A: REVISION HISTORY

Revision A (March 2014)

Original Release of this Document.

MCP2561/2FD

 2014 Microchip Technology Inc. DS20005284A-page 27

MCP2561/2FD

NOTES:

DS20005284A-page 28  2014 Microchip Technology Inc.

MCP2561/2FD

PART NO. -X /XX

PackageTemperature

Range

Device

Device: MCP2561FD:High-Speed CAN Transceiver with SPLIT

MCP2561FDT:High-Speed CAN Transceiver with SPLIT

(Tape and Reel) (DFN and SOIC only)

MCP2562FD:High-Speed CAN Transceiver with V

IO

MCP2562FDT:High-Speed CAN Transceiver with VIO

(Tape and Reel) (DFN and SOIC only)

Temperature
Range:

E = -40°C to +125°C (Extended)
H = -40°C to +150°C (High)

Package: MF = Plastic Dual Flat, No Lead Package -

3x3x0.9 mm Body, 8-lead
P = Plastic Dual In-Line - 300 mil Body, 8-lead
SN = Plastic Small Outline - Narrow, 3.90 mm Body, 

8-lead

Examples:

a) MCP2561FD-E/MF:Extended Temperature,

8LD 3x3 DFN package.

b) MCP2561FDT-E/MF:Tape and Reel,

Extended Temperature,
8LD 3x3 DFN package.

c) MCP2561FD-E/P: Extended Temperature,

8LD PDIP package.

d) MCP2561FD-E/SN:Extended Temperature,

8LD SOIC package.

e) MCP2561FDT-E/SN:Tape and Reel,

Extended Temperature,
8LD SOIC package.

a) MCP2561FD-H/MF:High Temperature,

8LD 3x3 DFN package.

b) MCP2561FDT-H/MF:Tape and Reel,

High Temperature,
8LD 3x3 DFN package.

c) MCP2561FD-H/P: High Temperature,

8LD PDIP package.

d) MCP2561FD-H/SN:High Temperature,

8LD SOIC package.

e) MCP2561FDT-H/SN:Tape and Reel,

High Temperature,
8LD SOIC package.

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, contact the factory or one of the sales offices listed on the back page.

 2014 Microchip Technology Inc. DS20005284A-page 29

MCP2561/2FD

NOTES:

DS20005284A-page 30  2014 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices:

YSTEM

CERTIFIED BY DNV

== ISO/TS 16949 ==

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, dsPIC,
FlashFlex, K
PICSTART, PIC
and UNI/O are registered trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.

FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MTP, SEEVAL and The Embedded Control Solutions
Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A.

Silicon Storage Technology is a registered trademark of
Microchip Technology Inc. in other countries.

Analog-for-the-Digital Age, Application Maestro, BodyCom,
chipKIT, chipKIT logo, CodeGuard, dsPICDEM,
dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
Programming, ICSP, Mindi, MiWi, MPASM, MPF, MPLAB
Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O,
Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA
and Z-Scale are trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.

GestIC and ULPP are registered trademarks of Microchip
Technology Germany II GmbH & Co. KG, a subsidiary of
Microchip Technology Inc., in other countries.

All other trademarks mentioned herein are property of their
respective companies.

© 2014, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.

Printed on recycled paper.

ISBN: 978-1-63276-020-3

EELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,

32

logo, rfPIC, SST, SST Logo, SuperFlash

QUALITY MANAGEMENT S

 2014 Microchip Technology Inc. DS20005284A-page 31

Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.

®

MCUs and dsPIC® DSCs, KEELOQ

®

code hopping

Worldwide Sales and Service

AMERICAS

Corporate Office

2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: [phone]
Fax: [phone]
Technical Support:
http://www.microchip.com/
support
Web Address:
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EUROPE

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03/25/14

DS20005284A-page 32  2014 Microchip Technology Inc.