Datasheet MCP1403, MCP1404, MCP1405 Datasheet

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MCP1403/4/5

8-Pin DFN

(2)

IN A

GND

IN B

8-Pin

1 2 3 4

OUT A

OUT B

IN A

GND

IN B

Note 1: Duplicate pins must both be connected for

proper operation.

2: Exposed pad of the DFN package is electrically

isolated.

MCP1403

MCP1404

NC OUT A

OUT B

MCP1405

NC OUT A

OUT B

1 2 3 4 5 6 7 8

13 12 11

IN A

NC GND GND

IN B

OUT A V

OUT B OUT B NC

OUT A

15 14

16-Pin SOIC

OUT A V

OUT B OUT B NC

OUT A

OUT A V

OUT B OUT B NC

OUT A

MCP1403

MCP1404

MCP1405

OUT A

OUT B

MCP1403

MCP1404

OUT A

OUT B

MCP1405

OUT A

OUT B

PDIP/SOIC

4.5A Dual High-Speed Power MOSFET Drivers

Features

• High Peak Output Current: 4.5A (typ.)

• Low Shoot-Through/Cross-Conduction Current in Output Stage

• Wide Input Supply Voltage Operating Range:

- 4.5V to 18V

• High Capacitive Load Drive Capability:

- 2200 pF in 15 ns

- 5600 pF in 34 ns

• Short Delay Times: 40 ns (typ.)

• Low Supply Current:

- With Logic ‘1’ Input – 1.0 mA (typ.)

- With Logic ‘0’ Input – 150 µA (typ.)

• Latch-Up Protected: Will Withstand 1.5A Reverse Current

• Logic Input Will Withstand Negative Swing Up To 5V

• Packages: 8-Pin SOIC, PDIP, 8-Pin 6x5 DFN, and 16-Pin SOIC

Applications

• Switch Mode Power Supplies

• Pulse Transformer Drive

• Line Drivers

• Motor and Solenoid Drive

General Description

The MCP1403/4/5 are a family of dual-inverting, dualnon-inverting, or complimentary output drivers. They can delivery high peak currents of 4.5A typically into capacitive loads. These devices also feature low shootthrough current, matched rise/fall times and propagation delays.

The MCP1403/4/5 drivers operate from a 4.5V to 18V single power supply and can easily charge and discharge 2200 pF gate capacitance in under 15 ns (typ). They provide low enough impedances in both the on and off states to ensure the MOSFETs intended state will not be affected, even by large transients. The input to the MCP1403/4/5 may be driven directly from either TTL or CMOS (3V to 18V).

The MCP1403/4/5 dual-output 4.5A driver family is offered in both surface-mount and pin-through-hole packages with a -40 The low thermal resistance of the thermally enhanced DFN package allows for greater power dissipation capability for driving heavier capacitive or resistive loads.

These devices are highly latch-up resistant under any conditions within their power and voltage ratings. They are not subject to damage when up to 5V of noise spiking (of either polarity) occurs on the ground pin. All terminals are fully protect against Electrostatic Discharge (ESD) up to 4 kV.

C to +125oC temperature rating.

Package Types

MCP1403/4/5

Effective

Input C = 20 pF

MCP1403 Dual Inverting MCP1404 Dual Non-inverting

Input

GND

300 mV

4.7V

Inverting

Non-inverting

Note 1: Unused inputs should be grounded.

730 µA

Output

(Each Input)

MCP1405 Inverting / Non-inverting

Functional Block Diagram

(1)

MCP1403/4/5

1.0 ELECTRICAL

CHARACTERISTICS

Absolute Maximum Ratings †

Supply Voltage................................................................+20V

Input Voltage...............................(V

Input Current (V

)................................................50 mA

IN>VDD

+ 0.3V) to (GND – 5V)

† Notice: Stresses above those listed under "Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational sections of this specification is not intended. Exposure to maximum rating conditions for extended periods may affect device reliability.

DC CHARACTERISTICS (NOTE 2)

Electrical Specifications: Unless otherwise indicated, TA = +25°C, with 4.5V ≤ VDD ≤ 18V.

Parameters Sym Min Typ Max Units Conditions

Input

Logic ‘1’, High Input Voltage V Logic ‘0’, Low Input Voltage V Input Current I Input Voltage V

Output

High Output Voltage V Low Output Voltage V Output Resistance, High R Output Resistance, Low R Peak Output Current I Latch-Up Protection With-

REV

stand Reverse Current

Switching Time (Note 1)

Rise Time t

Fall Time t

Delay Time t Delay Time t

Power Supply

Supply Voltage V Power Supply Current I

Note 1: Switching times ensured by design.

2: Tested during characterization, not production tested.

2.4 1.5 — V —1.30.8V –1 — 1 µA 0V ≤ VIN ≤ V

-5 — VDD+0.3 V

VDD – 0.025 — — V DC Test

— — 0.025 V DC Test —2.23.0Ω I —2.83.5Ω I —4.5—AV

OUT

— >1.5 — A Duty cycle ≤ 2%, t ≤ 300 µsec.

—1528nsFigure 4-1, Figure 4-2

CL = 2200 pF

—1828nsFigure 4-1, Figure 4-2

= 2200 pF

—4048nsFigure 4-1, Figure 4-2 —4048nsFigure 4-1, Figure 4-2

4.5 — 18.0 V —1.02.0mAV

= 3V (Both Inputs)

— 0.15 0.25 mA VIN = 0V (Both Inputs)

= 10 mA, VDD = 18V = 10 mA, VDD = 18V

= 18V (Note 2)

MCP1403/4/5

DC CHARACTERISTICS (OVER OPERATING TEMPERATURE RANGE)

Electrical Specifications: Unless otherwise indicated, operating temperature range with 4.5V ≤ VDD ≤ 18V.

Parameters Sym Min Typ Max Units Conditions

Input

Logic ‘1’, High Input Voltage V Logic ‘0’, Low Input Voltage V Input Current I

Output

High Output Voltage V Low Output Voltage V Output Resistance, High R Output Resistance, Low R

OHVDD

Switching Time (Note 1)

Rise Time t

Fall Time t

Delay Time t Delay Time t

Power Supply

Power Supply Current I

Note 1: Switching times ensured by design.

2: Tested during characterization, not production tested.

2.4 — — V ——0.8V

–10 — +10 µA 0V ≤ VIN ≤ V

– 0.025 — — V DC TEST

— — 0.025 V DC TEST —3.16.0Ω I —3.77Ω I

= 10 mA, VDD = 18V

OUT

= 10 mA, VDD = 18V

OUT

—2540nsFigure 4-1, Figure 4-2

CL = 2200 pF

—2540nsFigure 4-1, Figure 4-2

CL = 2200 pF

—5065nsFigure 4-1, Figure 4-2 —5065nsFigure 4-1, Figure 4-2

— —

2.0

0.2

3.0

0.3

mA VIN = 3V (Both Inputs)

= 0V (Both Inputs)

TEMPERATURE CHARACTERISTICS

Electrical Specifications: Unless otherwise noted, all parameters apply with 4.5V ≤ V

Parameters Sym Min Typ Max Units Conditions

Temperature Ranges

Specified Temperature Range T Maximum Junction Temperature T Storage Temperature Range T

Package Thermal Resistances

Thermal Resistance, 8L-6x5 DFN θ

Thermal Resistance, 8L-PDIP θ Thermal Resistance, 8L-SOIC θ Thermal Resistance, 16L-SOIC θ

–40 — +125 °C

— — +150 °C

–65 — +150 °C

— 33.2 — °C/W Typical four-layer board with

—125 —°C/W —155 —°C/W — 155 — °C/W 4-Layer JC51-7 Standard

≤ 18V.

vias to ground plane

Board, Natural Convection

MCP1403/4/5

100

4 6 8 10 12 14 16 18

Supply Voltage (V)

Rise Time (ns)

6800 pF

4700 pF

2200 pF

1800 pF

1000 10000

Capacitive Load (pF)

Rise Time (ns)

18V

12V

-40 -25 -10 5 20 35 50 65 80 95 110 125

Temperature (

Time (ns)

FALL

RISE

LOAD

= 1800 pF

100

4 6 8 10 12 14 16 18

Supply Voltage (V)

Fall Time (ns)

6800 pF

4700 pF

2200 pF

1800 pF

100

1000 10000

Capacitive Load (pF)

Fall Time (ns)

18V

12V

110

135

160

2345678910

Input Amplitude (V)

Propagation Delay (ns)

VDD = 12V

LOAD

= 1800 pF

2.0 TYPICAL PERFORMANCE CURVES

Note: The graphs and tables provided following this note are a statistical summary based on a limited number of

samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range.

Note: Unless otherwise indicated, TA = +25°C with 4.5V ≤ VDD ≤ 18V.

FIGURE 2-1: Rise Time vs. Supply Voltage.

FIGURE 2-2: Rise Time vs. Capacitive Load.

FIGURE 2-4: Fall Time vs. Supply Voltage.

FIGURE 2-5: Fall Time vs. Capacitive Load.

FIGURE 2-3: Rise and Fall Times vs. Temperature.

FIGURE 2-6: Propagation Delay vs. Input Amplitude.

MCP1403/4/5

100

4 6 8 10 12 14 16 18

Supply Voltage (V)

Propagation Delay (ns)

LOAD

= 1800 pF

-40 -25 -10 5 20 35 50 65 80 95 110 125

Temperature (

Propagation Delay (ns)

LOAD

= 1800 pF

0.1

0.2

0.3

0.4

0.5

4 6 8 1012141618

Supply Voltage (V)

Quiescent Current (mA)

Both Inputs = 1

Both Inputs = 0

0.1

0.2

0.3

0.4

0.5

-40 -25 -10 5 20 35 50 65 80 95 110 125

Temperature (

Quiescent Current (mA)

Both Inputs = 1

Both Inputs = 0

4 6 8 10 12 14 16 18

Supply Voltage (V)

OUT-HI

(

)

TJ = +150oC

TJ = +25oC

VIN = 5V (MCP1404) V

= 0V (MCP1403)

4 6 8 10 12 14 16 18

Supply Voltage (V)

OUT-LO

(

)

TJ = +150oC

TJ = +25oC

VIN = 0V (MCP1404) V

= 5V (MCP1403)

Typical Performance Curves (Continued)

Note: Unless otherwise indicated, TA = +25°C with 4.5V ≤ VDD ≤ 18V.

FIGURE 2-7: Propagation Delay Time vs. Supply Voltage.

FIGURE 2-8: Propagation Delay Time vs. Temperature.

FIGURE 2-10: Quiescent Current vs. Temperature.

FIGURE 2-11: Output Resistance (Output High) vs. Supply Voltage.

FIGURE 2-9: Quiescent Current vs. Supply Voltage.

FIGURE 2-12: Output Resistance (Output Low) vs. Temperature.

Typical Performance Curves (Continued)

100

100 1000 10000

Capacitive Load (pF)

Supply Current (mA)

650 kHz

VDD = 18V

50 kHz

100 kHz

200 kHz

400 kHz

100

120

100 1000 10000

Capacitive Load (pF)

Supply Current (mA)

2 MHz

VDD = 12V

500 kHz

200 kHz

100 kHz

1 MHz

100

120

100 1000 10000

Capacitive Load (pF)

Supply Current (mA)

3.5 MHz

VDD = 6V

1 MHz

500 kHz

200 kHz

2 MHz

10 100 1000

Frequency (kHz)

Supply Current (mA)

VDD = 18V

6,800 pF

100 pF

2,200 pF

4,700 pF

100

120

140

10 100 1000 10000

Frequency (kHz)

Supply Current (mA)

VDD = 12V

6,800 pF

100 pF

2,200 pF

4,700 pF

100

120

140

10 100 1000 10000

Frequency (kHz)

Supply Current (mA)

VDD = 6V

6,800 pF

100 pF

2,200 pF

4,700 pF

Note: Unless otherwise indicated, TA = +25°C with 4.5V ≤ VDD ≤ 18V.

MCP1403/4/5

FIGURE 2-13: Supply Current vs. Capacitive Load.

FIGURE 2-14: Supply Current vs. Capacitive Load.

FIGURE 2-16: Supply Current vs. Frequency.

FIGURE 2-17: Supply Current vs. Frequency.

FIGURE 2-15: Supply Current vs. Capacitive Load.

FIGURE 2-18: Supply Current vs. Frequency.

MCP1403/4/5

1.00E-09

1.00E-08

1.00E-07

1.00E-06

4 6 8 10 12 14 16 18

Supply Voltage (V)

Crossover Energy (A*sec)

-6

-7

-8

-9

Note: The values on this graph represent the

loss seen by both drivers in a package during one complete cycle. For a single driver, divide the stated value by 2. For a single transition of a single driver divide the stated value by 4.

Typical Performance Curves (Continued)

Note: Unless otherwise indicated, TA = +25°C with 4.5V ≤ VDD ≤ 18V.

FIGURE 2-19: Crossover Energy vs. Supply Voltage.

3.0 PIN DESCRIPTIONS

The descriptions of the pins are listed in Table 3-1.

MCP1403/4/5

TABLE 3-1: PIN FUNCTION TABLE

8-Pin PDIP SOIC

1 1 1 NC No Connection 2 2 2 IN A Control Input for Output A

— — 3 NC No Connection

3 3 4 GND Ground — — 5 GND Ground — — 6 NC No Connection

4 4 7 IN B Control Input for Output B — — 8 NC No Connection — — 9 NC No Connection

5 5 10 OUT B Output B — — 11 OUT B Output B

6612V ——13V

7 7 14 OUT A Output A — — 15 OUT A Output A

8 8 16 NC No Connection — PAD — NC Exposed Metal Pad

Note 1: Duplicate pins must be connected for proper operation.

8-Pin

DFN

16-Pin

SOIC

Symbol Description

(1)

Supply Input Supply Input

3.1 Supply Input (VDD)

VDD is the bias supply input for the MOSFET driver and has a voltage range of 4.5V to 18V. This input must be decoupled to ground with a local capacitor. This bypass capacitor provides a localized low-impedance path for the peak currents that are to be provided to the load.

3.2 Control Inputs A and B

The MOSFET driver input is a high-impedance, TTL/ CMOS-compatible input. The input also has hysteresis between the high and low input levels, allowing them to be driven from slow rising and falling signals, and to provide noise immunity.

3.3 Ground (GND)

Ground is the device return pin. The ground pin should have a low impedance connection to the bias supply source return. High peak currents will flow out the ground pin when the capacitive load is being discharged.

3.4 Outputs A and B

Outputs A and B are CMOS push-pull output that is capable of sourcing and sinking 4.5A of peak current (VDD = 18V). The low output impedance ensures the gate of the external MOSFET will stay in the intended state even during large transients. These output also has a reverse current latch-up rating of 1.5A.

3.5 Exposed Metal Pad

The exposed metal pad of the DFN package is not internally connected to any potential. Therefore, this pad can be connected to a ground plane or other copper plane on a printed circuit board to aid in heat removal from the package.

MCP1403/4/5

0.1 µF

+5V

10%

90%

10%

90%

10%

90%

18V

1µF

MCP1403

CL = 2200 pF

Input

Output

VDD = 18V

Ceramic

Input

(1/2 MCP1405)

90%

Input

Output

10%

+5V

18V

90%

0.1 µF

1µF

MCP1404

CL = 2200 pF

Input Output

= 18V

Ceramic

Input

(1/2 MCP1405)

4.0 APPLICATION INFORMATION

4.1 General Information

MOSFET drivers are high-speed, high current devices which are intended to source/sink high peak currents to charge/discharge the gate capacitance of external MOSFETs or IGBTs. In high frequency switching power supplies, the PWM controller may not have the drive capability to directly drive the power MOSFET. A MOSFET driver like the MCP1403/4/5 family can be used to provide additional source/sink current capability.

4.2 MOSFET Driver Timing

The ability of a MOSFET driver to transition from a fully off state to a fully on state are characterized by the drivers rise time (tR), fall time (tF), and propagation delays

and tD2). The MCP1403/4/5 family of drivers can

typically charge and discharge a 2200 pF load capacitance in 15 ns along with a typical matched propagation delay of 40 ns. Figure 4-1 and Figure 4-2 show the test circuit and timing waveform used to verify the MCP1403/4/5 timing.

FIGURE 4-1: Inverting Driver Timing Waveform.

FIGURE 4-2: Non-Inverting Driver Timing Waveform.

4.3 Decoupling Capacitors

Careful layout and decoupling capacitors are highly recommended when using MOSFET drivers. Large currents are required to charge and discharge capacitive loads quickly. For example, 2.5A are needed to charge a 2200 pF load with 18V in 16 ns.

To operate the MOSFET driver over a wide frequency range with low supply impedance a ceramic and low ESR film capacitor are recommended to be placed in parallel between the driver V

and GND. A 1.0 µF low

ESR film capacitor and a 0.1 µF ceramic capacitor placed between

VDD and GND pins should be used.

These capacitors should be placed close to the driver to minimized circuit board parasitics and provide a local source for the required current.

4.4 PCB Layout Considerations

Proper PCB layout is important in a high current, fast switching circuit to provide proper device operation and robustness of design. PCB trace loop area and inductance should be minimized by the use of ground planes or trace under MOSFET gate drive signals, separate analog and power grounds, and local driver decoupling.

MCP1403/4/5

PLP

++=

Where:

= Total power dissipation

= Load power dissipation

= Quiescent power dissipation

= Operating power dissipation

× V

×=

Where:

f = Switching frequency C

= Total load capacitance

= MOSFET driver supply voltage

DIQL1 D–()×+×()VDD×=

Where:

= Quiescent current in the high state D = Duty cycle I

= Quiescent current in the low state

= MOSFET driver supply voltage

CC f× VDD×=

Where:

CC = Cross-conduction constant (A*sec) f = Switching frequency V

= MOSFET driver supply voltage

Placing a ground plane beneath the MCP1403/4/5 will help as a radiated noise shield as well as providing some heat sinking for power dissipated within the device.

4.5 Power Dissipation

The total internal power dissipation in a MOSFET driver is the summation of three separate power dissipation elements.

4.5.1 CAPACITIVE LOAD DISSIPATION

The power dissipation caused by a capacitive load is a direct function of frequency, total capacitive load, and supply voltage. The power lost in the MOSFET driver for a complete charging and discharging cycle of a MOSFET is:

4.5.2 QUIESCENT POWER DISSIPATION

The power dissipation associated with the quiescent current draw depends upon the state of the input pin. The MCP1403/4/5 devices have a quiescent current draw when both inputs are high of 1.0 mA (typ) and

0.15 mA (typ) when both inputs are low. The quiescent power dissipation is:

4.5.3 OPERATING POWER DISSIPATION

The operating power dissipation occurs each time the MOSFET driver output transitions because for a very short period of time both MOSFETs in the output stage are on simultaneously. This cross-conduction current leads to a power dissipation describes as:

MCP1403/4/5

XXXXXXXX XXXXXNNN

YYWW

8-Lead PDIP (300 mil)

Example:

MCP1403

E/P^^256

0648

8-Lead SOIC (150 mil)

Example:

256

MCP1405E

8-Lead DFN

Example

XXXXXXX XXXXXXX

XXYYWW

NNN

MCP1403

E/MF^^

0648

256

SN^^0648

Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( )

can be found on the outer packaging for this package.

Note: In the event the full Microchip part number cannot be marked on one line, it will

be carried over to the next line, thus limiting the number of available characters for customer-specific information.

NNN

XXXXXXXX

XXXXYYWW

16-Lead SOIC (300 mil)

Example:

XXXXXXXXXXX XXXXXXXXXXX

YYWWNNN

XXXXXXXXXXX

0648256

MCP1405

E/SO^^

5.0 PACKAGING INFORMATION

5.1 Package Marking Information (Not to Scale)

MCP1403/4/5

8-Lead Plastic Dual Flat, No Lead Package (MF) – 6x5 mm Body [DFN-S] PUNCH SINGULATED

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.

2. Package may have one or more exposed tie bars at ends.

3. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only.

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Units MILLIMETERS

Dimension Limits MIN NOM MAX Number of Pins N 8 Pitch e 1.27 BSC Overall Height A – 0.85 1.00 Molded Package Thickness A2 – 0.65 0.80 Standoff A1 0.00 0.01 0.05 Base Thickness A3 0.20 REF Overall Length D 4.92 BSC Molded Package Length D1 4.67 BSC Exposed Pad Length D2 3.85 4.00 4.15 Overall Width E 5.99 BSC Molded Package Width E1 5.74 BSC Exposed Pad Width E2 2.16 2.31 2.46 Contact Width b 0.35 0.40 0.47 Contact Length L 0.50 0.60 0.75 Contact-to-Exposed Pad K 0.20 – – Model Draft Angle Top φ – – 12°

NOTE 2

NOTE 1

EXPOSED

PAD

BOTTOM VIEW

TOP VIEW

Microchip Technology Drawing C04-113B

MCP1403/4/5

8-Lead Plastic Dual In-Line (P) – 300 mil Body [PDIP]

Notes:

1. Pin 1 visual index feature may vary, but must be located with the hatched area.

2. § Significant Characteristic.

3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side.

4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances.

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Units INCHES

Dimension Limits MIN NOM MAX Number of Pins N 8 Pitch e .100 BSC Top to Seating Plane A – – .210 Molded Package Thickness A2 .115 .130 .195 Base to Seating Plane A1 .015 – – Shoulder to Shoulder Width E .290 .310 .325 Molded Package Width E1 .240 .250 .280 Overall Length D .348 .365 .400 Tip to Seating Plane L .115 .130 .150 Lead Thickness c .008 . 010 .015 Upper Lead Width b1 .040 .060 .070 Lower Lead Width b .014 .018 .022 Overall Row Spacing § eB – – .430

NOTE 1

Microchip Technology Drawing C04-018B

MCP1403/4/5

8-Lead Plastic Small Outline (SN) – Narrow, 3.90 mm Body [SOIC]

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.

2. § Significant Characteristic.

3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.

4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimension, usually without tolerance, for information purposes only.

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Units MILLIMETERS

Dimension Limits MIN NOM MAX Number of Pins N 8 Pitch e 1.27 BSC Overall Height A – – 1.75 Molded Package Thickness A2 1.25 – – Standoff

A1 0.10 – 0.25 Overall Width E 6.00 BSC Molded Package Width E1 3.90 BSC Overall Length D 4.90 BSC Chamfer (optional) h 0.25 – 0.50 Foot Length L 0.40 – 1.27 Footprint L1 1.04 REF Foot Angle φ 0° – 8° Lead Thickness c 0.17 – 0.25 Lead Width b 0.31 – 0.51 Mold Draft Angle Top α 5° – 15° Mold Draft Angle Bottom β 5° – 15°

NOTE 1

12 3

Microchip Technology Drawing C04-057B

MCP1403/4/5

16-Lead Plastic Small Outline (SO) – Wide, 7.50 mm Body [SOIC]

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.

2. § Significant Characteristic.

3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.

4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only.

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Units MILLIMETERS

Dimension Limits MIN NOM MAX Number of Pins N 16 Pitch e 1.27 BSC Overall Height A – – 2.65 Molded Package Thickness A2 2.05 – – Standoff § A1 0.10 – 0.30 Overall Width E 10.30 BSC Molded Package Width E1 7.50 BSC Overall Length D 10.30 BSC Chamfer (optional) h 0.25 – 0.75 Foot Length L 0.40 – 1.27 Footprint L1 1.40 REF Foot Angle φ 0° – 8° Lead Thickness c 0.20 – 0.33 Lead Width b 0.31 – 0.51 Mold Draft Angle Top α 5° – 15° Mold Draft Angle Bottom β 5° – 15°

NOTE 1

123

Microchip Technology Drawing C04-102B

APPENDIX A: REVISION HISTORY

Revision B (May 2007)

• Page 13: Updated Package Outline Drawing

• Page 14: Updated Package Outline Drawing

• Page 15: Updated Package Outline Drawing

• Page 16: Updated Package Outline Drawing

• Page 17: Updated Revision History

• Page 19: Corrected Package Codes in Product Identification System

Revision A (December 2006)

• Original Release of this Document.

MCP1403/4/5

NOTES:

MCP1403/4/5

Device: MCP1403: 4.5A Dual MOSFET Driver, Inverting

MCP1403T: 4.5A Dual MOSFET Driver, Inverting

(Tape and Reel) MCP1404: 4.5A Dual MOSFET Driver, Non-Inverting MCP1404T: 4.5A Dual MOSFET Driver, Non-Inverting

(Tape and Reel) MCP1405: 4.5A Dual MOSFET Driver, Complementary MCP1405T: 4.5A Dual MOSFET Driver, Complementary

(Tape and Reel)

Temperature Range: E = -40°C to +125°C

Package: * MF = Dual, Flat, No-Lead (6x5 mm Body), 8-lead

P = Plastic DIP, (300 mil body), 8-lead SN = Plastic SOIC (150 mil Body), 8-Lead SO = Plastic SOIC (Wide), 16-Lead

* All package offerings are Pb Free (Lead Free)

Examples:

a) MCP1403-E/SN: 4.5A Dual Inverting

MOSFET Driver, 8LD SOIC package.

b) MCP1403-E/P: 4.5A Dual Inverting

MOSFET Driver, 8LD PDIP package.

c) MCP1403-E/MF: 4.5A Dual Inverting

MOSFET Driver, 8LD DFN package.

d) MCP1403-E/SO: 4.5A Dual Inverting

MOSFET Driver, 16LD SOIC package.

a) MCP1404T-E/SN: Tape and Reel.

4.5A Dual Non-Inverting, MOSFET Driver, 8LD SOIC package,

b) MCP1404-E/P: 4.5A Dual Non-Inverting,

MOSFET Driver, 8LD PDIP package.

a) MCP1405-E/SN: 4.5A Dual Complementary,

MOSFET Driver, 8LD SOIC package.

b) MCP1405-E/P: 4.5A Dual Complementary,

MOSFET Driver, 8LD PDIP package.

c) MCP1405T-E/SO: Tape and Reel,

4.5A Dual Complementary MOSFET Driver, 16LD SOIC package.

PART NO. X XX

PackageTemperature

Range

Device

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

MCP1403/4/5

NOTES:

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, Accuron, dsPIC, K

EELOQ, KEELOQ logo, microID, MPLAB, PIC,

PICmicro, PICSTART, PRO MATE, rfPIC and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

AmpLab, FilterLab, Linear Active Thermistor, Migratable Memory, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.

All other trademarks mentioned herein are property of their respective companies.

Printed on recycled paper.

Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.

MCUs and dsPIC® DSCs, KEELOQ

code hopping

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12/08/06

Datasheet MCP1403, MCP1404, MCP1405 Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

FIGURE 2-1: Rise Time vs. Supply Voltage.

FIGURE 2-2: Rise Time vs. Capacitive Load.

FIGURE 2-4: Fall Time vs. Supply Voltage.

FIGURE 2-5: Fall Time vs. Capacitive Load.

FIGURE 2-3: Rise and Fall Times vs. Temperature.

FIGURE 2-6: Propagation Delay vs. Input Amplitude.

FIGURE 2-7: Propagation Delay Time vs. Supply Voltage.

FIGURE 2-8: Propagation Delay Time vs. Temperature.

FIGURE 2-10: Quiescent Current vs. Temperature.

FIGURE 2-11: Output Resistance (Output High) vs. Supply Voltage.

FIGURE 2-9: Quiescent Current vs. Supply Voltage.

FIGURE 2-12: Output Resistance (Output Low) vs. Temperature.

FIGURE 2-13: Supply Current vs. Capacitive Load.

FIGURE 2-14: Supply Current vs. Capacitive Load.

FIGURE 2-16: Supply Current vs. Frequency.

FIGURE 2-17: Supply Current vs. Frequency.

FIGURE 2-15: Supply Current vs. Capacitive Load.

FIGURE 2-18: Supply Current vs. Frequency.

FIGURE 2-19: Crossover Energy vs. Supply Voltage.

3.0 PIN DESCRIPTIONS

4.0 APPLICATION INFORMATION

FIGURE 4-1: Inverting Driver Timing Waveform.

FIGURE 4-2: Non-Inverting Driver Timing Waveform.

5.0 PACKAGING INFORMATION