Datasheet MCM72JG32SG66, MCM72JG64SG66 Datasheet (Motorola) [en, pt]

MCM72JG32•MCM72JG64

1

MOTOROLA FAST SRAM

Advance Information

256K and 512K Pipelined
BurstRAM Sedcondary Cache
Module for Pentium

The MCM72JG32 and MCM72JG64 are designed to provide a burstable, high
performance, 256K/512K L2 cache for the Pentium microprocessor in conjunc­tion with Intel’s Triton chip set. The modules are configured as 32K x 64 and
64K x 64 bits in a 160 pin card edge memory module. Each module uses four of
Motorola’s 5 V 32K x 18 or 64K x 18 BurstRAMs and one Motorola 5 V 32K x 8
FSRAM for the tag RAM.

Bursts can be initiated with either address status processor (ADSP

) or cache

address status (CADS

). Subsequent burst addresses are generated internal to

the BurstRAM by the cache burst advance (CADV

) input pin.

Write cycles are internally self timed and are initiated by the rising edge of the
clock (CLK0, CLK1) input. Eight write enables are provided for byte write control.

PD0 – PD4 map into the Triton chip set for auto–configuration of the cache
control.

Module family pinout supports 5 V and 3.3 V components. It is recommended
that all power supplies be connected.

These cache modules are plug and pin compatible with the
MCM64AF32SG15, a 256K byte asynchronous module also designed for the
Pentium microprocessor in conjunction with Intel’s Triton chip set.

• Pentium–Style Burst Counter on Chip

• Pipelined Data Out

• 160 Pin Card Edge Module

• Address Pipeline Supported by ADSP

Disabled with Ex

• All Cache Data and Tag I/Os are TTL Compatible

• Three State Outputs

• Byte Write Capability

• Fast Module Clock Rates: 66 MHz

• Fast SRAM Access Times:15 ns for Tag RAM

9 ns for Data RAMs

• Decoupling Capacitors for Each Fast Static RAM

• High Quality Multi–Layer FR4 PWB with Separate Power and Ground

Planes

• I/Os are 3.3 V Compatible on Data RAMs

• Burndy Connector, Part Number: CELP2X80SC3Z48

• Series 20 Ω Resistors for Noise Immunity

BurstRAM is a trademark of Motorola.
Pentium is a trademark of Intel Corp.

This document contains information on a new product. Motorola reserves the right to change or discontinue this product without notice.

160–LEAD CARD

EDGE

CASE 1113A–01

TOP VIEW

80

43

42

1

Order this document

by MCM72JG32/D

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Order this document

by MCM72JG32/D

MCM72JG32
MCM72JG64

REV 1
5/95

 Motorola, Inc. 1995

PIN ASSIGNMENT

160–PIN CARD EDGE MODULE

TOP VIEW

V

SS

TIO1
TIO7
TIO5
TIO3

(RSVD) NC

VCC5

(RSVD) NC

*(CAA4) CADV

V

SS

COE
CWE5
CWE7
CWE1

VCC5

CWE3

*(CAB3) NC
*(CALE) NC

V

SS

(RSVD) NC

A4
A6
A8

A10

VCC5

A17

V

SS

A9
A14
A15

(RSVD) NC

PD0
PD2
PD4
V

SS

CLK0

V

SS

DQ63
VCC5
DQ61
DQ59
DQ57

81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42

V

SS

TIO0
TIO2
TIO6
TIO4
NC (RSVD)
VCC3
TWE
CADS (CAA3)*
V

SS

CWE4
CWE6
CWE0
CWE2
VCC3
CCS

(CAB4)*

NC (GWE

)**

NC (BWE

)**

V

SS

A3
A7
A5
A11
A16
VCC3
NC (A18)

{

V

SS

A12
A13
ADSP
NC (ECS1, CS)
NC (ECS2

)
PD1
PD3
V

SS

CLK1
V

SS

DQ62
VCC3
DQ60
DQ58
DQ56

43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80

123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160

V

SS

DQ55
DQ53
DQ51
DQ49

V

SS

DQ47
DQ45
DQ43
VCC5
DQ41
DQ39
DQ37

V

SS

DQ35
DQ33
DQ31
VCC5
DQ29
DQ27
DQ25

V

SS

DQ23
DQ21
DQ19
VCC5
DQ17
DQ15
DQ13

V

SS

DQ11

DQ9
DQ7

VCC5

DQ5
DQ3
DQ1
V

SS

V

SS

DQ54
DQ52
DQ50
DQ48
V

SS

DQ46
DQ44
DQ42
VCC3
DQ40
DQ38
DQ36
V

SS

DQ34
DQ32
DQ30
VCC3
DQ28
DQ26
DQ24
V

SS

DQ22
DQ20
DQ18
VCC3
DQ16
DQ14
DQ12
V

SS

DQ10
DQ8
DQ6
VCC3
DQ4
DQ2
DQ0
V

SS

PIN NAMES

A3 – A18 Cache Address. . . . . . . . . . . . . . . . . . . . .

DQ0 – DQ63 Data Input/Output. . . . . . . . . . . . . . . .

CLK0, CLK1 Clock. . . . . . . . . . . . . . . . . . . . . . . . . . .

CWE0

– CWE7 Cache Write Enable. . . . . . . . . . .

BWE

** Byte Write Enable. . . . . . . . . . . . . . . . . . . . .

GWE

** Global Write Enable. . . . . . . . . . . . . . . . . . .

TIO0 – TIO7 Tag Input/Output. . . . . . . . . . . . . . . . .

TWE

Tag Write Enable. . . . . . . . . . . . . . . . . . . . . . . .

CADS

Cache Address Status. . . . . . . . . . . . . . . . .

ADSP

Address Status Processor. . . . . . . . . . . . . . .

CADV

Cache Burst Advance. . . . . . . . . . . . . . . . . .

COE

Cache Output Enable. . . . . . . . . . . . . . . . . . . .

CCS

Cache Chip Select. . . . . . . . . . . . . . . . . . . . . . .

RSVD Reserved for Future Use. . . . . . . . . . . . . . .

PD0 – PD4 Presence Detect. . . . . . . . . . . . . . . . . .

VCC5 + 5 V Power Supply. . . . . . . . . . . . . . . . . . . . .

VCC3 + 3.3 V Power Supply. . . . . . . . . . . . . . . . . . .

V

SS

Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

NC No Connect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

NOTES:

* Signals in parentheses indicate pin descriptions for asynchronous Triton

chip set module.

** Signals in parentheses will be implemented in future burstable Triton modules.

{

NC for MCM72JG32, A18 for MCM72JG64.

MCM72JG32•MCM72JG64
2

MOTOROLA FAST SRAM

PRESENCE DETECT TABLE

Cache Size and

Functionality

Module PD4 PD3 PD2 PD1 PD0

256K Async MCM64AF32 V

SS

NC V

SS

V

SS

NC

512K Async — V

SS

V

SS

NC V

SS

NC

256K Burst — V

SS

NC V

SS

NC V

SS

256K Pipe Burst MCM72JG32 V

SS

NC V

SS

NC NC

512K Burst — V

SS

V

SS

NC NC V

SS

512K Pipe Burst MCM72JG64 V

SS

V

SS

NC NC NC

512K 2–Bank

Burst

— V

SS

V

SS

NC V

SS

V

SS

MCM72JG32•MCM72JG64

3

MOTOROLA FAST SRAM

MCM72JG32 MODULE BLOCK DIAGRAM

A18 – NC

CCS

CADV

ADSP
CADS

CLK0

COE

A3 – A17

LW

MCM67J518

ADV

K
G

E

DQ0 – DQ7

DQ8

UW

ADSP
ADSC

DQ9 – DQ16

DQ17

A0 – A14

LW

MCM67J518

ADV

K
G

E

DQ0 – DQ7

DQ8

UW

ADSP
ADSC

DQ9 – DQ16

DQ17

A0 – A14

LW

MCM67J518

ADV

K
G

E

DQ0 – DQ7

DQ8

UW

ADSP
ADSC

DQ9 – DQ16

DQ17

A0 – A14

LW

MCM67J518

ADV

K
G

E

DQ0 – DQ7

DQ8

UW

ADSP
ADSC

DQ9 – DQ16

DQ17

DQ0 – DQ7

DQ8– DQ15

CWE0

CWE1

8

8

A0 – A14

A0 – A12

E

DQ0 – DQ7

A13

W

A14

G

32K x 8

CLK1

TIO0 – TIO7

A5 – A17

TWE

15

13

DQ16 – DQ23

DQ24– DQ31

CWE2

CWE3

8

8

DQ32 – DQ39

DQ40– DQ47

CWE4

CWE5

8

8

DQ48 – DQ55

DQ56– DQ63

CWE6

CWE7

8

8

PD2

PD0 – NC
PD1 – NC

PD4

PD3 – NC

MCM72JG32•MCM72JG64
4

MOTOROLA FAST SRAM

MCM72JG64 MODULE BLOCK DIAGRAM

CCS

CADV

ADSP
CADS

CLK0

COE

A3 – A18

LW

MCM67J618

ADV

K
G

E

DQ0 – DQ7

DQ8

UW

ADSP
ADSC

DQ9 – DQ16

DQ17

A0 – A15

LW

MCM67J618

ADV

K
G

E

DQ0 – DQ7

DQ8

UW

ADSP
ADSC

DQ9 – DQ16

DQ17

A0 – A15

LW

MCM67J618

ADV

K
G

E

DQ0 – DQ7

DQ8

UW

ADSP
ADSC

DQ9 – DQ16

DQ17

A0 – A15

LW

MCM67J618

ADV

K
G

E

DQ0 – DQ7

DQ8

UW

ADSP
ADSC

DQ9 – DQ16

DQ17

DQ0 – DQ7

DQ8– DQ15

CWE0

CWE1

8

8

A0 – A15

A0 – A13

E

DQ0 – DQ7

W

A14

G

CLK1

TIO0 – TIO7

A5 – A18

TWE

16

14

DQ16 – DQ23

DQ23– DQ31

CWE2

CWE3

8

8

DQ32 – DQ39

DQ40– DQ47

CWE4

CWE5

8

8

DQ48 – DQ55

DQ56– DQ63

CWE6

CWE7

8

8

PD2 – NC

PD0 – NC
PD1 – NC

PD4

PD3

32K x 8

MCM72JG32•MCM72JG64

5

MOTOROLA FAST SRAM

PIN DESCRIPTIONS

160–Lead Card Edge Pin Locations Symbol

Type Description

20, 21, 22, 23, 24, 28, 29,

101, 102, 103, 104, 106, 108, 109, 110

A3 – A18 Input Address Inputs: These inputs are registered into data RAMs and must

meet setup and hold times. The tag RAM addresses are not registered.

36, 116 CLK0,

CLK1

Input Clock: This signal registers the address, data in, and all control signals

except COE

.

11, 12, 13, 14, 92, 93, 94, 96 CWE0 –

CWE7

Input Cache Data Byte Write Enable: Active low write signal for data RAMs.

8 TWE Input Tag Write Enable: Active low write signal for tag RAMs.
— BWE Input Byte Write Enable: To be used in future modules.
— GWE Input Global Write Enable: To be used in future modules.
16 CCS Input Chip Select: Active low chip enable for data RAMs.
30 ADSP Input Address Status Processor: Initiates READ, WRITE, or chip deselect

cycle (Exception–chip deselect does not occur when ADSP

is asserted

and CCS

is high.

9 CADS Input Cache Address Status: Initiates READ, WRITE, or chip deselect cycle.
89 CADV Input Cache Burst Advance: Increments address count in accordance with

interleaved count style.

91 COE Input Cache Output Enable: Active low asynchronous input.

Low–enables output buffers (DQ pins)
High–DQx pins are high impedance.

38, 40, 41, 42, 44, 45, 46, 47, 49, 50, 51,
53, 54, 55, 57, 58, 59, 61, 62, 63, 65, 66,

67, 69, 70, 71, 73, 74, 75, 77, 78, 79,
118, 120, 121, 122, 124, 125, 126, 127,
129, 130, 131, 133, 134, 135, 137, 138,
139, 141, 142, 143, 145, 146, 147, 149,

150, 151, 153, 154, 155, 157, 158, 159

DQ0 –

DQ63

I/O Synchronous Data I/O:

Drives data out of data RAMs during READ cycles.
Stores data to data RAMs during WRITE cycles.

2, 3, 4, 5, 82, 83, 84, 85 TIO0 –

TIO7

I/O Tag RAM I/O:

Drives data out during tag compare cycles.
Stores data to tag RAM during tag WRITE cycles.

33, 34, 112, 113, 114 PD0 –

PD4

— Presence Detect: See Presence Detect Table

7, 15, 25, 39, 52, 60, 68, 76 VCC3 Supply Power Supply: 3.3 V ± 5%.

87, 95, 105, 119, 132, 140, 148, 156 VCC5 Supply Power Supply: 5.0 V ± 5%.

1, 10, 19, 27, 35, 37, 43, 48, 56, 64, 72,
80, 81, 90, 99, 107, 115, 117, 123, 128,

136, 144, 152, 160

V

SS

Supply Ground

6, 17, 18, 26, 31, 32, 86, 88, 97, 98, 100,

111

NC — No Connection: There is no connection to the module.

MCM72JG32•MCM72JG64
6

MOTOROLA FAST SRAM

64K x 18 BurstRAM BLOCK DIAGRAM (See Note)

DQ0 – DQ8

CLR

Q0

Q1

A0

A1

CLK

ADSC

A0 – A15

E

G

ADDRESS

REGISTER

WRITE

REGISTER

ENABLE

REGISTER

DATA–IN

REGISTERS

OUTPUT
BUFFER

64K x 18

MEMORY

ARRAY

ADV

BURST LOGIC

INTERNAL
ADDRESS

A0

′

A1

′

16

9

18

16

2

A2 – A15

A1 – A0

DQ9 – DQ17

9

9 9

9
9

BINARY

COUNTER

DATA–OUT

REGISTERS

UW

LW

ADSP

NOTE: All registers are positive–edge triggered. The ADSC or ADSP signals control the duration of the burst and the start of the

next burst. When ADSP

is sampled low, any ongoing burst is interrupted and a read (independent of CWE and ADSC) is

performed using the new external address. Alternatively , an ADSP

–initiated two cycle WRITE can be performed by negating

both ADSP

and ADSC and asserting L W and/or UW with valid data on the second cycle (see Single Write cycle in WRITE

CYCLES timing diagram). When ADSC

is sampled low (and ADSP is sampled high), any ongoing burst is interrupted and

a read or write (dependent on CWE

) is performed using the new external address. Chip enable (E) is sampled only when

a new base address is loaded. After the first cycle of the burst, ADV

controls subsequent burst cycles. When ADV is sampled

low, the internal address is advanced prior to the operation. When ADV

is sampled high, the internal address is not ad­vanced, thus inserting a wait state into the burst sequence accesses. Upon completion of a burst, the address will wrap
around to its initial state. See BURST SEQUENCE TABLE. Write refers to either or both byte write enables (LW

, UW).

64K x 18 BURST SEQUENCE TABLE

(See Note)

External Address A15 – A2 A1 A0
1st Burst Address A15 – A2 A1 A0
2nd Burst Address A15 – A2 A1 A0
3rd Burst Address A15 – A2 A1 A0

NOTE: The burst wraps around to its initial state upon completion.

NOTE: The above BurstRAM Block Diagram and Burst Sequence Table apply specifically tothe 64K x 18 chip. The 32K x 18 chip is functionally

identical but has no A15.

MCM72JG32•MCM72JG64

7

MOTOROLA FAST SRAM

SYNCHRONOUS TRUTH TABLE (See Notes 1, 2, and 3)

CCS

ADSP CADS CADV CWEx CLK0/1 Address Used Operation

H X L X X L–H N/A Deselected

L L X X X L–H External Address Read Cycle, Begin Burst
L H L X L L–H External Address Write Cycle, Begin Burst

L H L X H L–H External Address Read Cycle, Begin Burst
X H H L L L–H Next Address Write Cycle, Continue Burst
X H H L H L–H Next Address Read Cycle, Continue Burst
X H H H L L–H Current Address Write Cycle, Suspend Burst
X H H H H L–H Current Address Read Cycle, Suspend Burst
H X H L L L–H Next Address Write Cycle, Continue Burst
H X H L H L–H Next Address Read Cycle, Continue Burst
H X H H L L–H Current Address Write Cycle, Suspend Burst
H X H H H L–H Current Address Read Cycle, Suspend Burst

NOTES:

1. X means Don’t Care.

2. All inputs except COE

must meet setup and hold times for the low–to–high transition of clock (CLK0/1).

3. Wait states are inserted by suspending burst.

ASYNCHRONOUS TRUTH TABLE (See Notes 1 and 2)

Operation

COE I/O Status

Read L Data Out
Read H High–Z
Write X High–Z — Data In

Deselected X High–Z

NOTES:

1. X means Don’t Care.

2. For a write operation following a read operation, G

must be high before the input data

required setup time and held high through the input data hold time.

ABSOLUTE MAXIMUM RATINGS (Voltages Referenced to V

SS

= 0 V)

Rating

Symbol Value Unit

Power Supply Voltage VCC5 – 0.5 to + 7.0 V
Voltage Relative to V

SS

Vin, V

out

– 0.5 to VCC + 0.5 V

Output Current (per I/O) I

out

± 30 mA

Temperature Under Bias T

bias

– 10 to + 85 °C

Operating Temperature T

A

0 to +70 °C

Storage Temperature T

stg

– 55 to + 125 °C

NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are

exceeded. Functional operation should be restricted to RECOMMENDED OPER­ATING CONDITIONS. Exposure to higher than recommended voltages for
extended periods of time could affect device reliability.

device contains circuitry to protect the
inputs against damage due to high static volt­ages or electric fields; however, it is advised
that normal precautions be taken to avoid
application of any voltage higher than maxi­mum rated voltages to this high–impedance
circuit.

This BiCMOS memory circuit has been
designed to meet the dc and ac specifications
shown in the tables, after thermal equilibrium
has been established.

This device contains circuitry that will
ensure the output devices are in High–Z at
power up.

This

MCM72JG32•MCM72JG64
8

MOTOROLA FAST SRAM

DC OPERATING CONDITIONS AND CHARACTERISTICS

(VCC = 5.0 V ± 5%, TA = 0 to + 70°C, Unless Otherwise Noted)

RECOMMENDED OPERATING CONDITIONS

(Voltages referenced to VSS = 0 V)

Parameter

Symbol Min Max Unit

Supply Voltage (Operating Voltage Range) V

CC

4.75 5.25 V

Input High Voltage V

IH

2.2 VCC + 0.3** V

Input Low Voltage V

IL

– 0.5* 0.8 V

*VIL (min) = – 0.5 V dc; VIL (min) = – 2.0 V ac (pulse width ≤ 20 ns) for I ≤ 20.0 mA.

**VIH (max) = VCC + 0.3 V dc; VIH (max) = VCC + 2.0 V ac (pulse width ≤ 20 ns) for I ≤ 20.0 mA.

DC CHARACTERISTICS

Parameter Symbol Min Max Unit

Input Leakage Current (All Inputs, Vin = 0 to VCC) I

lkg(I)

— ± 1.0 µA

Output Leakage Current (COE = VIH) I

lkg(O)

— ± 1.0 µA

TTL Output Low Voltage (IOL = + 8.0 mA) V

OL

— 0.4 V

TTL Output High Voltage (IOH = – 4.0 mA) V

OH

2.4 3.3 V

POWER SUPPLY CURRENTS

Parameter Symbol Max Unit

AC Supply Current (COE = VIH, CCS = VIL, I

out

= 0 mA, All Inputs = VIL or VIH,

VIL = 0.0 V and VIH ≥ 3.0 V, Cycle Time ≥ t

KHKH

min)

I

CCA

1300 mA

AC Standby Current (COE = VIH, CCS = VIL, I

out

= 0 mA, All Inputs = VIL or VIH,

VIL = 0.0 V and VIH ≥ 3.0 V, Cycle Time ≥ t

KHKH

min)

I

SB1

340 mA

CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, T

A

= 25°C, Periodically Sampled Rather Than 100% Tested)

Parameter

Symbol Max Unit

Input Capacitance (Address and Control) C

in

28 pF

Input Capacitance (CLK0, CLK1) C

in

12 pF

Input/Output Capacitance (DQ0 – DQ63) C

I/O

10 pF

MCM72JG32•MCM72JG64

9

MOTOROLA FAST SRAM

DATA RAMs AC OPERATING CONDITIONS AND CHARACTERISTICS

(VCC = 5.0 V ± 5% TA = 0 to + 70°C, Unless Otherwise Noted)

Input Timing Measurement Reference Level 1.5 V. . . . . . . . . . . . . . .

Input Pulse Levels 0 to 3.0 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input Rise/Fall Time 3 ns. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output Timing Reference Level 1.5 V. . . . . . . . . . . . . . . . . . . . . . . . . .

Output Load See Figure 1A Unless Otherwise Noted. . . . . . . . . . . .

DATA RAMs READ/WRITE CYCLE TIMING (See Notes 1, 2, 3, and 4)

MCM72JG32–66
MCM72JG64–66

Parameter Symbol Min Max Unit Notes

Cycle Time t

KHKH

15 — ns

Clock Access Time t

KHQV

— 7 ns 5

Output Enable to Output Valid t

GLQV

— 5 ns

Clock High to Output Active t

KHQX1

2 — ns

Clock High to Output Change t

KHQX2

2 — ns

Output Enable to Output Active t

GLQX

1 — ns

Output Disable to Q High–Z t

GHQZ

— 6 ns 6

Clock High to Q High–Z t

KHQZ

2 6 ns

Clock High Pulse Width t

KHKL

5 — ns

Clock Low Pulse Width t

KLKH

5 — ns

Setup Times: Address

Address Status

Data In

Write

Address Advance

Chip Enable

t

AVKH

t

ADSVKH

t

DVKH

t

WVKH

t

ADVVKH

t

EVKH

2.5 — ns 7

Hold Times: Address

Address Status

Data In

Write

Address Advance

Chip Enable

t

KHAX

t

KHADSX

t

KHDX

t

KHWX

t

KHADVX

t

KHEX

0.5 — ns 7

NOTES:

1. In setup and hold times, W (write) refers to either one or both byte write enables LW

and UW.

2. A read cycle is defined by UW

and LW high or ADSP low for the setup and hold times. A write cycle is defined by LW or UW low and

ADSP

high for the setup and hold times.

3. All read and write cycle timings are referenced from CLK or COE

.

4. COE

is a don’t care when UW or LW is sampled low.

5. Maximum access times are guaranteed for all possible i486 amd Pentium external bus cycles.

6. Transition is measured ± 500 mV from steady–state voltage with load of Figure 1B. This parameter is sampled rather than 100% tested.
At any given voltage and temperature, t

KHQZ

max is less than t

KHQZ1

min for a given device and from device to device.

7. This is a synchronous device. All addresses must meet the specified setup and hold times for

ALL

rising edges of CLK whenever ADSP or

CADS

is low, and the chip is selected. All other synchronous inputs must meet the specified setup and hold times for

ALL

rising edges of

CLK when the chip is enabled. Chip enable must be valid at each rising edge of clock for the device (when ADSP

or CADS is low) to remain

enabled.

MCM72JG32•MCM72JG64
10

MOTOROLA FAST SRAM

t

ADSVKH

t

KHADSX

t

KHKH

t

KHKL

t

KLKH

t

AVKH

t

KNAX

t

ADSVKH

t

KHADSX

t

WVKH

t

KMWX

t

ADWKH

t

KHADVX

t

GLQX

t

KHQV

SINGLE READ BURST READ

Q(A2) Q(A2+1) Q(A2+3)

(BURST WRAPS AROUND

TO ITS INITIAL STATE)

DATA RAMs READ CYCLES

A1 A2 A3

ADSP STARTS NEW BURST

Ax

CLK0, CLK1

ADSP

CWEx

DQ

CADV

CADS

Q (A2+2)

t

GHQZ

Q (A2) Q (A3) Q(A3+1) Q(A3+2)

ADDR ignored

(CADV SUSPENDS BURST)

t

EVKH

t

KHEX

ADSP blocked with E high,

t

KHQX1

t

KHQV

Q(A1)

t

KHQX2

COE

CCS

(Address)

BURST READ

MCM72JG32•MCM72JG64

11

MOTOROLA FAST SRAM

W IS IGNORED FOR FIRST CYCLE WHEN ADSP INITIATES BURST

NEW BURST WRITEBURST WRITE

CADV SUSPENDS BURST

t

KHDX

t

DVKH

t

KHADVX

t

ADVVKH

t

KHWX

t

WVKH

CADS STARTS NEW BURST

A3

D(A3 + 2)D(A3 + 1)D(A3)D(A2 + 3)D(A2 + 2)D(A2 + 1)D(A2) D(A2 + 1)

t

KHADSX

t

ADSVKH

t

KHKH

t

KHKL

t

KLKH

D(A1)

t

KHADSX

t

ADSVKH

t

KHAX

t

AVKH

t

KHEX

t

EVKH

SINGLE WRITEBURST READ

t

GHQZ

CLK0, CLK1

ADSP

CADS

Ax

CADV

COE

DATA IN

DATA OUT

A1 A2

CCS

CWEx

DATA RAMs WRITE CYCLES

Q(An – 1) Q(An)

(WITH A SUSPENDED CYCLE)

(Address)

MCM72JG32•MCM72JG64
12

MOTOROLA FAST SRAM

DATA RAMs COMBINATION READ/WRITE CYCLES (CCS low, CADS high)

t

ADVSKH

t

KHADSX

t

KHKH

t

KHKL

t

KLKH

t

AVKH

t

KHAX

t

KHWX

t

WVKH

t

ADVKH

t

KHQX1

t

KHQV

t

GHQZ

t

DVKH

t

KHDX

t

GLQX

t

KHQX2

Q(A1) Q(A3) Q(A3 + 1) Q(A3 + 2)

READ BURST READWRITE

D(A2)

Ax

CLK0, CLK1

ADSP

CWEx

COE

Q

CADV

D

t

KHADVX

A1 A2 A3

t

KHQV

(Address)

MCM72JG32•MCM72JG64

13

MOTOROLA FAST SRAM

TAG RAM AC OPERATING CONDITIONS AND CHARACTERISTICS

(VCC = 5.0 V ± 5%, TA = 0 to + 70°C, Unless Otherwise Noted)

Input Timing Measurement Reference Level 1.5 V. . . . . . . . . . . . . . .

Input Pulse Levels 0 to 3.0 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input Rise/Fall Time 3 ns. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output Timing Measurement Reference Level 1.5 V. . . . . . . . . . . . .

Output Load Figure 1A Unless Otherwise Noted. . . . . . . . . . . . . . . .

TAG RAM READ CYCLE (See Note 1 and 5)

– 15

Parameter Symbol Min Max Unit Notes

Read Cycle Time t

AVAV

15 — ns 2

Address Access Time t

AVQV

— 15 ns

Output Hold from Address Change t

AXQX

4 — ns 3, 4

NOTES:

1. CWE

is high for read cycle.

2. All timings are referenced from the last valid address to the first address transition.

3. Transition is measured ±500 mV from steady–state voltage with load of Figure 1B.

4. This parameter is sampled and not 100% tested.

5. Device is continuously selected (COE

= VIL).

TAG RAM READ CYCLE (See Note 5)

Q (DATA OUT)

Ax (ADDRESS)

DATA VALIDPREVIOUS DATA VALID

t

AVAV

t

AXQX

t

AVQV

MCM72JG32•MCM72JG64
14

MOTOROLA FAST SRAM

TAG RAM WRITE CYCLE (See Notes 1 and 2)

– 15

Parameter Symbol Min Max Unit Notes

Write Cycle Time t

AVAV

15 — ns 3

Address Setup Time t

AVWL

0 — ns

Address Valid to End of Write t

AVWH

12 — ns

Data Valid to End of Write t

DVWH

7 — ns

Data Hold Time t

WHDX

0 — ns

Write Low to Output High–Z t

WLQZ

0 7 ns 5,6,7

Write High to Output Active t

WHQX

4 — ns 5,6,7

Write Recovery Time t

WHAX

0 — ns

NOTES:

1. A write occurs when CWE

is low.

2. If COE

goes low coincident with or after CWE goes low, the output will remain in a high impedance state.

3. All timings are referenced from the last valid address to the first address transition.

4. If COE

≥ VIH, the output will remain in a high impedance state.

5. At any given voltage and temperature, t

WLQZ

(max) is less than t

WHQX

(min), both for a given device and from device to device.

6. Transition is measured ±500 mV from steady–state voltage with load of Figure 2B.

7. This parameter is sampled and not 100% tested.

TAG RAM WRITE CYCLE (See Notes 1 and 2)

DATA VALID

t

DVWH

t

AVWL

t

AVWH

t

AVAV

t

WHAX

t

WLWH

t

WHDX

t

WLQZ

t

WHQX

HIGH Z

HIGH Z

AX (ADDRESS)

TWE

Q (DATA OUT)

D (DATA IN)

AC TEST LOADS

OUTPUT

Z0 = 50

Ω

50

Ω

VL = 1.5 V

Figure 1A Figure 1B

5 pF

+5 V

OUTPUT

255

Ω

480

Ω

TIMING LIMITS

The table of timing values shows either a
minimum or a maximum limit for each param­eter. Input requirements are specified from
the external system point of view. Thus, ad­dress setup time is shown as a minimum
since the system must supply at least that
much time (even though most devices do not
require it). On the other hand, responses from
the memory are specified from the device
point of view. Thus, the access time is shown
as a maximum since the device never pro­vides data later than that time.

MCM72JG32•MCM72JG64

15

MOTOROLA FAST SRAM

ORDERING INFORMATION

(Order by Full Part Number)

MCM 72JG32 XX XX

72JG64

Motorola Memory Prefix
Part Number

Full Part Numbers — MCM72JG32SG66 MCM72JG64SG66

Speed (66 = 66 MHz)

Package (SG = Gold Pad SIMM)

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty , representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “T ypical” parameters can and do vary in different
applications. All operating parameters, including “T ypicals” must be validated for each customer application by customer’s technical experts. Motorola does
not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in
systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of
the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such
unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless
against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part.
Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.

MCM72JG32•MCM72JG64
16

MOTOROLA FAST SRAM

PACKAGE DIMENSIONS

160–LEAD

CARD EDGE MODULE

CASE 1113A–01

É

É

É

É

É

É

É

É

É

É

É

É

É

É

É

É

M

P

(N)

A

SIDE VIEW

E

L

K

R

160X

H160X

R

W

D

160X

156X

Y

L

0.004 (0.1) X

S

T

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A 4.330 4.350 109.98 110.49
B 1.270 1.310 32.26 33.27
C ––– 0.454 ––– 11.53
D 0.033 0.037 0.84 0.94
E 2.265 2.275 57.53 57.79
F 0.075 BSC 1.91 BSC

G 0.050 BSC 1.27 BSC

H ––– 0.030 ––– 0.51
J 0.055 0.069 1.40 1.75
K 0.210 ––– 5.33 –––
L 1.955 1.965 49.66 49.91

M 2.155 2.165 54.74 54.99

N 0.110 REF 2.79 REF
P 0.125 ––– 3.18 –––
R 0.285 0.305 7.24 7.75
V 0.157 ––– 3.99 –––

W 0.040 0.060 1.02 1.52
AB ––– 0.262 ––– 6.66
AC 0.072 0.076 1.83 1.93

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. CARD THICKNESS APPLIES ACROSS TABS AND
INCLUDES PLATING AND/OR METALLIZATION.

4. DIMENSIONS C AND V DEFINE A
DOUBLE–SIDED MODULE.

5. DIMENSION AB DEFINES OPTIONAL
SINGLE–SIDED MODULE.

6. STRAIGHTNESS CALLOUT APPLIES TO TAB
AREA ONLY.

G

É

É

É

É

É

É

É

É

É

2X

BACK VIEW

COMPONENT

VIEW AA

AC

F

–X–

–Y–

B

VIEW

AA

FULL R

COMPONENT

80 43 42 1

AREA

FRONT VIEW

V

NOTE 4

AB

NOTE 5

J NOTE 6

M

0.012 (0.3)

–T–

AREA

160 123 122 81

C

NOTE 4

Literature Distribution Centers:

USA/EUROPE: Motorola Literature Distribution; P .O. Box 20912; Phoenix, Arizona 85036.
JAPAN: Nippon Motorola Ltd.; 4–32–1, Nishi–Gotanda, Shinagawa–ku, Tokyo 141, Japan.
ASIA PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Center, No. 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong.

MCM72JG32/D

*MCM72JG32/D*

◊