Datasheet MCM72PB8ML3.5, MCM72FB8ML8, MCM72FB8ML8R, MCM72FB8ML7.5R, MCM72PB8ML4R Datasheet (Motorola)

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Advance Information

256K x 72 Bit BurstRAM

Order this document

by MCM72FB8ML/D

MCM72FB8ML
MCM72PB8ML

Multichip Module

The 256K x 72 multichip module uses four 4M bit synchronous fast static RAMs
designed to provide a burstable, high performance, secondary cache for the
PowerPC and other high performance microprocessors. It is organized as
256K words of 72 bits each. This device integrates input registers, an output reg­ister (MCM72PB8ML only), a 2–bit address counter, and high speed SRAM onto
a single monolithic circuit for reduced parts count in cache data RAM applica­tions. Synchronous design allows precise cycle control with the use of an exter­nal clock (K). BiCMOS circuitry reduces the overall power consumption of the
integrated functions for greater reliability.

Addresses (SA), data inputs (DQx), and all control signals except output
enable (G
edge–triggered noninverting registers.

addresses can be generated internally (burst sequence operates in linear or
interleaved mode dependent upon the state of LBO
address advance (ADV

clock (K) input. This feature eliminates complex off–chip write pulse generation
and provides increased timing flexibility for incoming signals.

nous write enable (SW
to all bytes. The eight bytes are designated as “a” through “h”. SBa
SBb
are asserted with SW. All bytes are written if either SGW is asserted or if all SBx
and SW are asserted.

For read cycles, pipelined SRAMs output data is temporarily stored by an edge–
triggered output register and then released to the output buffers at the next rising
edge of clock (K). Flow–through SRAMs allow output to simply flow freely from
the memory array.

operate on a separate 2.5 V or 3.3 V power supply. All inputs and outputs are
JEDEC standard JESD8–5 compatible.

• 3.3 V + 10%, – 5% Core Power Supply , 2.5 V or 3.3 V I/O Supply

• ADSP

• Option for Pipeline or Flow–Through (Speeds Guaranteed When Module is

• Selectable Burst Sequencing Order (Linear/Interleaved)

• Single–Cycle Deselect Timing

• Internally Self–Timed Write Cycle

• Byte Write and Global Write Control

• JEDEC BGA Pin Assignment

) and linear burst order (LBO) are clock (K) controlled through positive–

Bursts can be initiated with either ADSP

) input pin.

Write cycles are internally self–timed and are initiated by the rising edge of the

Synchronous byte write (SBx

) are provided to allow writes to either individual bytes or

controls DQb, etc. Individual bytes are written if the selected byte writes SBx

The module can be configured as either a pipelined or flow–through SRAM.

The multichip module operates from a 3.3 V core power supply and all outputs

, ADSC, and ADV Burst Control Pins

Purchased by Appropriate Part Number)

), synchronous global write (SGW), and synchro-

or ADSC input pins. Subsequent burst

) and controlled by the burst

controls DQa,

MULTICHIP MODULE

PIN A1
INDICA TION

(corner without

fiducial)

PIN A1
INDICA TION

(corner with

fiducial)

PBGA

CASE 1103B–01

TOP VIEW

BOTTOM VIEW

(Drawings Not to Scale)

The PowerPC name is a trademark of IBM Corp., used under license therefrom.

This document contains information on a new product. Specifications and information herein are subject to change without notice.

REV 1
7/30/97

 Motorola, Inc. 1997

MOTOROLA FAST SRAM

MCM72FB8ML  MCM72PB8ML

1

256K X 72 FOUR–CHIP MODULE BLOCK DIAGRAM

SA2 – SA17

SA0
SA1

ADSP
ADSC

ADV

K

G
SE1
SE2
SE3

LBO

SW

SGW

FT

18

MCM69P/F819DC*

SA2 – SA17
SA0
SA1
ADSP
ADSC
ADV
K
G
SE1
SE2
SE3
LBO
SW
SGW

FT

SA2 – SA17
SA0

SA1
ADSP
ADSC
ADV
K
G
SE1
SE2
SE3
LBO
SW
SGW
FT

SA2 – SA17
SA0

SA1
ADSP
ADSC
ADV
K
G
SE1
SE2
SE3
LBO
SW

SGW
FT

DQ0 – DQ8

DQ9 – DQ17

MCM69P/F819DC*

DQ0 – DQ8

DQ9 – DQ17

MCM69P/F819DC*

DQ0 – DQ8

DQ9 – DQ17

LW

UW

LW

UW

LW

UW

SBa

SBb

SBc

SBd

SBe

SBf

9

DQa

9

DQb

9

DQc

9

DQd

9

DQe

9

DQf

* Motorola TrueDie devices.

MCM72FB8ML  MCM72PB8ML
2

MCM69P/F819DC*

SA2 – SA17
SA0

SA1
ADSP
ADSC
ADV
K
G

SE1
SE2
SE3

LBO
SW
SGW

FT

DQ0 – DQ8

DQ9 – DQ17

LW

UW

SBg

9

DQg

SBh

9

DQh

MOTOROLA FAST SRAM

PIN ASSIGNMENT

109876511

A

DQe SA

DQe SA SA SE1

B

DQe DQe SA SA

C
D
E

F
G

H
J

K
L
M
N
P

R
T
U
V
W

DQe SE2 V

DQe
DQe DQe V

DQfDQe

DQf DQf V

DQfDQf

DQf

DQf V
DQfDQf

SBf

SBg NC VSSV
DQgDQg

DQg DQg V

DQgDQg

DQg DQg V

DQh K

DQg

DQh V

DQh

DQh

DQh V

DQh NC SA SA0NCSA

DQh
DQh NC

V

DDQVDD

V

V

DDQ

DDQVDD

V

V

DDQ

DDQVSS

V

SBe

V

SBh

V

DDQ

V

V

DDQ
DDQVDD

V

V

DDQ
DDQ

LBO

V

NCDQh

SA

G

SA

SGW

ADV
ADSC
ADSP

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

NC

SW

SA1

V

DDQ

DDQ

V

SS

V

SS

DD

V

SS

V

SS

DD

V

SS

V

SS

SS

SS

V

SS

SS

V

SS

SS

V

SS

DD

V

SS

V

SS

DD

V

V

DD

SS

V

DDQ

DDQ

SA

NC

NC

SA DQd

SA DQd

SA

DDQ
V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

DDQ

SA

SA

SE3

V

DDQ
V

V

DD

DDQ

V

DD

DDQ

V

V

DD

DDQ

V

DD

DDQ

V

V

DDQ

SS

V

SS

VSSNC SBb
V

SS

V

V

DDQ

SS

V

DDQ

DD

V

V

DDQ

DD

V

V

DD

DDQ

V

V

DD

DDQ

FT

V

DDQ

SA

NC DQa

NCNC DQa

141312 15

DQd

DQd
DQd
DQcV
DQc
DQcV
DQc

DQcSBd

DQbSBa
DQb
DQbV
DQb
DQa
DQa
DQa

DQa

DQd
DQd
DQd
DQd
DQc
DQc
DQc
DQc

SBc
DQb
DQb
DQb
DQb
DQb
DQa
DQa
DQa

256K X 72 JEDEC FOUR–CHIP MODULE

TOP VIEW

209 BUMP PBGA

Not to Scale

MOTOROLA FAST SRAM

MCM72FB8ML  MCM72PB8ML

3

PIN DESCRIPTIONS

Pin Locations Symbol

E10 ADSC Input Synchronous Address Status Controller: Active low, interrupts any

F10 ADSP Input Synchronous Address Status Processor: Active low, interrupts any

D10 ADV Input Synchronous Address Advance: Increments address count in

(a) R14, T14, T15, U14, U15, V14, V15,

W14, W15

(b) L14, L15, M14, M15, N14, N15, P14,

P15, R15

(c) E14, F14, F15, G14, G15, H14, H15,

J14, J15

(d) A14, A15, B14, B15, C14, C15, D14,

D15, E15
(e) A5, A6, B5, B6, C5, C6, D5, D6, E5
(f) E6, F5, F6, G5, G6, H5, H6, J5, J6
(g) L5, L6, M5, M6, N5, N6, P5, P6, R5
(h) R6, T5, T6, U5, U6, V5, V6, W5, W6

U13 FT Input Flow–Through Input: This pin must remain in steady state (this

B10 G Input Asynchronous Output Enable.
R10 K Input Clock: This signal registers the address, data in, and all control

U7 LBO Input Linear Burst Order Input: This pin must remain in steady state (this

U10, V10 SA1, SA0 Input Synchronous Address Inputs: These pins must be wired to the two

A7, A8, A9, A11, A12, A13, B7, B8, B9,

B11, B12, B13, V8, V9, V11, V12

L13, K14, K15, J13, J7, K5, K6, L7

(a) (b) (c) (d) (e) (f) (g) (h)

A10 SE1 Input Synchronous Chip Enable: Active low to enable chip.

C7 SE2 Input Synchronous Chip Enable: Active high for depth expansion.
C13 SE3 Input Synchronous Chip Enable: Active low for depth expansion.
C10 SGW Input Synchronous Global Write: This signal writes all bytes regardless of

T10 SW Input Synchronous Write: This signal writes only those bytes that have

D8, D12, E8, E12, F8, F12, G8,

G12, N8, N12, P8, P12, R8, R12, T8, T12

C8, C9, C11, C12, D7, D13, E7,

E13, F7, F13, G7, G13, H7, H13,

M7, M13, N7, N13, P7, P13, R7,
R13, T7, T13, U8, U9, U11, U12

Type Description

ongoing burst and latches a new external address. Used to initiate
READ, WRITE, or chip deselect cycle.

ongoing burst and latches a new external address. Used to initiate
READ, WRITE, or chip deselect cycle (exception — chip deselect
does not occur when ADSP

accordance with counter type selected (linear/interleaved).

DQx I/O Synchronous Data I/O: “x” refers to the byte being read or written

SA2 – SA17 Input Synchronous Address Inputs: These inputs are registered and must

SBx Input Synchronous Byte Write Inputs: “x” refers to the byte being written

V

V

DDQ

DD

Supply Core Power Supply.

Supply I/O Power Supply.

(byte a, b, c, d, e, f, g, h).

signal is not registered or latched). It must be tied high or low.
Low — flow–through mode.
High — pipeline mode.

signals except G

signal not registered or latched). It must be tied high or low.
Low — linear burst counter (68K/PowerPC).
High — interleaved burst counter (486/i960/Pentium).

LSBs of the address bus for proper burst operation. These inputs
are registered and must meet setup and hold times.

meet setup and hold times.

(byte a, b, c, d, e, f, g, h). SGW

Negated high–blocks ADSP
asserted.

the status of the SBx
are being used, tie this pin high.

been selected using the byte write SBx
signals SBx

, LBO, and FT.

are being used, tie this pin low.

is asserted and SE1 is high).

overrides SBx.

or deselects chip when ADSC is

and SW signals. If only byte write signals SBx

pins. If only byte write

MCM72FB8ML  MCM72PB8ML
4

MOTOROLA FAST SRAM

PIN DESCRIPTIONS (continued)

Pin Locations Symbol Type Description

D9, D11, E9, E11, F9, F11, G9 – G11,

H8 – H12, J8 – J12, K8 – K12, L8 – L12,

M8 – M12, N9 – N11, P9, P11, R9, R11,

T9, T11

K7, K13, P10, V7, V13, W7 – W13 NC — No Connection: There is no connection to the chip.

V

SS

Supply Ground.

TRUTH TABLE (See Notes 1 through 5)

Address

Next Cycle

Deselect None 1 X X X 0 X X High–Z X
Deselect None 0 X 1 0 X X X High–Z X
Deselect None 0 0 X 0 X X X High–Z X
Deselect None X X 1 1 0 X X High–Z X
Deselect None X 0 X 1 0 X X High–Z X
Begin Read External 0 1 0 0 X X X High–Z X
Begin Read External 0 1 0 1 0 X X High–Z READ
Continue Read Next X X X 1 1 0 1 High–Z READ
Continue Read Next X X X 1 1 0 0 DQ READ
Continue Read Next 1 X X X 1 0 1 High–Z READ
Continue Read Next 1 X X X 1 0 0 DQ READ
Suspend Read Current X X X 1 1 1 1 High–Z READ
Suspend Read Current X X X 1 1 1 0 DQ READ
Suspend Read Current 1 X X X 1 1 1 High–Z READ
Suspend Read Current 1 X X X 1 1 0 DQ READ
Begin Write External 0 1 0 1 0 X X High–Z WRITE
Continue Write Next X X X 1 1 0 X High–Z WRITE
Continue Write Next 1 X X X 1 0 X High–Z WRITE
Suspend Write Current X X X 1 1 1 X High–Z WRITE
Suspend Write Current 1 X X X 1 1 X High–Z WRITE

NOTES:

1. X = Don’t Care. 1 = logic high. 0 = logic low.

2. Write is defined as either 1) any SBx

3. G

is an asynchronous signal and is not sampled by the clock K. G drives the bus immediately (t

4. On write cycles that follow read cycles, G
also remain negated at the completion of the write cycle to ensure proper write data hold times.

5. This read assumes the RAM was previously deselected.

Used

SE1 SE2 SE3 ADSP ADSC ADV G

and SW low or 2) SGW is low.

must be negated prior to the start of the write cycle to ensure proper write data setup times. G must

GLQX

3

DQx Write 2,

) following G going low.

4

5

5

LINEAR BURST ADDRESS TABLE (LBO = V

1st Address (External) 2nd Address (Internal) 3rd Address (Internal) 4th Address (Internal)

X . . . X00 X . . . X01 X . . . X10 X . . . X11
X . . . X01 X . . . X10 X . . . X11 X . . . X00
X . . . X10 X . . . X1 1 X . . . X00 X . . . X01
X . . . X11 X . . . X00 X . . . X01 X . . . X10

INTERLEAVED BURST ADDRESS TABLE (LBO = V

1st Address (External)

X . . . X00 X . . . X01 X . . . X10 X . . . X11
X . . . X01 X . . . X00 X . . . X11 X . . . X10
X . . . X10 X . . . X1 1 X . . . X00 X . . . X01
X . . . X11 X . . . X10 X . . . X01 X . . . X00

2nd Address (Internal) 3rd Address (Internal) 4th Address (Internal)

MOTOROLA FAST SRAM

SS

)

)

DD

MCM72FB8ML  MCM72PB8ML

5

WRITE TRUTH TABLE

Cycle Type SGW SW SBa SBb SBc SBd SBe SBf SBg SBh

Read H H X X X X X X X X
Read H L L H H H H H H H
Write Byte a H L L H H H H H H H
Write Byte b H L H L H H H H H H
Write Byte c H L H H L H H H H H
Write Byte d H L H H H L H H H H
Write Byte e H L H H H H L H H H
Write Byte f H L H H H H H L H H
Write Byte g H L H H H H H H L H
Write Byte h H L H H H H H H H L
Write All Bytes H L L L L L L L L L
Write All Bytes L X X X X X X X X X

ABSOLUTE MAXIMUM RATINGS (See Note 1)

Rating Symbol Value Unit Notes

Power Supply Voltage V
I/O Supply Voltage V
Input Voltage Relative to VSS for

Any Pin Except V
Input Voltage (Three–State I/O) V

Output Current (per I/O) I
Package Power Dissipation P
Ambient Temperature T
Die Temperature T
Temperature Under Bias T
Storage Temperature T

NOTES:

1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED OPER­ATING CONDITIONS. Exposure to higher than recommended voltages for extended
periods of time could affect device reliability.

2. This is a steady–state DC parameter that is in effect after the power supply has
achieved its nominal operating level. Power sequencing is not necessary.

3. Power dissipation capability is dependent upon package characteristics and use en­vironment. See Package Thermal Characteristics.

DD

DD

DDQ

Vin, V

out

bias

stg

VSS – 0.5 to + 4.6 V
VSS – 0.5 to V

out

IT

D
A

J

VSS – 0.5 to

VDD + 0.5

VSS – 0.5 to

V

DDQ

0 to 70 °C

– 10 to 85 °C

– 55 to 125 °C

V 2

DD

V 2

+ 0.5

± 20 mA

6.4 W 3

110 °C 3

V 2

This device contains circuitry to protect the
inputs against damage due to high static volt­ages or electric fields; however, it is advised
that normal precautions be taken to avoid
application of any voltage higher than maxi­mum rated voltages to this high–impedance
circuit.

PACKAGE THERMAL CHARACTERISTICS

Thermal Resistance Symbol Max Unit Notes

Junction to Ambient (@ 200 lfm) Single–Layer Board

Four–Layer Board
Junction to Board (Bottom) R
Junction to Case (Top) R

NOTES:

1. Junction temperature is a function of on–chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient
temperature, air flow, board population, and board thermal resistance.

2. Per SEMI G38–87.

3. Indicates the average thermal resistance between the die and the printed circuit board.

4. Indicates the average thermal resistance between the die and the case top surface via the cold plate method (MIL SPEC–883
Method 1012.1).

MCM72FB8ML  MCM72PB8ML

R

θJA

θJB
θJC

19
13

10 °C/W 3

0.3 °C/W 4

°C/W 1, 2

MOTOROLA FAST SRAM

6

DC OPERA TING CONDITIONS AND CHARACTERISTICS

(VDD = 3.3 V + 10%, – 5%, TA = 0 to 70°C, Unless Otherwise Noted)

RECOMMENDED OPERATING CONDITIONS: 2.5 V I/O SUPPLY

Parameter

Supply Voltage V
I/O Supply Voltage V
Input Low Voltage V
Input High Voltage V
Input High Voltage I/O Pins V

(Voltages Referenced to VSS = 0 V)

Symbol Min Typ Max Unit

DD

DDQ

IL

IH

IH2

3.135 3.3 3.465 V

2.375 2.5 2.9 V
– 0.3 — 0.7 V

1.7 — VDD + 0.3 V

1.7 — V

RECOMMENDED OPERATING CONDITIONS: 3.3 V I/O SUPPLY (Voltages Referenced to V

Parameter Symbol Min Typ Max Unit

Supply Voltage V
I/O Supply Voltage V
Input Low Voltage V
Input High Voltage V
Input High Voltage I/O Pins V

V

IH

V

SS

DD

DDQ

IL

IH

IH2

3.135 3.3 3.465 V

3.135 3.3 V
– 0.5 — 0.8 V

2 — VDD + 0.5 V
2 — V

SS

= 0 V)

+ 0.3 V

DDQ

DD

+ 0.5 V

DDQ

V

VSS – 1.0 V

20% t

KHKH

Figure 1. Undershoot Voltage

(MIN)

MOTOROLA FAST SRAM

MCM72FB8ML  MCM72PB8ML

7

DC CHARACTERISTICS AND SUPPLY CURRENTS

Parameter Symbol Min Typ Max Unit Notes

Input Leakage Current (0 V ≤ Vin ≤ VDD) I
Output Leakage Current (0 V ≤ Vin ≤ V
AC Supply Current (Device Selected,

All Outputs Open, Freq = Max, VDD = Max, V
Includes Supply Current from Both VDD and V

CMOS Standby Supply Current (Device Deselected, Freq = 0,
VDD = Max, V

TTL Standby Supply Current (Device Deselected, Freq = 0,
VDD = Max, V

Clock Running (Device Deselected, Freq = Max,
VDD = Max, V
CMOS Levels)

Static Clock Running (Device Deselected, Freq = Max,
VDD = Max, V

Output Low Voltage (IOL = 2 mA) V
Output High Voltage (IOH = – 2 mA) V
Output Low Voltage (IOL = 8 mA) V
Output High Voltage (IOH = – 4 mA) V

NOTES:

1. Reference AC Operating Conditions and Characteristics for input and timing.

2. All addresses transition simultaneously low (LSB) then high (MSB).

3. Data states are all zero.

4. Device is deselected as defined by the Truth Table.

5. CMOS levels for I/O’s are VIT ≤ VSS + 0.2 V or ≥ V

6. TTL levels for I/O’s are VIT ≤ VIL or ≥ V

= Max, All Inputs Static at CMOS Levels)

DDQ

= Max, All Inputs Static at TTL Levels)

DDQ

= Max, All Inputs Toggling at

DDQ

= Max, All Inputs Static at TTL Levels)

DDQ

) I

DDQ

= Max)

DDQ

DDQ

= 2.5 V V

DDQ

= 2.5 V V

DDQ

= 3.3 V V

DDQ

= 3.3 V V

DDQ

DDQ

. TTL levels for other inputs are Vin ≤ VIL or ≥ VIH.

IH2

lkg(O)
I

– 0.2 V. CMOS levels for other inputs are Vin ≤ VSS + 0.2 V or ≥ VDD – 0.2 V.

lkg(I)

DDA

I

SB2

I

SB3

I

SB4

I

SB5

OL1

OH1

OL2

OH2

— — ± 1 µA
— — ± 1 µA
— — 1700 mA 1, 2, 3

— — TBD mA 4. 5

— — TBD mA 4, 6

— — TBD mA 4. 5

— — TBD mA 4, 6

— — 0.7 V

1.7 — — V
— — 0.4 V

2.4 — — V

CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, T

Parameter Symbol Min Typ Max Unit

Input Capacitance C
Input/Output Capacitance C

= 0 to 70°C, Periodically Sampled Rather Than 100% Tested)

A

in

I/O

— — 16 pF
— — 5 pF

MCM72FB8ML  MCM72PB8ML
8

MOTOROLA FAST SRAM

AC OPERA TING CONDITIONS AND CHARACTERISTICS

(VDD = 3.3 V + 10%, – 5%, TA = 0 to 70°C, Unless Otherwise Noted)

Input Timing Measurement Reference Level 1.25 V. . . . . . . . . . . . . .

Input Pulse Levels 0 to 2.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input Rise/Fall Time (See Figure 3) 1.0 V/ns (20 to 80%). . . . . . . . .

Output Timing Reference Level 1.25 V. . . . . . . . . . . . . . . . . . . . . . . . .

Output Load See Figure 2 Unless Otherwise Noted. . . . . . . . . . . . . .

READ/WRITE CYCLE TIMING (See Notes 1 and 2)

Pipeline

MCM72PB8ML3.5

166 MHz

Parameter Symbol

Cycle Time t
Clock High Pulse Width t
Clock Low Pulse Width t
Clock Access Time t
Output Enable to Output

Valid
Clock High to Output Active t
Clock High to Output

Change
Output Enable to Output

Active
Output Disable to Q High–Z t
Clock High to Q High–Z t
Setup Times: Address

Hold Times: Address

NOTES:

ADSP

, ADSC, ADV

Data In

Write

Chip Enable

ADSP

, ADSC, ADV

Data In

Write

Chip Enable

1. Write is defined as either any SBx
or ADSC is asserted.

2. All read and write cycle timings are referenced from K or G

3. In order to reduce test correlation issues and to reduce the effects of application specific input edge rate variations on correlation between
data sheet parameters and actual system performance, FSRAM AC parametric specifications are always specified at V
design exercises, it is desirable to evaluate timing using other reference levels. Since the maximum test input edge rate is known and is given
in the AC Test Conditions section of the data sheet as 1 V/ns, one can easily interpolate timing values to other reference levels.

4. This parameter is sampled and not 100% tested.

5. Measured at

± 200 mV from steady state.

KHKH

KHKL
KLKH

KHQV

t

GLQV

KHQX1

t

KHQX2

t

GLQX

GHQZ
KHQZ

t

ADKH

t

ADSKH
t

DVKH

t

WVKH

t

EVKH

t

KHAX

t

KHADSX

t

KHDX

t

KHWX

t

KHEX

Min Max Min Max Min Max Min Max

6 — 7.5 — 8.5 — 10 — ns

2.4 — 3 — 3.4 — 4 — ns 3

2.4 — 3 — 3.4 — 4 — ns 3
— 3.5 — 4 — 7.5 — 8 ns
— 3.5 — 3.8 — 3.5 — 3.5 ns

0 — 0 — 0 — 0 — ns 4, 5

1.5 — 1.5 — 2 — 2 — ns 4

0 — 0 — 0 — 0 — ns 4, 5

— 3.5 — 3.8 — 3.5 — 3.5 ns 4, 5

1.5 6 1.5 7.5 2 3.5 2 3.5 ns 4, 5

1.5 — 1.5 — 2 — 2 — ns

0.5 — 0.5 — 0.5 — 0.5 — ns

and SW low or SGW is low. Chip Enable is defined as SE1 low , SE2 high, and SE3 low whenever ADSP

Pipeline

MCM72PB8ML4

133 MHz

.

Flow–Through

MCM72FB8ML7.5

117 MHz

Flow–Through

MCM72FB8ML8

100 MHz

Unit Notes

/2. In some

DDQ

MOTOROLA FAST SRAM

OUTPUT

Z0 = 50

Ω

1.25 V

Figure 2. AC Test Load

RL = 50

Ω

MCM72FB8ML  MCM72PB8ML

9

OUTPUT LOAD

OUTPUT
BUFFER

UNLOADED RISE AND FALL TIME MEASUREMENT

INPUT

WAVEFORM

OUTPUT

WAVEFORM

NOTES:

1. Input waveform has a slew rate of 1 V/ns.

2. Rise time tr is measured from 0.5 to 2.0 V unloaded.

3. Fall time tf is measured from 2.0 to 0.5 V unloaded.

0.5

2.0

2.0

0.5 0.5

t

r

TEST POINT

Figure 3. Unloaded Rise and Fall Time Characterization

2.0

0.5

2.0

t

f

MCM72FB8ML  MCM72PB8ML
10

MOTOROLA FAST SRAM

VOLTAGE (V)

– 0.5

0

0.8

1.25

1.5

2.3

2.7

2.9

PULL–UP

I (mA) MIN I (mA) MAX

– 38
– 38
– 38
– 26

– 20

0
0
0

– 105
– 105
– 105

– 83
– 70

– 30
– 10

0

(a) Pull–Up for 2.5 V I/O Supply

2.9

2.5

2.3

2.1

1.25

VOLTAGE (V)

0.8

0

0 – 38 – 105

CURRENT (mA)

3.6

VOLTAGE (V)

– 0.5

0

1.4

1.65

2.0

3.135

3.6

VOLTAGE (V)

– 0.5

0

0.4

0.8

1.25

1.6

2.8

3.2

3.4

PULL–UP

I (mA) MIN I (mA) MAX

– 50
– 50
– 50
– 46
– 35

0
0

PULL–DOWN

I (mA) MIN I (mA) MAX

0
0

10
20

31
40
40
40
40

– 150
– 150
– 150
– 130
– 101

– 25

0

0
0

20
40

63
80
80
80
80

3.135

2.8

1.65

VOLTAGE (V)

1.4

0

0

(b) Pull–Up for 3.3 V I/O Supply

V

DD

1.6

1.25

VOLTAGE (V)

0.3

0

040 80

(c) Pull–Down

– 50

CURRENT (mA)

CURRENT (mA)

– 150– 100

MOTOROLA FAST SRAM

Figure 4. T ypical Output Buffer Characteristics

MCM72FB8ML  MCM72PB8ML

11

KHQV

t

GLQX

t

BURST WRITE

CD

SE2, SE3

IGNORED

ADSP, SA

KLKH

t

MCM72PB8ML PIPELINE READ/WRITE CYCLES

KHKL

t

KHKH

t

AB

BURST WRAPS AROUND

KHQV

t

Q(B) D(C) D(C+1) D(C+2) D(C+3) Q(D)

t

Q(B+2) Q(B+3)

Q(B) Q(B+1)

t

Q(A)Q(n)

t

GHQZ

BURST READSINGLE READ

KHQX2

KHQX1

K

SA

MCM72FB8ML  MCM72PB8ML
12

ADSP

ADSC

ADV

SE1

DESELECTED SINGLE READ

KHQZ

E

W

G

t

DQx

W low = SGW low and/or SW and SBx low.

NOTE: E low = SE2 high and SE3 low.

MOTOROLA FAST SRAM

Q(B) D(C) D(C+1) D(C+2) D(C+3) Q(D)

GLQX

t

SE2, SE3

ADSP, SA

GHQZ

t

BURST WRITE

IGNORED

GLQV

t

CD

KLKH

t

MCM72FB8ML FLOW–THROUGH READ/WRITE CYCLES

KHKL

t

KHKH

t

K

AB

SA

ADSP

ADSC

ADV

SE1

Q(B+2) Q(B+3)

BURST WRAPS AROUND

KHQX2

Q(B) Q(B+1)

t

KHQV

t

E

W

G

Q(A)Q(n)

DQx

KHQX1

t

KHQZ

t

BURST READSINGLE READ

DESELECTED SINGLE READ

W low = SGW low and/or SW and SBx low.

NOTE: E low = SE2 high and SE3 low.

MOTOROLA FAST SRAM

MCM72FB8ML  MCM72PB8ML

13

APPLICATION INFORMATION

STOP CLOCK OPERATION

In the stop clock mode of operation, the SRAM will hold all
state and data values even though the clock is not running
(full static operation). The SRAM design allows the clock to
start with ADSP

and ADSC, and stops the clock after the last

write data is latched, or the last read data is driven out.

When starting and stopping the clock, the AC clock timing
and parametrics must be strictly maintained. For example,

MCM72PB8ML PIPELINE STOP CLOCK WITH READ TIMING

K

ADSP

ADDRESS

A1 A2

clock pulse width and edge rates must be guaranteed when
starting and stopping the clocks.

To achieve the lowest power operation for all three stop

clock modes, stop read, stop write, and stop deselect:

1. Force the clock to a low state.

2. Force the control signals to an inactive state (this guar­antees any potential source of noise on the clock input
will not start an unplanned on activity).

3. Force the address inputs to a low state.

ADV

DQx

ADSP

(INITIATES

BURST READ)

NOTE: For lowest possible power consumption during stop clock, the addresses should be driven to a low state (VIL).

Best results are obtained if VIL < 0.2 V.

CLOCK STOP

(CONTINUE

BURST READ)

WAKE UP ADSP

(INITIATES BURST READ)

Q(A1 + 1) Q(A2)Q(A1)

MCM72FB8ML  MCM72PB8ML
14

MOTOROLA FAST SRAM

ADSP

MCM72FB8ML FLOW–THROUGH STOP CLOCK WITH READ TIMING

K

ADDRESS

ADV

DQx

NOTE: For lowest possible power consumption during stop clock, the addresses should be driven to a low state (VIL).

Best results are obtained if VIL < 0.2 V.

A1 A2

Q(A1)

ADSP

(INITIATES

BURST READ)

CLOCK STOP

(CONTINUE

BURST READ)

Q(A2)Q(A1 + 1)

WAKE UP ADSP

(INITIATES BURST READ)

MOTOROLA FAST SRAM

MCM72FB8ML  MCM72PB8ML

15

K

ADSC

STOP CLOCK WITH WRITE TIMING

ADDRESS

WRITE

ADV

DQx

NOTE: While the clock is stopped, DATA IN must be fixed in a high (VIH) or low (VIL) state to reduce the DC current of the

input buffers. For lowest power operation, all data and address lines should be held in a low (VIL) state and control
lines held in an inactive state.

A1 A2

D(A1)DATA IN D(A1 + 1) D(A2)

ADSC

(INITIATES

BURST WRITE)

CLOCK STOP

(CONTINUE

BURST WRITE)

VIH OR VIL FIXED (SEE NOTE)

HIGH–Z

WAKE UP ADSC

(INITIATES BURST WRITE)

MCM72FB8ML  MCM72PB8ML
16

MOTOROLA FAST SRAM

K

ADSC

SE1

STOP CLOCK WITH DESELECT OPERATION TIMING

DATA IN

DQx

NOTES:

1. While the clock is stopped, DA T A IN must be fixed in a high (VIH) or low (VIL) state to reduce the DC current of the
input buffers. For lowest power operation, all data and address lines should be held in a low (VIL) state and control
lines held in an inactive state.

2. For best possible power savings, the data–in should be driven low.

DATA DATA

CONTINUE

BURST READ

CLOCK STOP

(DESELECTED)

VIH OR VIL FIXED (SEE NOTE 1)

HIGH–Z

WAKE UP

(DESELECTED)

MOTOROLA FAST SRAM

MCM72FB8ML  MCM72PB8ML

17

NON–BURST SYNCHRONOUS OPERATION

Although this BurstRAM has been designed for PowerPC–
based and other high end MPU–based systems, these
SRAMs can be used in other high speed L2 cache or
memory applications that do not require the burst address
feature. Most L2 caches designed with a synchronous inter­face can make use of the MCM72FB8ML or MCM72PB8ML.

CONTROL PIN TIE VALUES

Non–Burst ADSP ADSC ADV SE1 LBO

Sync Non–Burst,
Pipelined SRAM

NOTE: Although X is specified in the table as a don’t care, the pin

must be tied either high or low.

(H ≥ VIH, L ≤ VIL)

H L H L X

The burst counter feature of the BurstRAM can be disabled,
and the SRAM can be configured to act upon a continuous
stream of addresses. See Figures 5 and 6.

K

ADDR A B CD EFGH

W

G

DQ

Q(B)Q(A)

Q(D)Q(C) D(E)

D(F) D(G) D(H)

WRITESREADS

Figure 5. Configured as Non–Burst Synchronous Flow–Through SRAM

K

ADDR A B CD EFGH

W

G

DQ

Figure 6. Configured as Non–Burst Synchronous Pipelined SRAM

MCM72FB8ML  MCM72PB8ML
18

Q(B)Q(A)

Q(D)Q(C) D(F)D(E) D(H)D(G)

WRITESREADS

MOTOROLA FAST SRAM

Motorola Memory Prefix

ORDERING INFORMATION

(Order by Full Part Number)

72FB8

MCM 72PB8 XX X X

Blank = Trays, R = Tape and Reel

Part Number

A1

CORNER

E

Speed for MCM72FB8 (7.5 = 7.5 ns, 8 = 8 ns)
Speed for MCM72PB8 (3.5= 3.5 ns, 4 = 4 ns)

Package (ML = Multichip Module on Laminate)

Full Part Numbers — MCM72FB8ML7.5 MCM72FB8ML8

MCM72FB8ML7.5R MCM72FB8ML8R

MCM72PB8ML3.5 MCM72PB8ML4
MCM72PB8ML3.5R MCM72PB8ML4R

P ACKAGE DIMENSIONS

MULTICHIP MODULE

PBGA

CASE 1103B–01

2X

0.2

D

(E3)

C

A

209X

0.2 C

0.35 C

4X

NOTES:

1. DIMENSIONS AND TOLERANCING PER ASME

(E2)

2X

0.2

D1

B

(D3)(D2)

TOP VIEW

56 87 9 10 1 1 12 13 14 15

e

E1

209X

W

V

U

T

R

P
N
M

L
K

J
H
G

F

E
D
C
B
A

b

M

0.30 CA

M

0.15 A

B

A

SIDE VIEW

Y14.5M, 1994.

2. DIMENSIONS IN MILLIMETERS.

3. DIMENSION b IS THE MAXIMUM SOLDER BALL
DIAMETER MEASURED PARALLEL TO DATUM A.

4. DIMENSIONS D2, D3, E2, AND E3 ARE FOR
INFORMATION ONLY.

MILLIMETERS

DIM MIN MAX

A 2.00 2.90
A1 0.50 0.70
A2 0.80 1.20

b 0.60 0.90

D 25.00 BSC
D1 22.86 BSC
D2 7.14 REF
D3 14.05 REF

e 1.27 BSC

E 25.00 BSC
E1 12.70 BSC
E2 7.14 REF

A2

E3 14.05 REF

A1

BOTTOM VIEW

MOTOROLA FAST SRAM

MCM72FB8ML  MCM72PB8ML

19

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty , representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. “T ypical” parameters which may be provided in Motorola
data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”
must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of
others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other
applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury
or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal
Opportunity/Affirmative Action Employer.

How to reach us:
USA/EUROPE/Locations Not Listed: Motorola Literature Distribution; JAPAN: Nippon Motorola Ltd.: SPD, Strategic Planning Office, 4–32–1,

P .O. Box 5405, Denver, Colorado 80217. 303–675–2140 or 1–800–441–2447 Nishi–Gotanda, Shinagawa–ku, Tokyo 141, Japan. 81–3–5487–8488
Mfax: [e-mail] – TOUCHTONE 602–244–6609 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park,

– US & Canada ONLY 1–800–774–1848 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298

INTERNET: http://motorola.com/sps

Mfax is a trademark of Motorola, Inc.

MCM72FB8ML  MCM72PB8ML
20

◊

MOTOROLA FAST SRAM

MCM72FB8ML/D