Datasheet MCM72F8DG12, MCM72F8DG8, MCM72F9DG12, MCM72F9DG8, MCM72F9DG9 Datasheet (Motorola)

MCM72F8•MCM72F9

1

MOTOROLA FAST SRAM

2MB and 4MB Synchronous Fast
Static RAM Module

The MCM72F8 (2MB) is configured as 256K x 72 bits and the MCM72F9 (4MB)
is configured as 512K x 72 bits. Both are packaged in a 168–pin dual–in–line
memory module DIMM. Each module uses Motorola’s 3.3 V 256K x 18 bit
flow–through BurstRAMs.

Address (A), data inputs (DQ, DP), and all control signals except output enable
(G

) are clock (K) controlled through positive–edge–triggered noninverting

registers.

Write cycles are internally self–timed and initiated by the rising edge of the
clock (K) input. This feature provides increased timing flexibility for incoming
signals. Synchronous byte write (W

) allows writes to either individual bytes or to

both bytes.

• Single 3.3 V + 10%, – 5% Power Supply

• Plug and Pin Compatibility with 2MB and 4MB

• Multiple Clock Pins for Reduced Loading

• All Inputs and Outputs are LVTTL Compatible

• Byte Write Capability

• Fast SRAM Access Times: 8/9/12 ns

• Decoupling Capacitors for Each Fast Static RAM

• High Quality Multi–Layer FR4 PWB With Separate Power and Ground

Planes

• Amp Connector, Part Number: 390064–4

• 168–Pin DIMM Module

Order this document

by MCM72F8/D

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

MCM72F8
MCM72F9

168–LEAD DIMM

CASE 1115J–01

TOP VIEW

84

41

40

1

11

REV 3
11/26/97

 Motorola, Inc. 1997

MCM72F8•MCM72F9
2

MOTOROLA FAST SRAM

256K x 18

ADSC
SBa

G

ADSP

SE1

A0 – A17

G0

A0 – A17

ADSP
SGW

K

SBb

ADV

LBO

DQb0 – DQb7

SE2

DQa0 – DQa7

SE3

DQa8

DQb8

SW

E0

V

DD

W1

K0

W0

V

SS

DQ0 – DQ7

DQ8 – DQ15

DP1

DP0

256K x 18

ADSC
SBa

G

SE1

A0 – A17

ADSP
SGW

K

SBb

ADV

LBO

DQb0 – DQb7

SE2

DQa0 – DQa7

SE3

DQa8

DQb8

SW

DQ16 – DQ23

DQ24 – DQ31

DP3

DP2

256K x 18

ADSC
SBa

G

SE1

A0 – A17

ADSP
SGW

K

SBb

ADV

LBO

DQb0 – DQb7

SE2

DQa0 – DQa7

SE3

DQa8

DQb8

SW

DQ32 – DQ39

DQ40 – DQ47

DP5

DP4

256K x 18

ADSC
SBa

G

SE1

A0 – A17

ADSP
SGW

K

SBb

ADV

LBO

DQb0 – DQb7

SE2

DQa0 – DQa7

SE3

DQa8

DQb8

SW

DQ48 – DQ55

DQ56 – DQ63

DP7

DP6

W3

K1

W2

W5

K2

W4

W7

K3

W6

MCM72F8 BLOCK DIAGRAM

MCM72F8•MCM72F9

3

MOTOROLA FAST SRAM

256K x 18

ADSC
SBa

G

ADSP

SE1

A0 – A17

G0

A0 – A17

ADSP
SGW

K

SBb

ADV

LBO

DQb0 – DQb7

SE2

DQa0 – DQa7

SE3

DQa8

DQb8

SW

E0

V

DD

W1

K0

W0

V

SS

DQ0 – DQ7

DQ8 – DQ15

DP1

DP0

W3

K1

W2

256K x 18

ADSC
SBa

G

SE1

A0 – A17

G1

ADSP
SGW

K

SBb

ADV

LBO

DQa0 – DQa7
SE2

DQb0 – DQb7

SE3

DQb8

DQa8

SW

E1

V

DD

V

SS

256K x 18

ADSC
SBa

G

SE1

A0 – A17

ADSP
SGW

K

SBb

ADV

LBO

DQb0 – DQb7

SE2

DQa0 – DQa7

SE3

DQa8

DQb8

SW

256K x 18

ADSC
SBa

G

SE1

A0 – A17

ADSP
SGW

K

SBb

ADV

LBO

DQb0 – DQb7

SE2

DQa0 – DQa7

SE3

DQa8

DQb8

SW

DQ16 – DQ23

DQ24 – DQ31

DP3

DP2

256K x 18

ADSC
SBa

G

SE1

A0 – A17

ADSP
SGW

K

SBb

ADV

LBO

DQb0 – DQb7

SE2

DQa0 – DQa7

SE3

DQa8

DQb8

SW

256K x 18

ADSC
SBa

G

SE1

A0 – A17

ADSP
SGW

K

SBb

ADV

LBO

DQb0 – DQb7

SE2

DQa0 – DQa7

SE3

DQa8

DQb8

SW

DQ32 – DQ39

DQ40 – DQ47

DP5

DP4

W5

K2

W4

256K x 18

ADSC
SBa

G

SE1

A0 – A17

ADSP
SGW

K

SBb

ADV

LBO

DQb0 – DQb7

SE2

DQa0 – DQa7

SE3

DQa8

DQb8

SW

256K x 18

ADSC
SBa

G

SE1

A0 – A17

ADSP
SGW

K

SBb

ADV

LBO

DQb0 – DQb7

SE2

DQa0 – DQa7

SE3

DQa8

DQb8

SW

DQ48 – DQ55

DQ56 – DQ63

DP7

DP6

W7

K3

W6

MCM72F9 BLOCK DIAGRAM

MCM72F8•MCM72F9
4

MOTOROLA FAST SRAM

PIN ASSIGNMENT

168–LEAD DIMM

TOP VIEW

125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168

41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84

DQ18
V

SS

DQ16
DQ15
V

SS

DQ13
DQ11
V

SS

DQ9
DP0
V

DD

DQ6
DQ4
V

SS

DQ2
DQ0
V

SS

NC
A17
V

SS

A15
A13
V

DD

A11
A9
V

SS

A7
A5
V

SS

A3
A1
ADSP
V

SS

K0
V

SS

W6
W4
V

SS

W2
W0
V

DD

G0
E0
V

SS

DQ19

V

SS

DQ17

DP1
V

DD

DQ14
DQ12

V

SS

DQ10

DQ8
V

SS

DQ7
DQ5
V

SS

DQ3
DQ1

V

DD
NC

NC

V

SS

A16
A14

V

SS

A12
A10

V

SS

A8
A6

V

DD

A4
A2
A0

V

SS

K1

V

SS
W7

W5

V

SS

W3
W1

V

SS
G1

E1

V

SS

1
2
3
4
5
6
7
8
9
10

11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40

85
86
87
88
89
90
91
92
93
94

95
96
97
98

99
100
101
102
103
104
105
106
107
108
109
110

111
112
113
114
115
116
117
118
119
120
121
122
123
124

V

SS

DP7
DQ61
V

SS

DQ59
DQ57
V

SS

DP6
DQ54
V

DD

DQ52
DQ50
V

SS

DQ48
DQ47
V

SS

DQ45
DQ43
V

SS

DQ41
DP4
V

DD

DQ38
DQ36
V

SS

DQ34
DQ32
V

SS

K2
V

SS

DQ31
DQ29
V

SS

DQ27
DQ25
V

SS

DP2
DQ22
V

DD

DQ20

V

SS

DQ63
DQ62

V

DD

DQ60
DQ58

V

SS

DQ56
DQ55

V

SS

DQ53
DQ51

V

SS

DQ49

DP5

V

DD

DQ46
DQ44

V

SS

DQ42
DQ40

V

SS

DQ39
DQ37

V

SS

DQ35
DQ33

V

SS

K3

V

SS

DP3

DQ30

V

DD

DQ28
DQ26

V

SS

DQ24
DQ23

V

SS

DQ21

MCM72F8•MCM72F9

5

MOTOROLA FAST SRAM

PIN DESCRIPTIONS

Pin Locations Symbol

Type Description

61, 62, 64, 65, 67, 68, 70, 71,

72, 143, 145, 146, 148, 149,

151, 152, 154, 155

A0 – A17 Input Synchronous Address Inputs: These inputs are registered and must meet

setup and hold times.

156 ADSP Input Synchronous Addresss Status Controller: Initiates read, write, or chip

deselect cycle.

15, 31, 44, 86, 92, 105, 121,

134

DP0 – DP7 Synchronous Parity Data Inputs/Outputs.

2, 3, 5, 6, 8, 9, 11, 12, 14, 17,
18, 20, 21, 23, 24, 26, 27, 32,
34, 35, 37, 38, 40, 41, 43, 46,
47, 49, 50, 52, 53, 55, 56, 87,

89, 90, 93, 95, 96, 98, 99,

101, 102, 104, 107, 108, 110,

111, 115, 116, 118, 119, 122,

124, 125, 127, 128, 130, 131,

133, 136, 137, 139, 140

DQ0 – DQ63 I/O Synchronous Data Inputs/Outputs.

167, 83 E0, E1 Input Synchronous Chip Enable: Active low to enable chip. Negated high —

blocks ADSP

or deselects chip when ADSC is asserted. E1 is only used on

4MB module.

166, 82 G0, G1 Input Asynchronous Output Enable Input:

Low — enables output buffer.
High — DQx pins are high impedance.
G1

is only used on 4MB module.

29, 74, 113, 158 K0 – K3 Input Clock: This signal registers the address, data in, and all control signals

except G

and LBO.

76, 77, 79, 80,

160, 161, 163, 164

W0 – W7 Input Synchronous Byte Write Inputs: x refers to the byte being written (byte a,

b). SGW

overrides SBx.

4, 16, 33, 45, 57, 69, 94,

106, 123, 135, 147, 165

V

DD

Supply Power Supply: 3.3 V + 10%, – 5%. Must be connected on all modules.

1, 7, 10, 13, 19, 22, 25, 28,
30, 36, 39, 42, 48, 51, 54, 60,
63, 66, 73, 75, 78, 81, 84, 85,

88, 91, 97, 100, 103, 109,

112, 114, 117, 120, 126, 129,

132, 138, 141, 144, 150, 153,

157, 159, 162, 168

V

SS

Supply Ground.

58, 59, 142 NC No Connection: There is no connection to the chip.

DATA RAM MCM69F618A SYNCHRONOUS TRUTH TABLE (See Notes 1, 2, 3, and 4)

Next Cycle Address Used E ADSP G DQx WRITE

Deselect None 1 0 X High–Z X

Begin Read External Address 0 0 0 DQ Read

Read Current X 1 1 High–Z Read
Read Current X 1 0 DQ Read

Begin Write External 0 0 X High–Z Write

Write Current X 1 X High–Z Write

NOTES:

1. X = don’t care, 1 = logic high, 0 = logic low.

2. Write is defined as any Wx

low.

3. G

is an asynchronous signal and is not sampled by the clock K. G drives the bus immediately (t

GLQX

) following G going low.

4. On write cycles that follow read cycles, G

must be negated prior to the start of the write cycle to ensure proper write data setup times. G must

also remain negated at the completion of the write cycle to ensure proper write data hold times.

MCM72F8•MCM72F9
6

MOTOROLA FAST SRAM

ABSOLUTE MAXIMUM RATINGS (Voltages Referenced to V

SS

= 0 V)

Rating

Symbol Value Unit

Power Supply Voltage V

DD

– 0.5 to + 4.6 V

Voltage Relative to VSS (See Note 2) Vin, V

out

– 0.5 to VDD + 0.5 V

Input Voltage Three State I/O (See Note 2) V

IT

– 0.5 to VDD + 0.5 V

Output Current (per I/O) I

out

± 20 mA

Power Dissipation MCM72F8

MCM72F9

P

D

4.6

9.2

W

Ambient Temperature T

A

0 to 70 °C

Die Temperature T

J

110 °C

Temperature Under Bias T

bias

– 10 to + 85 °C

Storage Temperature T

stg

– 55 to + 125 °C

NOTES:

1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED OPER­ATING CONDITIONS. Exposure to higher than recommended voltages for extended
periods of time could affect device reliability.

2. This is a steady–state DC parameter that is in effect after the power supply has
achieved its nominal operating level. Power sequencing cannot be controlled and is
not allowed.

DC OPERA TING CONDITIONS AND CHARACTERISTICS

(VDD = 3.3 V + 10%, – 5%, TA = 0 to 70°C, Unless Otherwise Noted)

RECOMMENDED OPERATING CONDITIONS

(Voltages Referenced to VSS = 0 V)

Parameter

Symbol Min Typ Max Unit

Supply Voltage (Operating Voltage Range) V

DD

3.135 3.3 3.6 V

Input High Voltage V

IH

1.7 — VDD + 0.3 V

Input Low Voltage V

IL

– 0.3* — 0.7 V

*VIL ≥ – 2.0 V for t ≤ t

KHKH

/2.

V

IH

20% t

KHKH

(MIN)

V

SS

VSS – 1.0 V

Figure 1. Undershoot Voltage

DC CHARACTERISTICS

Parameter Symbol Min Max Unit

Input Leakage Current (0 V ≤ Vin ≤ VDD) I

lkg(I)

— ± 1.0 µA

Output Leakage Current (0 V ≤ Vin ≤ VDD) I

lkg(O)

— ± 1.0 µA

Output Low Voltage (IOL = + 8.0 mA) V

OL

— 0.4 V

Output High Voltage (IOH = – 4.0 mA) V

OH

2.4 — V

This device contains circuitry to protect the
inputs against damage due to high static volt­ages or electric fields; however, it is advised that
normal precautions be taken to avoid application
of any voltage higher than maximum rated volt­ages to this high–impedance circuit.

This BiCMOS memory circuit has been
designed to meet the dc and ac specifications
shown in the tables, after thermal equilibrium
has been established.

This device contains circuitry that will ensure
the output devices are in High–Z at power up.

MCM72F8•MCM72F9

7

MOTOROLA FAST SRAM

POWER SUPPLY CURRENTS

Parameter Symbol Min Max Unit

AC Supply Current (Device Selected, All Outputs Open, MCM72F8DG8
Cycle Time ≥ t

KHKH

min) MCM72F8DG9

MCM72F8DG12

MCM72F9DG8
MCM72F9DG9

MCM72F9DG12

I

DDA

— 1300

1200
1120
2600
2400
2240

mA

CMOS Standby Supply Current (Deselected, MCM72F8DG
Clock (K) Cycle Time ≥ t

KHKH

MCM72F9DG

I

SB1

— 520

1040

mA

Clock Running Supply Current (Deselected, MCM72F8DG
Clock (K) Cycle Time ≥ t

KHKH

, All Other Inputs MCM72F9DG

Held to Static CMOS Levels Vin ≤ VSS + 0.2 V or ≥ VDD – 0.2 V)

I

SB2

— 120

240

mA

MCM72F8 CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, T

A

= 0 to 70°C, Periodically Sampled Rather Than 100% Tested)

Parameter

Symbol Typ Max Unit

Input Capacitance W, K

Other Inputs

C

in

—
—

15
32

pF

I/O Capacitance C

I/O

— 18 pF

MCM72F9 CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, T

A

= 0 to 70 °C, Periodically Sampled Rather Than 100% Tested)

Parameter Symbol Typ Max Unit

Input Capacitance W, K

E

, G

Other Inputs

C

in

—
—
—

20
32
52

pF

I/O Capacitance C

I/O

— 26 pF

MASS (Periodically Sampled Rather Than 100% Tested)

Parameter Max Unit

MCM72F8 16 g
MCM72F9 20 g

MCM72F8•MCM72F9
8

MOTOROLA FAST SRAM

AC OPERA TING CONDITIONS AND CHARACTERISTICS

(VDD = 3.3 V + 10%, – 5%, TA = 0 to 70°C, Unless Otherwise Noted)

Input Timing Measurement Reference Level 1.25 V. . . . . . . . . . . . . .

Input Pulse Levels 0 to 2.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input Rise/Fall Time 1 V/ns (20 to 80%). . . . . . . . . . . . . . . . . . . . . . .

Output Timing Reference Level 1.25 V. . . . . . . . . . . . . . . . . . . . . . . . .

Output Load See Figure 2 Unless Otherwise Noted. . . . . . . . . . . . . .

DATA RAMs READ/WRITE CYCLE TIMING (See Notes 1, 2, and 3)

MCM72F8–8
MCM72F9–8

MCM72F8–9
MCM72F9–9

MCM72F8–12
MCM72F9–12

Parameter Symbol

Min Max Min Max Min Max

Unit Notes

Cycle Time t

KHKH

10 — 11 — 16.6 — ns

Clock Access Time t

KHQV

— 8 — 9 — 12 ns

Output Enable to Output Valid t

GLQV

— 3.5 — 3.5 — 5 ns

Clock High to Output Active t

KHQX1

0 — 0 — 0 — ns 4, 5

Clock High to Output Change t

KHQX2

2 — 2 — 2 — ns 4

Output Enable to Output Active t

GLQX

0 — 0 — 0 — ns 4, 5

Output Disable to Q High–Z t

GHQZ

— 3.5 — 3.5 — 3.5 ns 4, 5

Clock High to Q High–Z t

KHQZ

2 3.5 2 3.5 2 3.5 ns 4, 5

Clock High Pulse Width t

KHKL

4 — 4.5 — 5 — ns

Clock Low Pulse Width t

KLKH

4 — 4.5 — 5 — ns

Setup Times: Address

ADSP

Data In

Write

Chip Enable

t

AVKH

t

ADKH

t

DVKH

t

WVKH

t

EVKH

2 — 2 — 2 — ns

Hold Times: Address

ADSP

, ADSC, ADV

Data In

Write

Chip Enable

t

KHAX

t

KHADX
t

KHDX

t

KHWX

t

KHEX

0.5 — 0.5 — 0.5 — ns

NOTES:

1. In setup and hold times, write refers to either any SBx

and SW or SGW is low.

2. Chip enable is defined as SE1

low, SE2 high, and SE3 low whenever ADSP or ADSC is asserted.

3. All read and write cycle timings are referenced from K or G

.

4. This parameter is sampled and not 100% tested.

5. Measured at ± 200 mV from steady state.

OUTPUT

Z0 = 50

Ω

RL = 50

Ω

VL = 1.25 V

TIMING LIMITS

The table of timing values shows either a minimum or a
maximum limit for each parameter. Input requirements are
specified from the external system point of view. Thus, ad­dress setup time is shown as a minimum since the system
must supply at least that much time (even though most
devices do not require it). On the other hand, responses
from the memory are specified from the device point of
view. Thus, the access time is shown as a maximum since
the device never provides data later than that time.

Figure 2. AC Test Load

MCM72F8•MCM72F9

9

MOTOROLA FAST SRAM

2.1

INPUT

WAVEFORM

t

r

TEST POINT

OUTPUT
BUFFER

2.1

0.3 0.3

OUTPUT

WAVEFORM

OUTPUT LOAD

t

f

UNLOADED RISE AND FALL TIME MEASUREMENT

NOTES:

1. Input waveform has a slew rate of 1 V/ns.

2. Rise time is measured from 0.3 to 2.1 V unloaded.

3. Fall time is measured from 2.1 to 0.3 V unloaded.

Figure 3. Unloaded Rise and Fall Time Characterization

2.1 2.1

0.3 0.3

(a) Pull–Up

(b) Pull–Down

VOLTAGE (V)

PULL–UP

I (mA) MIN I (mA) MAX

– 0.5

0

0.8

1.25

1.5

2.3

2.7

2.9

3.4

– 38
– 38
– 38
– 26

– 20

0
0
0
0

– 105
– 105
– 105

– 83
– 70

– 30
– 10

0
0

VOLTAGE (V)

PULL–DOWN

I (mA) MIN I (mA) MAX

– 0.5

0

0.4

0.8

1.25

1.6

2.8

3.2

3.4

0
0

10
20

31
40
40
40
40

0
0

20
40

63
80
80
80
80

Figure 4. Output Buffer Characteristics

3.6 0 0

3.6 46 120

TEST POINT

50 Ω LOAD

2.9

2.5

2.3

2.1

1.25

0.8

0

0 – 38 – 105

CURRENT (mA)

VOLTAGE (V)

3.6

TEST POINT

V

DD

1.6

1.25

0.3

0

040 80

CURRENT (mA)

VOLTAGE (V)

50 Ω LOAD

MCM72F8•MCM72F9
10

MOTOROLA FAST SRAM

WRITESREAD

t

KHKL

t

KHKH

A

t

KLKH

DESELECTED

t

KHQZ

t

KHQX1

t

GLQX

B C D E F G

K

Ax

ADSP

E

W

G

Q(n) Q(A) Q(B) Q(C) D(D) D(E) D(F) Q(G)

DQx

t

GHQZ

t

GLQV

READ

READ/WRITE CYCLES

t

KHQV

t

KHQX2

MCM 72F X XX XX

Motorola Memory Prefix
Part Number

Full Part Numbers — MCM72F8DG8 MCM72F8DG9 MCM72F8DG12

MCM72F9DG8 MCM72F9DG9 MCM72F9DG12

Speed (8 = 8 ns, 9 = 9 ns, 12 = 12 ns)
Package (DG = Gold Pad DIMM)

Memory Size (8 = 2MB, 9 = 4MB)

ORDERING INFORMATION

(Order by Full Part Number)

MCM72F8•MCM72F9

11

MOTOROLA FAST SRAM

P ACKAGE DIMENSIONS

168–LEAD DIMM

CASE 1115J–01

ЙЙЙЙЙЙЙЙЙЙЙЙЙЙЙЙЙ

ЙЙЙЙЙЙЙЙЙЙЙЙЙЙЙЙЙ

É

ЙЙЙЙЙЙЙЙЙЙЙЙЙЙЙЙЙ

ЙЙЙЙЙЙЙЙЙЙЙЙЙЙЙЙЙ

C

L

M

0.016 (0.4)

A

D1

D5

FRONT VIEW

VIEW C

VIEW D

D6

VIEW B

(DATUM PLANE C)

VIEW D

b168X

L168X

L1168X

162X

e

M

0.004 (0.1) CA B

84

11 40 4110

1

E2

NOTE 5

A1

NOTE 4

E1

NOTE 6

E

SIDE VIEW

R

K

VIEW B

16885

COMPONENT

AREA

1

A

B

M

0.004 (0.1) CA B

C

NOTES:

1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.

2. CONTROLLING DIMENSION: INCH.

3. CARD THICKNESS APPLIES ACROSS TABS AND
INCLUDES PLATING AND/OR METALLIZATION.

4. DIMENSIONS E AND A1 DEFINE A
DOUBLE–SIDED MODULE.

5. DIMENSION E2 DEFINES OPTIONAL
SINGLE–SIDED MODULE

6. STRAIGHTNESS CALLOUT APPLIES TO TAB
AREA ONLY.

7. D5 DIMENSION DEFINES SLOT END AND EDGE
OF COMPONENT AREA.

R

VIEW C

A3

84

2X

2X

2X P

2X A4

A2

M

0.004 (0.1) CA B

M

0.004 (0.1) CA B

94 95

A5

D4

D4

D3

D2

D2

/2

VIEW C

R

K

VIEW A

M

0.004 (0.1) CA B

A5

M

0.15 (0.006) CA B

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A 1.095 1.105 27.81 28.07
A1 0.390 ––– 9.90 –––
A2 0.118 BSC 3.00 BSC
A3 0.700 BSC 17.78 BSC
A4 0.154 0.161 3.90 4.10
A5 0.118 0.128 3.00 3.25

b 0.037 0.041 0.95 1.05
D1 5.245 5.255 133.22 133.48
D2 5.014 BSC 127.35 BSC
D3 1.700 BSC 43.18 BSC
D4 0.250 BSC 6.35 BSC
D5 0.118 ––– 3.00 –––
D6 0.125 BSC 3.175 BSC

e 0.050 BSC 1.27 BSC

E ––– 0.200 ––– 4.00
E1 0.046 0.054 1.17 1.37
E2 ––– 0.148 ––– 2.70

K 0.075 0.083 1.90 2.10

L 0.100 ––– 2.54 –––
L1 ––– 0.010 ––– 0.25

P 0.114 0.122 2.90 3.10

BACK VIEW

COMPONENT

AREA

MCM72F8•MCM72F9
12

MOTOROLA FAST SRAM

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty , representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. “T ypical” parameters which may be provided in Motorola
data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”
must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of
others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other
applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury
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arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal
Opportunity/Affirmative Action Employer.

Mfax is a trademark of Motorola, Inc.

How to reach us:
USA/EUROPE/Locations Not Listed: Motorola Literature Distribution; JAPAN: Nippon Motorola Ltd.: SPD, Strategic Planning Office, 141,

P.O. B o x 5405, Denver , Colorado, 80217. 1-303-675-2140 or 1-800-441-2447 4-32-1 Nishi-Gotanda, Shagawa-ku, Tokyo, Japan. 03-5487-8488

Mfax: [e-mail] – TOUCHTONE 1-602-244-6609 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park,

Motorola Fax Back System – US & Canada ONLY 1-800-774-1848 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298

– http://sps.motorola.com/mfax/

HOME PAGE: http://motorola.com/sps/ CUSTOMER FOCUS CENTER: 1-800-521-6274

MCM72F8/D

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