Datasheet MCM72F7ADG10, MCM72F7ADG12, MCM72F7ADG9, MCM72F6ADG10, MCM72F6ADG12 Datasheet (Motorola)

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

512KB and 1MB Synchronous
Fast Static RAM Module

Order this document

by MCM72F6A/D

MCM72F6A
MCM72F7A

The MCM72F6A (512KB) is configured as 64K x 72 bits and the MCM72F7A
(1MB) is configured as 128K x 72 bits. Both are packaged in a 168–pin dual–
in–line memory module DIMM. Each module uses Motorola’s 3.3 V 64K x 18 bit
flow–through BurstRAMs.

Address (A), data inputs (DQ, DP), and all control signals except output enable

) are clock (K) controlled through positive–edge–triggered noninverting reg-

(G
isters.

Write cycles are internally self–timed and initiated by the rising edge of the
clock (K) input. This feature provides increased timing flexibility for incoming
signals. Synchronous byte write (W
both bytes.

• Single 3.3 V + 10%, – 5% Power Supply

• Plug and Pin Compatibility with 2MB and 4MB

• Multiple Clock Pins for Reduced Loading

• All Inputs and Outputs are L VTTL Compatible

• Byte Write Capability

• Fast SRAM Access Times: 9/10/12 ns

• Decoupling Capacitors for Each Fast Static RAM

• High Quality Multi–Layer FR4 PWB With Separate Power and Ground

Planes

• Amp Connector, Part Number: 390064–4

• 5 V Tolerant on All Pins (Inputs and I/Os)

• 168–Pin DIMM Module

) allows writes to either individual bytes or to

168–LEAD DIMM

CASE 1115J–01

TOP VIEW

1

11

40
41

1/29/98

 Motorola, Inc. 1998

MOTOROLA FAST SRAM

84

MCM72F6A•MCM72F7A

1

MCM72F6A BLOCK DIAGRAM

E0

G0

A0 – A15

ADSP

W0
W1

K0

V

DD

V

SS

DQ0 – DQ7

DP0

DQ8 – DQ15

DP1

64K x 18

SE1
G
A0 – A15
ADSC
SBa
SBb
K

SE2
ADV
ADSP
SGW
SW
LBO
SE3
DQa0 – DQa7
DQa8
DQb0 – DQb7
DQb8

DQ16 – DQ23

DP2

DQ24 – DQ31

DP3

W2
W3

K1

64K x 18

SE1
G
A0 – A15
ADSC
SBa
SBb
K

SE2
ADV
ADSP
SGW
SW
LBO
SE3
DQa0 – DQa7
DQa8
DQb0 – DQb7
DQb8

DQ32 – DQ39

DP4

DQ40 – DQ47

DP5

W4
W5

K2

64K x 18

SE1
G
A0 – A15
ADSC
SBa
SBb
K

SE2
ADV
ADSP
SGW
SW
LBO
SE3
DQa0 – DQa7
DQa8
DQb0 – DQb7
DQb8

DQ48 – DQ55

DP6

DQ56 – DQ63

DP7

W6
W7

K3

64K x 18

SE1
G
A0 – A15
ADSC
SBa
SBb
K

SE2
ADV
ADSP
SGW
SW
LBO
SE3
DQa0 – DQa7
DQa8
DQb0 – DQb7
DQb8

MCM72F6A•MCM72F7A
2

MOTOROLA FAST SRAM

MCM72F7A BLOCK DIAGRAM

E0

G0

A0 – A15

ADSP

W0
W1

K0

V

DD

V

SS

DQ0 – DQ7

DP0

DQ8 – DQ15

DP1

V

DD

V

SS

E1

G1

64K x 18

SE1
G
A0 – A15
ADSC
SBa
SBb
K

DQa0 – DQa7
DQa8
DQb0 – DQb7
DQb8

SE2
ADV

ADSP
SGW

SW
LBO
SE3

DQ16 – DQ23

DP2

DQ24 – DQ31

DP3

64K x 18

A0 – A15
ADSC

SBa
SBb

K
DQb8
DQb0 – DQb7

DQa8
DQa0 – DQa7
SE2
ADV
ADSP
SGW
SW
LBO
SE3

SE1
G

W2
W3

K1

64K x 18

SE1
G
A0 – A15
ADSC
SBa
SBb
K

DQa0 – DQa7
DQa8
DQb0 – DQb7
DQb8

SE2
ADV

ADSP
SGW

SW
LBO
SE3

DQ32 – DQ39

DP4

DQ40 – DQ47

DP5

64K x 18

A0 – A15
ADSC

SBa
SBb

K
DQb8
DQb0 – DQb7
DQa8
DQa0 – DQa7

SE2
ADV
ADSP
SGW
SW
LBO
SE3

SE1
G

W4
W5

K2

64K x 18

SE1
G
A0 – A15
ADSC
SBa
SBb
K

DQa0 – DQa7
DQa8
DQb0 – DQb7
DQb8

SE2
ADV

ADSP
SGW

SW
LBO
SE3

DQ48 – DQ55

DP6

DQ56 – DQ63

DP7

64K x 18

A0 – A15
ADSC

SBa
SBb

K
DQb8
DQb0 – DQb7
DQa8
DQa0 – DQa7

SE2
ADV
ADSP
SGW
SW
LBO
SE3

SE1
G

W6
W7

K3

64K x 18

SE1
G
A0 – A15
ADSC
SBa
SBb
K

DQa0 – DQa7
DQa8
DQb0 – DQb7
DQb8

SE2
ADV

ADSP
SGW

SW
LBO
SE3

64K x 18

A0 – A15
ADSC

SBa
SBb

K
DQb8
DQb0 – DQb7
DQa8
DQa0 – DQa7

SE2
ADV
ADSP
SGW
SW
LBO
SE3

SE1
G

MOTOROLA FAST SRAM

MCM72F6A•MCM72F7A

3

V

SS

DQ63
DQ62

V

DD

DQ60
DQ58

V

SS

DQ56
DQ55

V

SS

1
2
3
4
5
6
7
8
9
10

85
86
87
88
89
90
91
92
93
94

PIN ASSIGNMENT

168–LEAD DIMM

TOP VIEW

V

SS

DP7
DQ61
V

SS

DQ59
DQ57
V

SS

DP6
DQ54
V

DD

DQ53
DQ51

V

SS

DQ49

DP5

V

DD

DQ46
DQ44

V

SS

DQ42
DQ40

V

SS

DQ39
DQ37

V

SS

DQ35
DQ33

V

SS
K3

V

SS

DP3

DQ30

V

DD

DQ28
DQ26

V

SS

DQ24
DQ23

V

SS

DQ21

11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40

95
96
97
98

99
100
101
102
103
104
105
106
107
108
109
110

111
112
113
114
115
116
117
118
119
120
121
122
123
124

DQ52
DQ50
V

SS

DQ48
DQ47
V

SS

DQ45
DQ43
V

SS

DQ41
DP4
V

DD

DQ38
DQ36
V

SS

DQ34
DQ32
V

SS

K2
V

SS

DQ31
DQ29
V

SS

DQ27
DQ25
V

SS

DP2
DQ22
V

DD

DQ20

DQ19

V

SS

DQ17

DP1

V

DD

DQ14
DQ12

V

SS

DQ10

DQ8

V

SS

DQ7
DQ5

V

SS

DQ3
DQ1
V

DD
NC

NC

V

SS

NC

A14

V

SS

A12
A10

V

SS

A8
A6

V

DD

A4
A2
A0

V

SS

K1

V

SS
W7

W5

V

SS

W3
W1

V

SS
G1

E1

V

SS

41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84

125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168

DQ18
V

SS

DQ16
DQ15
V

SS

DQ13
DQ11
V

SS

DQ9
DP0
V

DD

DQ6
DQ4
V

SS

DQ2
DQ0
V

SS

NC
NC
V

SS

A15
A13
V

DD

A11
A9
V

SS

A7
A5
V

SS

A3
A1
ADSP
V

SS

K0
V

SS

W6
W4
V

SS

W2
W0
V

DD

G0
E0
V

SS

MCM72F6A•MCM72F7A
4

MOTOROLA FAST SRAM

PIN DESCRIPTIONS

Pin Locations Symbol

72, 155, 71, 154, 70, 152,
68, 151, 67, 149, 65, 148,

64, 146, 62, 145

156 ADSP Input Synchronous Addresss Status Controller: Initiates read, write, or chip

134, 44, 121, 31,

105, 15, 92, 86

140, 56, 139, 55, 137, 53,
136, 52, 50, 133, 49, 131,
47, 130, 46, 128, 127, 43,
125, 41, 124, 40, 122, 38,
37, 119, 35, 118, 34, 116,
32, 115, 111, 27, 110, 26,
108, 24, 107, 23, 21, 104,

20, 102, 18, 101, 17, 99,
98, 14, 96, 12, 95, 11, 93,
9, 8, 90, 6, 89, 5, 87, 3, 2

167, 83 E0, E1 Input Synchronous Chip Enable: Active low to enable chip. Negated high —

166, 82 G0, G1 Input Asynchronous Output Enable Input:

158, 74, 113, 29 K0 – K3 Input Clock: This signal registers the address, data in, and all control signals

164, 80, 163, 79, 161,

77, 160, 76

4, 16, 33, 45, 57, 69, 94,

106, 123, 135, 147, 165

1, 7, 10, 13, 19, 22, 25, 28,
30, 36, 39, 42, 48, 51, 54, 60,
63, 66, 73, 75, 78, 81, 84, 85,

88, 91, 97, 100, 103, 109,

112, 114, 117, 120, 126, 129,

132, 138, 141, 144, 150, 153,

157, 159, 162, 168

58, 59, 61, 142, 143 NC No Connection: There is no connection to the chip.

A0 – A15 Input Synchronous Address Inputs: These inputs are registered and must meet

DP0 – DP7 Synchronous Parity Data Inputs/Outputs.

DQ0 – DQ63 I/O Synchronous Data Inputs/Outputs.

W0 – W7 Input Synchronous Byte Write Inputs.

V

DD

V

SS

Type Description

setup and hold times.

deselect cycle.

deselects chip when ADSP

Low — enables output buffer.
High — DQx pins are high impedance.
G1

is only used on 1MB module.

except G0

Supply Power Supply: 3.3 V + 10%, – 5%. Must be connected on all modules.

Supply Ground.

and G1.

is asserted. E1 is only used on 1MB module.

DATA RAM MCM69F618A SYNCHRONOUS TRUTH TABLE (See Notes 1, 2, 3, and 4)

Next Cycle Address Used Ex ADSP Gx DQx WRITE

Deselect None 1 0 X High–Z X

Begin Read External Address 0 0 0 DQ Read

Read Current X 1 1 High–Z Read
Read Current X 1 0 DQ Read

Begin Write External 0 0 X High–Z Write

Write Current X 1 X High–Z Write

NOTES:

1. X = don’t care, 1 = logic high, 0 = logic low.

2. Write is defined as any Wx

3. G

is an asynchronous signal and is not sampled by the clock K. G drives the bus immediately (t

4. On write cycles that follow read cycles, G
also remain negated at the completion of the write cycle to ensure proper write data hold times.

low.

must be negated prior to the start of the write cycle to ensure proper write data setup times. G must

MOTOROLA FAST SRAM

) following G going low.

GLQX

MCM72F6A•MCM72F7A

5

ABSOLUTE MAXIMUM RATINGS (Voltages Referenced to V

Rating Symbol Value Unit

Power Supply Voltage V
Voltage Relative to V
Output Current (per I/O) I
Power Dissipation MCM72F6A

Temperature Under Bias T
Storage Temperature T

NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are

exceeded. Functional operation should be restricted to RECOMMENDED OPER­ATING CONDITIONS. Exposure to higher than recommended voltages for
extended periods of time could affect device reliability.

SS

MCM72F7A

DD

Vin, V

out

P

bias

stg

out

D

– 0.5 to + 4.6 V
– 0.5 to + 6.0 V

– 10 to + 85 °C

– 55 to + 125 °C

= 0 V)

SS

± 20 mA

4.6

9.2

W

DC OPERA TING CONDITIONS AND CHARACTERISTICS

(VDD = 3.3 V + 10%, – 5%, TA = 0 to 70°C, Unless Otherwise Noted)

This device contains circuitry to protect the
inputs against damage due to high static volt­ages or electric fields; however, it is advised
that normal precautions be taken to avoid
application of any voltage higher than maximum
rated voltages to this high–impedance circuit.

This BiCMOS memory circuit has been
designed to meet the dc and ac specifications
shown in the tables, after thermal equilibrium
has been established.

This device contains circuitry that will ensure
the output devices are in High–Z at power up.

RECOMMENDED OPERATING CONDITIONS

Parameter

Supply Voltage (Operating Voltage Range) V
Input High Voltage V
Input Low Voltage V

*VIL ≥ – 2.0 V for t ≤ t

**VIH ≤ 6 V for t

KHKH

KHKH

/2.

/2.

(Voltages Referenced to VSS = 0 V)

Symbol Min Max Unit

DC CHARACTERISTICS

Parameter Symbol Min Max Unit

Input Leakage Current (0 V ≤ Vin ≤ VDD) I
Output Leakage Current (0 V ≤ Vin ≤ VDD) I
Output Low Voltage (IOL = + 8.0 mA) V
Output High Voltage (IOH = – 4.0 mA) V

POWER SUPPLY CURRENTS

Parameter Symbol Min Max Unit

AC Supply Current (Device Selected, All Outputs Open, MCM72F6ADG9
Cycle Time ≥ t

CMOS Standby Supply Current (Deselected, MCM72F6ADG9
Clock (K) Cycle Time ≥ t
CMOS Levels Vin ≤ VSS + 0.2 V or ≥ VDD – 0.2 V) MCM72F6ADG12

Clock Running Supply Current (Deselected, MCM72F6ADG9
Clock (K) Cycle Time ≥ t
Held to Static CMOS Levels Vin ≤ VSS + 0.2 V MCM72F7ADG9
or ≥ VDD – 0.2 V) MCM72F7ADG10/12

min) MCM72F6ADG10

KHKH

, All Inputs Toggling at MCM72F6ADG10

KHKH

, All Other Inputs MCM72F6ADG10/12

KHKH

MCM72F6ADG12

MCM72F7ADG9
MCM72F7ADG10
MCM72F7ADG12

MCM72F7ADG9
MCM72F7ADG10

MCM72F7ADG912

DD

IH
IL

lkg(I)

lkg(O)

OL
OH

I

DDA

I

SB1

I

SB2

3.135 3.6 V

2.0 5.5** V

– 0.5* 0.8 V

— ± 1.0 µA
— ± 1.0 µA
— 0.4 V

2.4 — V

— 900

860

840
1800
1720
1680

— 440

400

380

880

800

760

— 160

140

320

280

mA

mA

mA

MCM72F6A CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, T

Parameter

Input Capacitance W, K

I/O Capacitance C

= 0 to 70°C, Periodically Sampled Rather Than 100% Tested)

A

Other Inputs

MCM72F6A•MCM72F7A
6

Symbol Typ Max Unit

C

in

I/O

—
—

— 19 pF

16
36

pF

MOTOROLA FAST SRAM

MCM72F7A CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, T

Parameter Symbol Typ Max Unit

Input Capacitance W, K

I/O Capacitance C

= 0 to 70 °C, Periodically Sampled Rather Than 100% Tested)

A

E

Other Inputs

, G

C

in

I/O

—
—
—

— 28 pF

22
36
60

MASS (Periodically Sampled Rather Than 100% Tested)

Parameter Max Unit

MCM72F6A 16 g
MCM72F7A 20 g

AC OPERA TING CONDITIONS AND CHARACTERISTICS

(VDD = 3.3 V + 10%, – 5%, TA = 0 to 70°C, Unless Otherwise Noted)

pF

Input Timing Measurement Reference Level 1.5 V. . . . . . . . . . . . . . .

Input Pulse Levels 0 to 3.0 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input Rise/Fall Time 1 V/ns (20 to 80%). . . . . . . . . . . . . . . . . . . . . . .

Output Timing Reference Level 1.5 V. . . . . . . . . . . . . . . . . . . . . . . . . .

Output Load See Figure 1 Unless Otherwise Noted. . . . . . . . . . . . . .

DATA RAMs READ/WRITE CYCLE TIMING (See Notes 1, 2, 3, and 4)

MCM72F6A–9
MCM72F7A–9

Parameter Symbol

Cycle Time t
Clock High Pulse Width t
Clock Low Pulse Width t
Clock Access Time t
Output Enable to Output Valid t
Clock High to Output Active t
Clock High to Output Change t
Output Enable to Output Active t
Output Disable to Q–High–Z t
Clock High to Q–High–Z t
Setup Times Address

Hold Times: Address

NOTES:

1. In setup and hold times, write refers to any Wx

2. Chip Enable is defined as Ex

3. All read and write cycle timings are referenced from K or G

4. G

is a don’t care after write cycle begins. To prevent bus contention, G should be negated prior to start of write cycle.

5. This parameter is sampled and not 100% tested.

6. Measured at ± 200 mV from steady state.

ADSP

ADSP

Data In

Write

Chip Enable

, ADSC, ADV

Data In

Write

Chip Enable

KHKH
KHKL

KLKH
KHQV
GLQV

KHQX1
KHQX2

GLQX
GHQZ
KHQZ

t

AVKH

t

ADKH

t

DVKH

t

WVKH

t

EVKH

t

KHAX

t

KHADX
t

KHDX

t

KHWX

t

KHEX

low, whenever ADSP is asserted.

Min Max Min Max Min Max

12 — 15 — 16.6 — ns

4 — 5 — 6 — ns

4 — 5 — 6 — ns
— 9 — 10 — 12 ns
— 5 — 5 — 6 ns

0 — 0 — 0 — ns 5

3 — 3 — 3 — ns 5

0 — 0 — 0 — ns 5
— 5 — 5 — 6 ns 5, 6

3 5 3 5 3 6 ns 5, 6

2.5 — 2.5 — 2.5 — ns

0.5 — 0.5 — 0.5 — ns

low.

.

MCM72F6A–10
MCM72F7A–10

MCM72F6A–12
MCM72F7A–12

Unit Notes

MOTOROLA FAST SRAM

MCM72F6A•MCM72F7A

7

OUTPUT

K

Z0 = 50

Ω

t

KHKH

50

VL = 1.5 V

Ω

Figure 1. AC Test Load

READ/WRITE CYCLES

t

KHKL

TIMING LIMITS

The table of timing values shows either a minimum or a
maximum limit for each parameter. Input requirements are
specified from the external system point of view. Thus, ad­dress setup time is shown as a minimum since the system
must supply at least that much time (even though most
devices do not require it). On the other hand, responses
from the memory are specified from the device point of
view. Thus, the access time is shown as a maximum since
the device never provides data later than that time.

t

KLKH

Ax

ADSP

E

W

G

DQx

A

Q(n) Q(A) Q(B) Q(C) D(D) D(E) D(F) Q(G)

t

KHQZ

DESELECTED

B C D E F G

t

t

KHQV

t

KHQX1

t

KHQX2

GHQZ

WRITESREAD

t

GLQV

t

GLQX

ORDERING INFORMATION

(Order by Full Part Number)

READ

Motorola Memory Prefix
Part Number Package (DG = Gold Pad DIMM)

Full Part Numbers — MCM72F6ADG9 MCM72F6ADG10 MCM72F6ADG12

MCM72F6A•MCM72F7A
8

MCM 72F X A XX XX

Speed (9 = 9 ns, 10 = 10 ns, 12 = 12 ns)

Module Revision
Memory Size (6A = 512KB, 7A = 1 MB)

MCM72F7ADG9 MCM72F7ADG10 MCM72F7ADG12

MOTOROLA FAST SRAM

ЙЙЙЙЙЙЙЙЙЙЙЙЙЙЙЙЙ

ЙЙЙЙЙЙЙЙЙЙЙЙЙЙЙЙЙ

D5

P ACKAGE DIMENSIONS

168–LEAD DIMM

CASE 1115J–01

D1

0.15 (0.006) CA B

M

C

L

(DATUM PLANE C)

E

A

A

VIEW D

1

VIEW D

1

11 40 4110

94 95

R

K

0.004 (0.1) CA B

M

VIEW A

0.004 (0.1) CA B

L1168X

162X

e

VIEW C

D4

D2

b168X

D3

/2

M

L168X

COMPONENT

AREA

D2

FRONT VIEW

COMPONENT

AREA

BACK VIEW

A5

D6

D4

R

84

VIEW C

VIEW B

VIEW C

R

K

0.004 (0.1) CA B

M

VIEW B

2X A4

A3

2X

2X P

0.004 (0.1) CA B

84

16885

A5

C

0.004 (0.1) CA B

M

A2

2X

M

A1

NOTE 4

E2

NOTE 5

E1

NOTE 6

0.016 (0.4)

M

B

SIDE VIEW

NOTES:

1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.

2. CONTROLLING DIMENSION: INCH.

3. CARD THICKNESS APPLIES ACROSS TABS AND
INCLUDES PLATING AND/OR METALLIZATION.

4. DIMENSIONS E AND A1 DEFINE A
DOUBLE–SIDED MODULE.

5. DIMENSION E2 DEFINES OPTIONAL
SINGLE–SIDED MODULE

6. STRAIGHTNESS CALLOUT APPLIES TO TAB
AREA ONLY.

7. D5 DIMENSION DEFINES SLOT END AND EDGE
OF COMPONENT AREA.

DIM MIN MAX MIN MAX

A 1.095 1.105 27.81 28.07
A1 0.390 ––– 9.90 –––
A2 0.118 BSC 3.00 BSC
A3 0.700 BSC 17.78 BSC
A4 0.154 0.161 3.90 4.10
A5 0.118 0.128 3.00 3.25

b 0.037 0.041 0.95 1.05
D1 5.245 5.255 133.22 133.48
D2 5.014 BSC 127.35 BSC
D3 1.700 BSC 43.18 BSC
D4 0.250 BSC 6.35 BSC
D5 0.118 ––– 3.00 –––
D6 0.125 BSC 3.175 BSC

e 0.050 BSC 1.27 BSC

E ––– 0.200 ––– 4.00
E1 0.046 0.054 1.17 1.37
E2 ––– 0.148 ––– 2.70

K 0.075 0.083 1.90 2.10

L 0.100 ––– 2.54 –––
L1 ––– 0.010 ––– 0.25

P 0.114 0.122 2.90 3.10

MILLIMETERSINCHES

MOTOROLA FAST SRAM

MCM72F6A•MCM72F7A

9

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty , representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. “T ypical” parameters which may be provided in Motorola
data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”
must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of
others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other
applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury
or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal
Opportunity/Affirmative Action Employer.

How to reach us:
USA/EUROPE/ Locations Not Listed: Motorola Literature Distribution; JAPAN: Nippon Motorola Ltd.: SPD, Strategic Planning Of fice, 141,

P.O. B o x 5405, Denver , Colorado, 80217. 1-303-675-2140 or 1-800-441-2447 4-32-1 Nishi-Gotanda, Shagawa-ku, Tokyo, Japan. 03-5487-8488
Mfax: RMF [e-mail] – TOUCHTONE 1-602-244-6609 ASIA/P ACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park,

Motorola Fax Back System – US & Canada ONLY 1-800-774-1848 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298

– http://sps.motorola.com/mfax/

HOME PAGE: http://motorola.com/sps/ CUSTOMER FOCUS CENTER: 1-800-521-6274

Mfax is a trademark of Motorola, Inc.

MCM72F6A•MCM72F7A
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MOTOROLA FAST SRAM

MCM72F6A/D