Datasheet MCM69R737AZP6, MCM69R737AZP6R, MCM69R737AZP7, MCM69R737AZP7R, MCM69R737AZP8 Datasheet (Motorola)

MCM69R737A•MCM69R819A

1

MOTOROLA FAST SRAM

Advance Information

4M Late Write LVTTL

The MCM69R737A/819A is a 4 megabit synchronous late write fast static RAM
designed to provide high performance in secondary cache and ATM switch,
Telecom, and other high speed memory applications. The MCM69R819A
organized as 256K words by 18 bits, and the MCM69R737A organized as 128K
words by 36 bits wide are fabricated in Motorola’s high performance silicon gate
BiCMOS technology.

The differential CK clock inputs control the timing of read/write operations of
the RAM. At the rising edge of the CK clock all addresses, write enables, and
synchronous selects are registered. An internal buffer and special logic enable
the memory to accept write data on the rising edge of the CK clock a cycle after
address and control signals. Read data is driven on the rising edge of the CK
clock also.

The RAM uses LVTTL 3.3 V inputs and outputs.

The synchronous write and byte enables allow writing to individual bytes or the
entire word.

• Byte Write Control

• Single 3.3 V + 10%, – 5% Operation

• L VTTL 3.3 V I/O (V

DDQ

)

• Register to Register Synchronous Operation

• Asynchronous Output Enable

• Boundary Scan (JTAG) IEEE 1149.1 Compatible

• Differential Clock Inputs

• Optional x 18 or x 36 organization

• MCM69R737A/819A–5 = 5 ns

MCM69R737A/819A–6 = 6 ns
MCM69R737A/819A–7 = 7 ns
MCM69R737A/819A–8 = 8 ns

• Sleep Mode Operation (ZZ Pin)

• 1 19 Bump, 50 mil (1.27 mm) Pitch, 14 mm x 22 mm Plastic Ball Grid Array

(PBGA) Package

This document contains information on a new product. Specifications and information herein are subject to change without notice.

Order this document

by MCM69R737A/D

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

MCM69R737A
MCM69R819A

ZP PACKAGE

PBGA

CASE 999–01

REV 1
8/13/97

 Motorola, Inc. 1997

MCM69R737A•MCM69R819A
2

MOTOROLA FAST SRAM

ADDRESS

REGISTERS

SA

CK

SW

SBx

CONTROL

LOGIC

DATA IN

REGISTER

MEMORY

ARRAY

G

SW

REGISTERS

DATA OUT
REGISTER

DQ

SS

SS

REGISTERS

FUNCTIONAL BLOCK DIAGRAM

PIN ASSIGNMENTS

MCM69R737A

6543217

B
C

V

SS

G

A

D
E

F

H
J

V

SS

V

SS

SBb
V

SS

SA

V

SS

V

SS

V

SS

SA SA SA SA

SA SA SA SA

NC SA SA NC

NC
NC

DQb

SA SA

NC

ZZ

SW

DQa

DQa

V

DDQ

V

DDQ

DQb

V

DDQ

DQb

DQb

DQa

DQa

V

DD

V

DD

TDO

SA

TDITMS

NC

TCK

DQd DQd VSSSA

CK

V

SS

DQa

DQaSAV

SS

DQdDQd

V

DDQ

DQd V

SS

NC

DQa

DQaSBa

SBdDQdDQd

DQd DQd VSSCK V

SS

DQc

DQa

V

DD

NC

V

DD

NC

V

DD

V

DDQ

DQc VSSNC DQb

DQb
DQbNCSBc

DQcDQc

V

DDQ

DQc V

SS

G

DQbSSV

SS

DQc

DQc DQc VSSNC DQb

V

DD

NC

NC NC SA NC

NC

K
L
M
N
P

R
T
U

V

DDQ

V

DDQ

NC

V

DDQ

V

DDQ

NC

6543217

B
C

V

SS

G

A

D
E

F

H
J

V

SS

V

SS

V

SS

V

SS

SA

V

SS

V

SS

V

SS

SA SA SA SA

SA SA SA SA

SA SA SA SA

NC
NC
NC

SA SA

NC

ZZ

SW

NC

NC

V

DDQ

V

DDQ

NC

V

DDQ

DQa

DQa

DQa

DQa

V

DD

V

DD

TDO

NC

TDITMS

NC

TCK

NC DQb VSSSA

CK

V

SS

NC

DQaSAV

SS

NCDQb

V

DDQ

DQb V

SS

NC

NC

DQaSBa

V

SS

NCDQb

NC DQb VSSCK V

SS

DQb

NC

V

DD

NC

V

DD

NC

V

DD

V

DDQ

NC VSSNC DQa

DQa

NCNCSBb

DQbNC

V

DDQ

NC V

SS

G

NCSSV

SS

DQbNC

DQb NC VSSNC DQa

V

DD

NC

NC NC SA NC

NC

K
L
M
N
P

R
T
U

V

DDQ

V

DDQ

NC

V

DDQ

V

DDQ

NC

MCM69R819A

DQc

TOP VIEW

MCM69R737A•MCM69R819A

3

MOTOROLA FAST SRAM

MCM69R737A PIN DESCRIPTIONS

PBGA Pin Locations Symbol

Type Description

4K CK Input Address, data in and control input register clock. Active high.
4L CK Input Address, data in and control input register clock. Active low.

(a) 6K, 7K, 6L, 7L, 6M, 6N, 7N, 6P, 7P
(b) 6D, 7D, 6E, 7E, 6F, 6G, 7G, 6H, 7H
(c) 1D, 2D, 1E, 2E, 2F, 1G, 2G, 1H, 2H

(d) 1K, 2K, 1L, 2L, 2M, 1N, 2N, 1P, 2P

DQx I/O Synchronous Data I/O.

4F G Input Output Enable: Asynchronous pin, active low.

2A, 3A, 5A, 6A, 3B, 5B, 2C, 3C,

5C, 6C, 4N, 4P, 2R, 6R, 3T, 4T, 5T

SA Input Synchronous Address Inputs: Registered on the rising clock edge.

5L, 5G, 3G, 3L
(a), (b), (c), (d)

SBx Input Synchronous Byte Write Enable: Enables writes to byte x in

conjunction with the SW

input. Has no effect on read cycles, active

low.

4E SS Input Synchronous Chip Enable: Registered on the rising clock edge, active

low.

4M SW Input Synchronous Write: Registered on the rising clock edge, active low.

Writes all enabled bytes.
4U TCK Input Test Clock (JTAG).
3U TDI Input Test Data In (JTAG).
5U TDO Output Test Data Out (JTAG).
2U TMS Input T est Mode Select (JTAG).
7T ZZ Input Enables sleep mode, active high.

4C, 2J, 4J, 6J, 4R, 5R V

DD

Supply Core Power Supply.

1A, 7A, 1F, 7F, 1J, 7J, 1M, 7M, 1U, 7U V

DDQ

Supply Output Power Supply: provides operating power for output buffers.

3D, 5D, 3E, 5E, 3F, 5F, 3H, 5H,

3K, 5K, 3M, 5M, 3N, 5N, 3P, 5P, 3R

V

SS

Supply Ground.

4A, 1B, 2B, 4B, 6B, 7B, 1C, 7C, 4D, 4G,

4H, 3J, 5J, 1R, 7R, 1T, 2T, 6T, 6U

NC — No Connection: There is no connection to the chip.

Note: 3J and 5J are tied common.

MCM69R737A•MCM69R819A
4

MOTOROLA FAST SRAM

MCM69R819A PIN DESCRIPTIONS

PBGA Pin Locations Symbol

Type Description

4K CK Input Address, data in and control input register clock. Active high.
4L CK Input Address, data in and control input register clock. Active low.

(a) 6D, 7E, 6F, 7G, 6H, 7K, 6L, 6N, 7P

(b) 1D, 2E, 2G, 1H, 2K, 1L, 2M, 1N, 2P

DQx I/O Synchronous Data I/O.

4F G Input Output Enable: Asynchronous pin, active low.

2A, 3A, 5A, 6A, 3B, 5B, 2C, 3C, 5C,

6C, 4N, 4P, 2R, 6R, 2T, 3T, 5T, 6T

SA Input Synchronous Address Inputs: Registered on the rising clock edge.

5L, 3G
(a), (b)

SBx Input Synchronous Byte Write Enable: Enables writes to byte x in

conjunction with the SW

input. Has no effect on read cycles, active

low.
4E SS Input Synchronous Chip Enable: Registered on the rising clock edge, active

low.
4M SW Input Synchronous Write: Registered on the rising clock edge, active low.

Writes all enabled bytes.
4U TCK Input Test Clock (JTAG).
3U TDI Input Test Data In (JTAG).
5U TDO Output Test Data Out (JTAG).
2U TMS Input T est Mode Select (JTAG).
7T ZZ Input Enables sleep mode, active high.

4C, 2J, 4J, 6J, 4R, 5R V

DD

Supply Core Power Supply.

1A, 7A, 1F, 7F, 1J, 7J, 1M, 7M, 1U, 7U V

DDQ

Supply Output Power Supply: provides operating power for output buffers.

3D, 5D, 3E, 5E, 3F, 5F, 5G, 3H, 5H,

3K, 5K, 3L, 3M, 5M, 3N, 5N, 3P, 5P, 3R

V

SS

Supply Ground.

4A, 1B, 2B, 4B, 6B, 7B, 1C, 7C,

2D, 4D, 7D, 1E, 6E, 2F, 1G, 4G, 6G,

2H, 4H, 7H, 3J, 5J, 1K, 6K, 2L, 7L, 6M, 2N,

7N, 1P, 6P, 1R, 7R, 1T, 4T, 6U

NC — No Connection: There is no connection to the chip.

Note: 3J and 5J are tied common.

MCM69R737A•MCM69R819A

5

MOTOROLA FAST SRAM

ABSOLUTE MAXIMUM RATINGS (Voltages Referenced to V

SS

, See Note 1)

Rating

Symbol Value Unit

Core Supply Voltage V

DD

– 0.5 to + 4.6 V

Output Supply Voltage V

DDQ

– 0.5 to VDD + 0.5 V

Voltage On Any Pin V

in

– 0.5 to VDD + 0.5 V

Input Current (per I/O) I

in

± 50 mA

Output Current (per I/O) I

out

± 70 mA

Power Dissipation (See Note 2) P

D

— W

Operating Temperature T

A

0 to + 70 °C

Temperature Under Bias T

bias

–10 to + 85 °C

Storage Temperature T

stg

– 55 to + 125 °C

NOTES:

1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED OPER­ATING CONDITIONS. Exposure to higher than recommended voltages for extended
periods of time could affect device reliability.

2. Power dissipation capability will be dependent upon package characteristics and use
environment. See enclosed thermal impedance data.

PBGA PACKAGE THERMAL CHARACTERISTICS

Rating Symbol Max Unit Notes

Junction to Ambient (Still Air) R

θJA

53 °C/W 1, 2

Junction to Ambient (@200 ft/min) Single Layer Board R

θJA

38 °C/W 1, 2

Junction to Ambient (@200 ft/min) Four Layer Board R

θJA

22 °C/W

Junction to Board (Bottom) R

θJB

14 °C/W 3

Junction to Case (Top) R

θJC

5 °C/W 4

NOTES:

1. Junction temperature is a function of on–chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient
temperature, air flow, power dissipation of other components on the board, and board thermal resistance.

2. Per SEMI G38–87.

3. Indicates the average thermal resistance between the die and the printed circuit board.

4. Indicates the average thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC–883
Method 1012.1).

CLOCK TRUTH TABLE

K ZZ SS SW SBa SBb SBc SBd DQ (n) DQ (n+1) Mode

L – H L L H X X X X X D

out

0–35 Read Cycle All Bytes
L – H L L L L H H H High–Z Din 0–8 Write Cycle 1st Byte
L – H L L L H L H H High–Z Din 9–17 Write Cycle 2nd Byte
L – H L L L H H L H High–Z Din 18–26 Write Cycle 3rd Byte
L – H L L L H H H L High–Z Din 27–35 Write Cycle 4th Byte
L – H L L L L L L L High–Z Din 0–35 Write Cycle All Bytes
L – H L L L H H H H High–Z High–Z Abort Write Cycle
L – H L H H X X X X X High–Z Deselect Cycle
L – H L H L X X X X High–Z High–Z Deselect Cycle

X H X X X X X X High–Z High–Z Sleep Mode

This device contains circuitry to protect the
inputs against damage due to high static volt­ages or electric fields; however, it is advised
that normal precautions be taken to avoid
application of any voltage higher than maxi­mum rated voltages to this high–impedance
circuit.

This BiCMOS memory circuit has been
designed to meet the dc and ac specifications
shown in the tables, after thermal equilibrium
has been established.

This device contains circuitry that will ensure
the output devices are in High–Z at power up.

MCM69R737A•MCM69R819A
6

MOTOROLA FAST SRAM

DC OPERA TING CONDITIONS AND CHARACTERISTICS

(0°C ≤ TA ≤ 70°C, Unless Otherwise Noted)

RECOMMENDED OPERATING CONDITIONS

(See Notes 1 through 4)

Parameter

Symbol Min

Typical–5Typical–6Typical–7Typical

–8

Max Unit Notes

Core Power Supply Voltage V

DD

3.15 — — — — 3.6 V

Output Driver Supply Voltage V

DDQ

3.15 — — — — 3.6 V

Active Power Supply Current (x18)

(x36)

I

DD1

—
—

380
450

360
420

330
390

320
370

480
550

mA 5

Quiescent Active Power Supply Current I

DD2

—
—

180 180 180 180 250 mA 6, 10

Active Standby Power Supply Current) I

SB1

—
—

170 170 170 170 250 mA 7

Quiescent Standby Power Supply Current I

SB2

—
—

150 150 150 150 230 mA 8, 10

Sleep Mode Power Supply Current I

SB3

— 30 30 30 30 50 mA 9, 10

NOTES:

1. All data sheet parameters specified to full range of VDD unless otherwise noted. All voltages are referenced to voltage applied to VSS bumps.

2. Supply voltage applied to VDD connections.

3. Supply voltage applied to V

DDQ

connections.

4. All power supply currents measured with outputs open or deselected.

5. VDD = VDD (max), t

KHKH

= t

KHKH

(min), SS

registered active, 50% read cycles.

6. VDD = VDD (max), t

KHKH

= dc, SS

registered active.

7. VDD = VDD (max), t

KHKH

= t

KHKH

(min), SS

registered inactive.

8. VDD = VDD (max), t

KHKH

= dc, SS

registered inactive. ZZ low.

9. VDD = VDD (max), t

KHKH

= dc, SS

registered inactive, ZZ high.

10. 200 mV ≥ Vin ≥ V

DDQ

– 200 mV .

DC INPUT CHARACTERISTICS

Parameter Symbol Min Max Unit Notes

DC Input Logic High VIH (dc) 2.0 VDD + 0.3 V
DC Input Logic Low VIL (dc) – 0.3 0.8 V 1
Input Leakage Current I

lkg(1)

— ± 5 µA 2

Clock Input Leakage Current I

clkg(1)

— ± 8 µA 2

Clock Input Signal Voltage V

in

– 0.3 VDD + 0.3 V

Clock Input Differential V oltage V

DIF

(dc) 0.2 VDD + 0.6 V 3

Clock Input Common Mode Voltage Range (See Figure 3) VCM (dc) 1 2.1 V 4

NOTES:

1. Inputs may undershoot to – 0.5 V (peak) for up to 20% t

KHKH

(e.g., 2 ns at a clock cycle time of 10 ns).

2. 0 V ≤ Vin ≤ V

DDQ

for all pins.

3. Minimum instantaneous differential input voltage required for differential input clock operation.

4. Maximum rejectable common mode input voltage variation.

DC OUTPUT CHARACTERISTICS

Parameter Symbol Min Max Unit Notes

Output Leakage Current I

lkg(0)

–1.0 1.0 µA

Output Low Voltage V

OL

— 0.4 V 1

Output High Voltage V

OH

2.4 — V 2

NOTES:

1. IOL = 8.0 mA.

2. IOH = – 8.0 mA.

MCM69R737A•MCM69R819A

7

MOTOROLA FAST SRAM

CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, 0°C ≤ T

A

≤ 70°C, Periodically Sampled Rather Than 100% Tested)

Characteristic

Symbol Typ Max Unit

Input Capacitance C

in

4 5 pF

Input/Output Capacitance C

I/O

7 8 pF

CK, CK Capacitance C

CK

4 5 pF

AC OPERA TING CONDITIONS AND CHARACTERISTICS

(0°C ≤ TA ≤ 70°C, Unless Otherwise Noted)

Input Pulse Levels 0 to 3.0 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input Rise/Fall Time 1 V/ns (20% to 80%). . . . . . . . . . . . . . . . . . . . . .

Input Timing Measurement Reference Level 1.5 V. . . . . . . . . . . . . . .

Output Timing Reference Level 1.5 V. . . . . . . . . . . . . . . . . . . . . . . . . .

Clock Input Timing Reference Level Differential Cross–Point. . . . . .

Clock Input Pulse Level 1.8 V to 2.1 V. . . . . . . . . . . . . . . . . . . . . . . . .

R

θJA

TBD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

READ/WRITE CYCLE TIMING (See Note 1)

MCM69R737A–5
MCM69R819A–5

MCM69R737A–6
MCM69R819A–6

MCM69R737A–7
MCM69R819A–7

MCM69R737A–8
MCM69R819A–8

Parameter Symbol Min Max Min Max Min Max Min Max Unit Notes

Cycle Time t

KHKH

5 — 6 — 7 — 8 — ns

Clock High Pulse Width t

KHKL

2 — 2.4 — 2.8 — 3.2 — ns

Clock Low Pulse Width t

KLKH

2 — 2.4 — 2.8 — 3.2 — ns

Clock High to Output
Low–Z

t

KHQX1

1 — 1 — 1 — 1 — ns 2,3

Clock High to Output
Valid

t

KHQV

— 2.5 — 3 — 3.5 — 3.5 ns

Clock High to Output
Hold

t

KHQX

0.5 — 0.5 — 0.5 — 0.5 — ns

Clock High to Output
High–Z

t

KHQZ

— 2.5 — 3 — 3.5 — 3.5 ns 2, 3

Output Enable Low to
Output Low–Z

t

GLQX

0.5 — 0.5 — 0.5 — 0.5 — ns

Output Enable Low to
Output Valid

t

GLQV

— 2.5 — 3 — 3.5 — 3.5 ns

Output Enable to Output
Hold

t

GHQX

0.5 — 0.5 — 0.5 — 0.5 — ns

Output Enable High to
Output High–Z

t

GHQZ

— 2.5 — — 3.5 — 3.5 ns 2, 3

Setup Times: Address

Data In

Chip Select

Write Enable

t

AVKH

t

DVKH

t

SVKH

t

WVKH

0.5 — 0.5 — 0.5 — 0.5 — ns

Hold Times: Address

Data In

Chip Select

Write Enable

t

KHAX

t

KHDX

t

KHSX

t

KHWX

1 — 1 — 1 — 1 — ns

NOTES:

1. In no case may control input signals (e.g., SS

) be operated with pulse widths less than the minimum clock input pulse width specifications

(e.g., t

KHKL

) or at frequencies that exceed the applied K clock frequency.

2. This parameter is sampled and not 100% tested.

3. Measured at ± 200 mV from steady state.

MCM69R737A•MCM69R819A
8

MOTOROLA FAST SRAM

The table of timing values shows either a
minimum or a maximum limit for each param­eter. Input requirements are specified from
the external system point of view. Thus, ad­dress setup time is shown as a minimum
since the system must supply at least that
much time (even though most devices do not
require it). On the other hand, responses from
the memory are specified from the device
point of view. Thus, the access time is shown
as a maximum since the device never pro­vides data later than that time.

TIMING LIMITS

DEVICE

UNDER

TEST

50

Ω

50

Ω

V

DDQ

/2

Figure 1. AC Test Load

V

OH

V

SS

50%

100%

20% t

KHKH

Figure 2. Undershoot Voltage

CROSSING POINT

V

DDQ

V

SS

V

TR

V

DIF

V

CP

VCM*

Figure 3. Differential Inputs/Common Mode Input Voltage

*VCM, the Common Mode Input Voltage, equals VTR – ((VTR – VCP)/2).

MCM69R737A•MCM69R819A

9

MOTOROLA FAST SRAM

t

KHKL

t

KHKH

DQx

CK

Q–1

SA

A0 A1

REGISTER/REGISTER READ–WRITE–READ CYCLES

t

KLKH

Q0 Q1

t

KHQV

D2 Q3

t

KHQZ

A2 A3 A4

t

KHQX1

t

KHDX

t

DVKH

t

WVKH

t

KHWX

t

SVKH

t

KHSX

t

AVKH

t

KHAX

V

IL

SS

SW

SBx

G

t

KHQX

MCM69R737A•MCM69R819A
10

MOTOROLA FAST SRAM

t

KHKL

t

KHKH

DQx

CK

Q–1

SA

A0 A1

t

KLKH

Q0 Q1 D2 Q3

t

GHQZ

A2 A3 A4

t

GLQX

t

AVKH

t

KHAX

V

IL

t

GHQX

t

GLQV

REGISTER/REGISTER READ–WRITE–READ

(G

Controlled)

SS

SW

SBx

G

MCM69R737A•MCM69R819A

11

MOTOROLA FAST SRAM

FUNCTIONAL OPERATION

READ AND WRITE OPERATIONS

All control signals except G

are registered on the rising
edge of the CK clock. These signals must meet the setup
and hold times shown in the AC Characteristics table. On the
rising edge of the following clock, read data is clocked into
the output register and available at the outputs at t

KHQV

. Dur­ing this same cycle a new read address can be applied to the
address pins.

A deselect cycle (dead cycle) must occur prior to a write

cycle. Read cycles may follow write cycles immediately.

G

, SS, and SW control output drive. Chip deselect via a

high on SS

at the rising edge of the CK clock has its effect on
the output drivers after the next rising edge of the CK clock.
SW

low deselects the output drivers immediately (on the
same cycle). Output selecting via a low on SS and high on
SW

at a rising CK clock has its effect on the output drivers
after the next rising edge of the CK clock. Output drive is also
controlled directly by output enable, G

. G is an asynchronous
input. No clock edges are required to enable/disable the out­put using G

.

Output data will be valid the latter of t

GLQV

and t

KHQV

. Out-

puts will begin driving at t

KHQX1

. Outputs will hold previous

data until t

KHQX

or t

GHQX

.

WRITE AND BYTE WRITE FUNCTIONS

Note that in the following discussion the term “byte” refers
to nine bits of the RAM I/O bus. In all cases, the timing pa­rameters described for synchronous write input (SW

) apply

to each of the byte write enable inputs (SBa

, SBb, etc.).

Byte write enable inputs have no effect on read cycles.
This allows the system designer not interested in performing

byte writes to connect the byte enable inputs to active low
(VSS). Reads of all bytes proceed normally and write cycles,
activated via a low on SW

, and the rising edge of the CK
clock, write the entire RAM I/O width. This way the designer
is spared having to drive multiple write input buffer loads.

Byte writes are performed using the byte write enable in-

puts in conjunction with the synchronous write input (SW

). It
is important to note that writing any one byte will inhibit a read
of all bytes at the current address. The RAM cannot simulta­neously read one byte and write another at the same ad­dress. A write cycle initiated with none of the byte write
enable inputs active is neither a read or a write. No write will
occur, but the outputs will be deselected as in a normal write
cycle.

LATE WRITE

The write address is sampled on the first rising edge of

clock and write data is sampled on the following rising edge.

The late write feature is implemented with single stage
write buffering. Write buffering is transparent to the user. A
comparator monitors the address bus and, when necessary,
routes buffer contents to the outputs to assure coherent op­eration. This occurs in all cases whether there is a byte write
or a full word is written.

POWER UP AND INITIALIZATION

The following supply voltage application sequence is rec­ommended: VSS, VDD, then V

DDQ

. Please note, per the Ab-

solute Maximum Ratings table, V

DDQ

is not to exceed VDD +

0.5 V, whatever the instantaneous value of VDD. Once sup­plies have reached specification levels, a minimum dwell of

1.0 ms with C/K clock inputs cycling is required before begin­ning normal operations. At power up the output impedance
will be set at approximately 50 Ω as stated above.

MCM69R737A•MCM69R819A
12

MOTOROLA FAST SRAM

SERIAL BOUNDARY SCAN TEST ACCESS PORT OPERATION

OVERVIEW

The serial boundary scan test access port (TAP) on this
RAM is designed to operate in a manner consistent with
IEEE Standard 1149.1–1990 (commonly referred to as
JTAG), but does not implement all of the functions required
for 1149.1 compliance. Certain functions have been modified
or eliminated because their implementation places extra de­lays in the RAMs critical speed path. Nevertheless, the RAM
supports the standard TAP controller architecture. (The TAP
controller is the state machine that controls the TAPs opera­tion) and can be expected to function in a manner that does
not conflict with the operation of devices with Standard

1 149.1 compliant T APs. The TAP operates using convention­al JEDEC Standard 8–1B Low Voltage (3.3 V) TTL / CMOS
logic level signaling.

DISABLING THE TEST ACCESS PORT

It is possible to use this device without utilizing the TAP. To
disable the T AP Controller without interfering with normal op­eration of the device, TCK must be tied to VSS to preclude
mid level inputs. TDI and TMS are designed so an undriven
input will produce a response identical to the application of a
logic 1, and may be left unconnected. But they may also be
tied to VDD through a 1 k resistor. TDO should be left uncon­nected.

T AP DC OPERATING CHARACTERISTICS

(0°C ≤ TA ≤ 70°C, Unless Otherwise Noted)

Parameter

Symbol Min Max Unit Note

Logic Input Logic High VIH1 2.0 VDD + 0.3 V
Logic Input Logic Low VIL1 – 0.3 0.8 V
Logic Input Leakage Current I

lkg

— ± 5 µA 1
CMOS Output Logic Low VOL1 — 0.2 V 2
CMOS Output Logic High VOH1 VDD – 0.2 — V 3
TTL Output Logic Low VOL2 — 0.4 V 4
TTL Output Logic High VOH2 2.4 — V 5

NOTES:

1. 0 V ≤ Vin ≤ V

DDQ

for all logic input pins.

2. IOL1 ≤ 100 µA @ VOL = 0.2 V. Sampled, not 100% tested.

3. |IOH1| ≤ 100 µA @ V

DDQ

– 0.2 V. Sampled, not 100% tested.

4. IOL2 ≤ 8 mA @ VOL = 0.4 V.

5. |IOH2| ≤ 8 mA @ VOH = 2.4 V.

MCM69R737A•MCM69R819A

13

MOTOROLA FAST SRAM

T AP AC OPERATING CONDITIONS AND CHARACTERISTICS

(0°C ≤ TA ≤ 70°C, Unless Otherwise Noted)

Input Pulse Levels 0 to 3.0 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input Rise/Fall Time 1 V/ns (20% to 80%). . . . . . . . . . . . . . . . . . . . . .

Input Timing Measurement Reference Level 1.5 V. . . . . . . . . . . . . . .

Output Timing Reference Level 1.5 V. . . . . . . . . . . . . . . . . . . . . . . . . .

Output Test Load 50 Ω Parallel Terminated T–line with 20 pF. . . . . .

Receiver Input Capacitance

Test Load Termination Supply Voltage (VT) 1.5 V. . . . . . . . . . . . . . .

TAP CONTROLLER TIMING

Parameter Symbol Min Max Unit Notes

Cycle Time t

THTH

100 — ns

Clock High Time t

THTL

40 — ns

Clock Low Time t

TLTH

40 — ns

TMS Setup t

MVTH

10 — ns

TMS Hold t

THMX

10 — ns

TDI Valid to TCK High t

DVTH

10 — ns

TCK High to TDI Don’t Care t

THDX

10 — ns

Capture Setup t

CS

10 — ns 1

Capture Hold t

CH

10 — ns 1

TCK Low to TDO Unknown t

TLQX

0 — ns

TCK Low to TDO Valid t

TLOV

— 20 ns

NOTES:

1. tCS + tCH defines the minimum pause in RAM I/O pad transitions to assure accurate pad data capture.

AC TEST LOAD

DEVICE

UNDER

TEST

50

Ω

50

Ω

1.5 V

20 pF

t

THDX

t

TLQV

t

TLQX

t

DVTH

t

TLTH

t

THMX

t

MVTH

TAP CONTROLLER TIMING DIAGRAM

t

THTH

TEST CLOCK

(TCK)

TEST MODE SELECT

(TMS)

TEST DATA IN

(TDI)

TEST DATA OUT

(TDO)

t

THTL

MCM69R737A•MCM69R819A
14

MOTOROLA FAST SRAM

TEST ACCESS PORT PINS

TCK – TEST CLOCK (INPUT)

Clocks all TAP events. All inputs are captured on the rising
edge of TCK and all outputs propagate from the falling edge
of TCK.

TMS – TEST MODE SELECT (INPUT)

The TMS input is sampled on the rising edge of TCK. This
is the command input for the TAP controller state machine.
An undriven TMS input will produce the same result as a log­ic one input level.

TDI – TEST DATA IN (INPUT)

The TDI input is sampled on the rising edge of TCK. This is
the input side of the serial registers placed between TDI and
TDO. The register placed between TDI and TDO is deter­mined by the state of the TAP controller state machine and
the instruction that is currently loaded in the TAP instruction
register (refer to Figure 5 TAP Controller State Diagram). An
undriven TDI pin will produce the same result as a logic one
input level.

TDO – TEST DATA OUT (OUTPUT)

Output that is active depending on the state of the TAP
state machine (refer to Figure 5 TAP Controller State Dia­gram). Output changes in response to the falling edge of
TCK. This is the output side of the serial registers placed be­tween TDI and TDO.

TRST – TAP RESET

This device does not have a TRST pin. TRST is optional in
IEEE 1149.1. The test–logic reset state is entered while TMS
is held high for five rising edges of TCK. Power on reset cir­cuitry is included internally. This type of reset does not affect
the operation of the system logic. The reset affects test logic
only .

TEST ACCESS PORT REGISTERS

OVERVIEW

The various TAP registers are selected (one at a time) via
the sequences of ones and zeros input to the TMS pin as the
TCK is strobed. Each of the TAPs registers are serial shift
registers that capture serial input data on the rising edge of
TCK and push serial data out on subsequent falling edge of
TCK. When a register is selected it is “placed” between the
TDI and TDO pins.

INSTRUCTION REGISTER

The instruction register holds the instructions that are
executed by the TAP controller when it is moved into the run
test/idle or the various data register states. The instructions
are three bits long. The register can be loaded when it is
placed between the TDI and TDO pins. The instruction regis­ter is automatically preloaded with the IDCODE instruction at
power–up or whenever the controller is placed in test–logic–
reset state.

BYPASS REGISTER

The bypass register is a single bit register that can be
placed between TDI and TDO. It allows serial test data to be
passed through the RAMs TAP to another device in the scan
chain with as little delay as possible.

BOUNDARY SCAN REGISTER

The boundary scan register is identical in length to the
number of active input and I/O connections on the RAM (not
counting the T AP pins). This also includes a number of place
holder locations (always set to a logic 1) reserved for density
upgrade address pins. There are a total of 70 bits in the case
of the x36 device and 51 bits in the case of the x18 device.
The boundary scan register, under the control of the TAP
controller, is loaded with the contents of the RAMs I/O ring
when the controller is in capture–DR state and then is placed
between the TDI and TDO pins when the controller is moved
to shift–DR state. Several TAP instructions can be used to
activate the boundary scan register.

The Bump/Bit Scan Order tables describe which device
bump connects to each boundary scan register location. The
first column defines the bit’s position in the boundary scan
register. The shift register bit nearest TDO (i.e., first to be
shifted out) is defined as bit 1. The second column is the
name of the input or I/O at the bump and the third column is
the bump number.

IDENTIFICATION (ID) REGISTER

The ID Register is a 32 bit register that is loaded with a de­vice and vendor specific 32 bit code when the controller is
put in capture–DR state with the IDCODE command loaded
in the instruction register. The code is loaded from a 32 bit
on–chip ROM. It describes various attributes of the RAM as
indicated below. The register is then placed between the TDI
and TDO pins when the controller is moved into shift–DR
state. Bit 0 in the register is the LSB and the first to reach
TDO when shifting begins.

ID Register Presence Indicator

Bit # 0

Value 1

Motorola JEDEC ID Code (Compressed Format, per
IEEE Standard 1149.1 – 1990

Bit # 11 10 9 8 7 6 5 4 3 2 1

Value 0 0 0 0 0 0 0 1 1 1 0

Reserved For Future Use

Bit # 17 16 15 14 13 12

Value x x x x x x

Device Width

Configuration Bit # 22 21 20 19 18

128Kx36 V alue 0 0 1 0 0
256Kx18 V alue 0 0 0 1 1

Device Depth

Configuration Bit # 27 26 25 24 23

128Kx36 V alue 0 0 1 0 1
256Kx18 V alue 0 0 1 1 0

Revision Number

Bit # 31 30 29 28

Value x x x x

Figure 4. ID Register Bit Meanings

MCM69R737A•MCM69R819A

15

MOTOROLA FAST SRAM

MCM69R737A Bump/Bit Scan Order

BIT Signal Bump Bit Signal Bump

BIT#Signal

Name

Bump

ID

Bit#Signal

Name

Bump

ID

1 M2 5R 36 SA 3B
2 SA 4P 37 NC 2B
3 SA 4T 38 SA 3A
4 SA 6R 39 SA 3C
5 SA 5T 40 SA 2C
6 ZZ 7T 41 SA 2A
7 DQa 6P 42 DQc 2D
8 DQa 7P 43 DQc 1D

9 DQa 6N 44 DQc 2E
10 DQa 7N 45 DQc 1E
11 DQa 6M 46 DQc 2F
12 DQa 6L 47 DQc 2G
13 DQa 7L 48 DQc 1G
14 DQa 6K 49 DQc 2H
15 DQa 7K 50 DQc 1H
16 SBa 5L 51 SBc 3G
17 CK 4L 52 NC 4D
18 CK 4K 53 SS 4E
19 G 4F 54 NC 4G
20 SBb 5G 55 NC 4H
21 DQb 7H 56 SW 4M
22 DQb 6H 57 SBd 3L
23 DQb 7G 58 DQd 1K
24 DQb 6G 59 DQd 2K
25 DQb 6F 60 DQd 1L
26 DQb 7E 61 DQd 2L
27 DQb 6E 62 DQd 2M
28 DQb 7D 63 DQd 1N
29 DQb 6D 64 DQd 2N
30 SA 6A 65 DQd 1P
31 SA 6C 66 DQd 2P
32 SA 5C 67 SA 3T
33 SA 5A 68 SA 2R
34 NC 6B 69 SA 4N
35 SA 5B 70 M1 3R

MCM69R819A Bump/Bit Scan Order

Bit Signal Bump Bit Signal Bump

Bit#Signal

Name

Bump

ID

Bit#Signal

Name

Bump

ID

1 M2 5R 36 SBb 3G
2 SA 6T 37 NC 4D
3 SA 4P 38 SS 4E
4 SA 6R 39 NC 4G
5 SA 5T 40 NC 4H
6 ZZ 7T 41 SW 4M
7 DQa 7P 42 DQb 2K
8 DQa 6N 43 DQb 1L
9 DQa 6L 44 DQb 2M

10 DQa 7K 45 DQb 1N

11 SBa 5L 46 DQb 2P
12 CK 4L 47 SA 3T
13 CK 4K 48 SA 2R
14 G 4F 49 SA 4N
15 DQa 6H 50 SA 2T
16 DQa 7G 51 M1 3R
17 DQa 6F
18 DQa 7E
19 DQa 6D
20 SA 6A
21 SA 6C
22 SA 5C
23 SA 5A
24 NC 6B
25 SA 5B
26 SA 3B
27 NC 2B
28 SA 3A
29 SA 3C
30 SA 2C
31 SA 2A
32 DQb 1D
33 DQb 2E
34 DQb 2G
35 DQb 1H

NOTES:

1. The NC pads listed in this table are indeed no connects, but are represented in the boundary scan register by a “place holder” bit that is forced
to logic 1. These pads are reserved for use as address inputs on higher density RAMs that follow this pad out and scan order standard.

2. In scan mode, differential inputs CK and CK

are referenced to each other and must be at opposite logic levels for reliable operation.

3. M1 and M2 are not ordinary inputs and may not respond to standard I/O logic levels. M1 and M2 must be driven to within 100 mV of a V

DD

or VSS supply rail to ensure consistent results.

4. ZZ must remain at VIL during boundary scan to ensure consistent results.

MCM69R737A•MCM69R819A
16

MOTOROLA FAST SRAM

T AP CONTROLLER INSTRUCTION SET

OVERVIEW

There are two classes of instructions defined in the Stan­dard 1149.1–1990; the standard (public) instructions, and de­vice specific (private) instructions. Some public instructions,
are mandatory for 1149.1 compliance. Optional public
instructions must be implemented in prescribed ways.

Although the TAP controller in this device follows the
1 149.1 conventions, it is not 1194.1 compliant because some
of the mandatory instructions are not fully implemented. The
TAP on this device may be used to monitor all input and I/O
pads, but cannot be used to load address, data or control sig­nals into the RAM or to preload the I/O buffers. In other
words, the device will not perform Standard 1149.1 EXTEST,
INTEST or the preload portion of the SAMPLE / PRELOAD
command.

When the TAP controller is placed in capture–IR state the
two least significant bits of the instruction register are loaded
with 01. When the controller is moved to the shift–IR state
the instruction register is placed between TDI and TDO. In
this state the desired instruction is serially loaded through the
TDI input (while the previous contents are shifted out at
TDO). For all instructions, the TAP executes newly loaded
instructions only when the controller is moved to update–IR
state. The TAP instruction sets for this device are listed in the
following tables.

ST ANDARD (PUBLIC) INSTRUCTIONS

BYPASS

The BYPASS instruction is loaded in the instruction regis­ter when the bypass register is placed between TDI and
TDO. This occurs when the TAP controller is moved to the
shift–DR state. This allows the board level scan path to be
shortened to facilitate testing of other devices in the scan
path.

SAMPLE/PRELOAD

Sample/preload is a Standard 1149.1 mandatory public
instruction. When the sample / preload instruction is loaded
in the Instruction register, moving the TAP controller into the
capture–DR state loads the data in the RAMs input and I/O
buffers into the boundary scan register. Because the RAM
clock(s) are independent from the TAP clock (TCK) it is pos­sible for the TAP to attempt to capture the I/O ring contents
while the input buffers are in transition (i.e. in a metastable
state). Although allowing the TAP to sample metastable in­puts will not harm the device, repeatable results cannot be

expected. RAM input signals must be stabilized for long
enough to meet the T APs input data capture set–up plus hold
time (tCS plus tCH). The RAMs clock inputs need not be
paused for any other TAP operation except capturing the I/O
ring contents into the boundary scan register.

Moving the controller to shift–DR state then places the
boundary scan register between the TDI and TDO pins. Be­cause the PRELOAD portion of the command is not imple­mented in this device, moving the controller to the
update–DR state with the SAMPLE / PRELOAD instruction
loaded in the instruction register has the same effect as the
pause–DR command. This functionality is not Standard
1 149.1 compliant.

EXTEST

EXTEST is an IEEE 1149.1 mandatory public instruction. It
is to be executed whenever the instruction register, whatever
length it may be in the device, is loaded with all logic 0s.
EXTEST is not implemented in this device. Therefore this
device is not 1149.1 compliant. Nevertheless, this RAMs TAP
does respond to an all zeros instruction, as follows. With the
EXTEST (000) instruction loaded in the instruction register
the RAM responds just as it does in response to the
SAMPLE / PRELOAD instruction described above, except
the RAM outputs are forced to high–Z any time the
instruction is loaded.

IDCODE

The IDCODE instruction causes the ID ROM to be loaded
into the ID register when the controller is in capture–DR
mode and places the ID register between the TDI and TDO
pins in shift–DR mode. The IDCODE instruction is the default
instruction loaded in at power up and any time the controller
is placed in the test–logic–reset state.

THE DEVICE SPECIFIC (PUBLIC) INSTRUCTION

SAMPLE–Z

If the SAMPLE–Z instruction is loaded in the instruction
register, all RAM outputs are forced to an inactive drive state
(high–Z) and the boundary scan register is connected be­tween TDI and TDO when the TAP controller . is moved to the
shift–DR state.

THE DEVICE SPECIFIC (PRIV ATE) INSTRUCTION

NOOP

Do not use these instructions; they are reserved for future
use.

MCM69R737A•MCM69R819A

17

MOTOROLA FAST SRAM

STANDARD (PUBLIC) INSTRUCTION CODES

Instruction Code* Description

EXTEST 000 Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces all

RAM outputs to High–Z state. *NOT 1149.1 COMPLIANT*

IDCODE 001** Preloads ID register and places it between TDI and TDO.

Does not affect RAM operation.

SAMPLE / PRELOAD 100 Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Does not

affect RAM operation.
Does not implement 1149.1 Preload function. * NOT 1149.1 COMPLIANT *

BYPASS 111 Places bypass register between TDI and TDO.

Does not affect RAM operation.

SAMPLE–Z 010 Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces all

RAM output drivers to High–Z.

*Instruction codes expressed in binary, MSB on left, LSB on right.

**Default instruction automatically loaded at power–up and in test–logic–reset state.

STANDARD (PRIVATE) INSTRUCTION CODES

Instruction Code* Description

NO OP 011 Do not use these instructions; they are reserved for future use.
NO OP 101 Do not use these instructions; they are reserved for future use.
NO OP 110 Do not use these instructions; they are reserved for future use.

*Instruction codes expressed in binary, MSB on left, LSB on right.

CAPTURE–DR

EXIT1–DR

EXIT2–DR

UPDATE–DR

CAPTURE–IR

EXIT1–IR

EXIT2–IR

UPDATE–IR

SHIFT–IR

PAUSE–IR

SHIFT–DR

PAUSE–DR

TEST–LOGIC

RESET

RUN–TEST/

IDLE

SELECT

DR–SCAN

SELECT

IR–SCAN

1

0

1

1

1

1

1

1

1

11

1

1

1

1

1

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

NOTE: The value adjacent to each state transition represents the signal present at TMS at the rising edge of TCK.

0

Figure 5. TAP Controller State Diagram

MCM69R737A•MCM69R819A
18

MOTOROLA FAST SRAM

ORDERING INFORMATION

(Order by Full Part Number)

MCM 69R819A XX X X

Motorola Memory Prefix
Part Number

Full Part Numbers — MCM69R737AZP5 MCM69R737AZP6 MCM69R737AZP7 MCM69R737AZP8

MCM69R819AZP5 MCM69R819AZP6 MCM69R819AZP7 MCM69R819AZP8
MCM69R737AZP5R MCM69R737AZP6R MCM69R737AZP7R MCM69R737AZP8R
MCM69R819AZP5R MCM69R819AZP6R MCM69R819AZP7R MCM69R819AZP8R

R = Tape and Reel, Blank = Tray

Package (ZP = PBGA)

Speed (5 = 5 ns, 6 = 6 ns, 7 = 7 ns, 8 = 8 ns)

69R737A

MCM69R737A•MCM69R819A

19

MOTOROLA FAST SRAM

ZP PACKAGE

7 X 17 BUMP PBGA

CASE 999–01

P ACKAGE DIMENSIONS

–L–

A
B
C
D
E
F
G
H

J
K
L
M
N
P
R
T
U

A

P

N

4X

16X

119X

TOP VIEW

K

BOTTOM VIEW

SIDE VIEW

B

S

0.20 (0.008)

R

6X G

G

7654321

D

L0.30 (0.012)STW

SS

0.10 (0.004)ST

0.15 (0.006) T

0.25 (0.010) T

0.35 (0.014) T

E

C

DIMAMIN MAX MIN MAX

INCHES

14.00 BSC 0.551 BSC

MILLIMETERS

B 22.00 BSC 0.866 BSC
C ––– 2.40 ––– 0.094
D 0.60 0.90 0.024 0.035
E 0.50 0.70 0.020 0.028
F 1.30 1.70 0.051 0.067
G 1.27 BSC 0.050 BSC
K 0.80 1.00 0.031 0.039
N 11.90 12.10 0.469 0.476
P 19.40 19.60 0.764 0.772
R 7.62 BSC 0.300 BSC
S 20.32 BSC 0.800 BSC

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

PIN 1A
IDENTIFIER

F

–W–

–T–

MCM69R737A•MCM69R819A
20

MOTOROLA FAST SRAM

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty , representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. “T ypical” parameters which may be provided in Motorola
data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”
must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of
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arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal
Opportunity/Affirmative Action Employer.

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MCM69R737A/D

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