Datasheet MCM69Q618TQ6, MCM69Q618TQ6R, MCM69Q618TQ8, MCM69Q618TQ10, MCM69Q618TQ10R Datasheet (Motorola)

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Advance Information

64K x 18 Bit Synchronous
Separate I/O Fast SRAM

The Motorola MCM69Q618 is a 1 Megabit static random access memory , organized
as 64K words of 18 bits. It features separate data input and data output buffers and
incorporates input and output registers on board with high speed SRAM.

The MCM69Q618 allows the user to perform transparent write and data pass
through. Two data bus ports are provided – a data input (D) and a data output (Q) port.

The synchronous design allows for precise cycle control with the use of an external
single clock (K). Address port, data input (D0 – D17), data output (Q0 – Q17), write en­able (W
rising edge of clock (K).

writes can be intermixed. Thus, one can perform a read, a write, or a combination read/
write during any one cycle. For a combination read/write, the contents of the array are
read before the new data is written.

the contents of the array or the data presented to the input port D. For read/write or a
read cycle with G
is asserted, the Q port will instead output the data presented at the D input port.

• Single 3.3 V ± 5% Power Supply

• Fast Access Times: 6/8/10 ns Max

• Sustained Throughput of 1.49 Gigabits/Second

• Single Clock Operation

• Address, Data Input, E1

• 83 MHz Maximum Clock Cycle Time

• Self Timed Write

• Separate Data Input and Data Output Pins

• Pass–Through Feature

• Asynchronous Output Enable (G

• L VTTL Compatible I/O

• No Dead Cycles Required for Reads after Writes or for Writes after Reads

• 100 Pin TQFP Package

• Simultaneous Reads and Writes

Suggested Applications

), chip enables (E1, E2), and pass–through enable (PT) are registered on the

Any given cycle operates on only one address. However, for any cycle, reads and

By using the pass–through function, the output port Q can be made to reflect either

low, the Q port will output the contents of the array. However, if PT

, E2, PT, W, and Data Output Registers on Chip

)

— A TM — Ethernet Switches — Routers
— Cell/Frame Buffers — SNA Switches — Shared Memory

Order this document

by MCM69Q618/D

MCM69Q618

TQ PACKAGE
100 PIN TQFP

CASE 983A–01

Product Family Configurations

Part

Number

MCM69D536
MCM69D618
MCM69Q536
MCM69Q618
MCM67Q709
MCM67Q909

NOTES:

1. Tie AX and AY address ports together for the part to function as a single address part.

2. Tie GX

This document contains information on a new product. Specifications and information herein are subject to change without notice.

REV 5
11/24/97

 Motorola, Inc. 1997

MOTOROLA FAST SRAM

high for DQX to be inputs and tie WY high and GY low for DQY to be outputs.

Dual

Address

n
n

Single

Address

Note 1
Note 1

n n
n n
n n
n n

Dual

I/O

n
n

Separate

I/O

Note 2
Note 2

MCM69Q618

1

BLOCK DIAGRAM

K

A0 – A15

W

PT

E1

E2

G

16

ADDRESS

REGISTER

REGISTER

REGISTER

ENABLE

REGISTER 1

WRITE

PT

ENABLE

REGISTER 2

64K x 18 ARRAY

WRITE

DRIVER

PASS–THROUGH

DATA INPUT

REGISTER

D0 – D17 Q0 – Q17

SENSE

AMP

DATA OUTPUT

REGISTER

MCM69Q618
2

MOTOROLA FAST SRAM

PIN ASSIGNMENT

V

DD

V

SS
D9
Q9

D10
Q10

V

DD

V

SS

D11
Q11
D12

Q12

V

DD

V

SS

Q13
D13
Q14
D14

V

DD

V

SS

Q15
D15
Q16
D16

V

DD

V

SS

Q17
D17

NC

A5

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

31 32 33

A6NCA7

DD

NC

VSSV

K

NC

94 9397 96 95 89 8892 91 90 86 8587100 99 98 81828384

37 3834 35 36 42 4339 40 41 45 4644

E1

G

E2

NC

PT

A8

NC

A9

NC

50494847

80

79

78

77

76
75
74
73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

A15

NC
V
V
D8
Q8
D7
Q7
V
V
D6
Q6
D5
Q5
V
V

Q4
D4
Q3
D3
V
V
Q2
D2
Q1
D1

V
V

Q0
D0

NC

SS
DD

SS
DD

SS
DD

SS
DD

SS
DD

NC

W

A4NCA3

NC

NC

A2

NC

A1

NC

A0

V

DD

A10

NC

A11

NC

A12NCA13

NC

A14

MOTOROLA FAST SRAM

MCM69Q618

3

PIN DESCRIPTIONS

Pin Locations Symbol Type Description

30, 32, 34, 36, 38, 40, 42, 44, 46, 48, 50,

81, 83, 85, 98, 100

3, 5, 9, 11, 16, 18, 22, 24, 28, 52, 56, 58,

62, 64, 69, 71, 75, 77

90 E1 Input Synchronous Chip Enable: Active low for depth expansion.
91 E2 Input Synchronous Chip Enable: Active high for depth expansion.
92 G Input Asynchronous Output Enable Input:

96 K Input Clock: This signal registers the address, data in, and all control signals

86 PT Input Pass–through enable: Synchronous.

4, 6, 10, 12, 15, 17, 21, 23, 27, 53, 57,

59, 63, 65, 68, 70, 74, 76

88 W Input Synchronous Write.

1, 7, 13, 19, 25, 41, 54, 60, 66, 72, 78, 95 V

2, 8, 14, 20, 26, 55, 61, 67, 73, 79, 94 V

29, 31, 33, 35, 37, 39, 43, 45, 47, 49, 51,

80, 82, 84, 87, 89, 93, 97, 99

A0 – A15 Input Synchronous Address Inputs: These inputs are registered and must

D0 – D17 Input Synchronous Data Input.

Q0 – Q17 Output Synchronous Data Output.

DD

SS

NC — No Connection: There is no connection to the chip.

Supply + 3.3 V Power Supply.
Supply Ground.

meet setup and hold times.

Low — enables output buffers (Qx pins).
High — Qx pins are high impedance.

except G

.

TRUTH TABLE

Input at tn Clock Result from tn + 1 Clock Notes

Operation

Write and Pass–Through L H L L D written to A D data appears 1

Write/Read L H L H D written to A Q out from A 2

Pass–Through L H H L D data D data appears 3

Read L H H H Don’t Care Q out from A 4
Deselected X L X X Don’t Care Q is high–Z 5
Deselected H X X X Don’t Care Q is high–Z 6

NOTES:

1. W rite D to array and output D at Q.

2. Output contents of array to Q then write D to array.

3. Output D at Q. Do not write.

4. Output contents of array to Q. Do not write.

5. No operation.

6. No operation.

E1 E2 W PT Data Input D Data Output Q

K

ADDRESS & CONTROL

t

n

VALID

tn +

1

MCM69Q618
4

DATA INPUT D

DATA OUTPUT Q

PIPELINED READ ACCESS

VALID

PASS–THROUGH

VALID

MOTOROLA FAST SRAM

ABSOLUTE MAXIMUM RATINGS (See Note)

Rating Symbol Value Unit

Power Supply Voltage V
Voltage Relative to VSS for Any Pin

Except V
Output Current I
Power Dissipation P
Temperature Under Bias T
Operating Temperature T
Storage Temperature — Plastic T

NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are

DD

exceeded. Functional operation should be restricted to RECOMMENDED OPER­ATING CONDITIONS. Exposure to higher than recommended voltages for
extended periods of time could affect device reliability.

DD

Vin, V

out

bias

stg

out

D

A

– 0.5 to + 4.6 V

– 0.5 to VDD + 0.5 V

± 20 mA
TBD W

– 10 to + 85 °C

0 to + 70 °C

– 55 to + 125 °C

This is a synchronous device. All synchro­nous inputs must meet specified setup and hold
times with stable logic levels for
edges of clock (K) while the device is selected.

This device contains circuitry to protect the
inputs against damage due to high static volt­ages or electric fields; however, it is advised
that normal precautions be taken to avoid
application of any voltage higher than maxi­mum rated voltages to these high–impedance
circuits.

ALL

PACKAGE THERMAL CHARACTERISTICS (See Note 1)

Rating

Junction to Ambient (@ 200 lfm) Single Layer Board

Four Layer Board
Junction to Board (Bottom) R
Junction to Case (Top) R

NOTES:

1. Junction temperature is a function of on–chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient
temperature, air flow, board population, and board thermal resistance.

2. Per SEMI G38–87.

3. Indicates the average thermal resistance between the die and the printed circuit board.

4. Indicates the average thermal resistance between the die and the case top surface via the cold plate method (MIL SPEC–883 Method 1012.1).

Symbol TQFP Unit Notes

R

θJA

θJB
θJC

40
25

17 °C/W 3

9 °C/W 4

°C/W 2

rising

MOTOROLA FAST SRAM

MCM69Q618

5

DC OPERA TING CONDITIONS AND CHARACTERISTICS

(VDD = 3.3 V ± 5%, TA = 0 to + 70°C, Unless Otherwise Noted)

RECOMMENDED OPERATING CONDITIONS AND SUPPLY CURRENTS

Parameter Symbol Min Max Unit

Supply Voltage (Operating Voltage Range) V
Input High Voltage V
Input Low Voltage V
Input Leakage Current (All Inputs, Vin = 0 to VDD) I
Output Leakage Current (E = VIH, V
AC Supply Current (I

CMOS Standby Supply Current (Deselected, Clock (K) MCM69Q618–6 ns
Cycle Time ≥ t
Vin ≤ VSS + 0.2 V or ≥ VDD – 0.2 V) MCM69Q618–10 ns

Output Low Voltage (IOL = + 8.0 mA) V
Output High Voltage (IOH = – 4.0 mA) V

*VIL ≥ –1.5 V for t ≤ t

**VIH ≤ VDD + 1.0 V for t ≤ t

KHKH

= 0 mA) (VDD = max, f = f

out

, All Inputs Toggling at CMOS Levels MCM69Q618–8 ns

/2.

KHKH

KHKH

= 0 to VDD) I

out

) MCM69Q618–6 ns

max

/2.

MCM69Q618–8 ns

MCM69Q618–10 ns

DD

IH

IL

lkg(I)

lkg(O)
I

DDA

I

SB1

OL
OH

3.135 3.465 V

2.0 VDD + 0.5** V

– 0.5* 0.8 V

— ± 1.0 µA
— ± 1.0 µA
—

—
—

—
—
—

— 0.4 V

2.4 V

TBD
TBD
TBD

TBD
TBD
TBD

DD

mA

mA

V

CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, T

Address and Data Input Capacitance C
Control Pin Input Capacitance C
Output Capacitance C

= 0 to 70°C, Periodically Sampled Rather Than 100% Tested)

A

Parameter Symbol Max Unit

in
in

out

6 pF
6 pF
8 pF

MCM69Q618
6

MOTOROLA FAST SRAM

AC OPERA TING CONDITIONS AND CHARACTERISTICS

(VDD = 3.3 V ± 5%, TA = 0 to + 70°C, Unless Otherwise Noted)

Input Timing Measurement Reference Level 1.5 V. . . . . . . . . . . . . . .

Input Pulse Levels 0 to 3.0 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input Rise/Fall Time 3 ns. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output Timing Reference Level 1.5 V. . . . . . . . . . . . . . . . . . . . . . . . . .

Output Load Figure 1 Unless Otherwise Noted. . . . . . . . . . . . . . . . . .

READ/WRITE CYCLE TIMING

MCM69Q618–6 MCM69Q618–8 MCM69Q618–10

Parameter Symbol

Cycle Time t
Clock Access Time t
Clock Low Pulse Width t
Clock High Pulse Width t
Clock High to Data Output Invalid t
Clock High to Data Output High–Z t
Output Enable to Output Valid t
Output Enable to Output Active t
Output Disable to Output High–Z t
Setup Times: A0 – A15

E1, E2

D0 – D17

Hold Times: A0 – A15

E1, E2

D0 – D17

NOTES:

1. All read and write cycles are referenced from K.

2. Valid data from Clock High will be the data stored at the address or the last valid read cycle.

3. This parameter is sampled and not 100% tested.

4. This is a synchronous device. All synchronous inputs must meet the specified setup and hold times with stable logic levels for
edges of clock (K) while the device is selected.

PT

PT

KHKH

KHQV

KLKH
KHKL

KHQX

KHQZ
GLQV
GLQX

GHQZ

t

AVKH

W

t

WVKH

t

PTVKH
t

EVKH

t

DVKH

t

KHAX

W

t

KHWX

t

KHPTX
t

KHEX

t

KHDX

Min Max Min Max Min Max

12 — 15 — 20 — ns 1
— 6 — 8 — 10 ns 2

4 — 6 — 8 — ns
4 — 6 — 8 — ns

0 — 0 — 0 — ns
— 5 — 6 — 7 ns 3
— 6 — 8 — 10 ns

0 — 0
— 5 — 6 — 7 ns 3

2.5 — 3 — 3 — ns 4

0.5 — 2 — 2 — ns 4

—

0 — ns 3

Unit Notes

ALL

rising

MOTOROLA FAST SRAM

OUTPUT

Figure 1. AC Test Load

Z0 = 50

Ω

RL = 50

VL = 1.5 V

Ω

MCM69Q618

7

READ CYCLE TIMING

t

KHKH

K

t

AVKH

A0 – A15

E

G

Q

E low = E1 low, E2 high. E high = E1 high or E2 low.

ABCDEFGH

t

EVKH

t

GLQX

t

KLKH

t

KHEX

t

GLQV

Q(A) Q(B) Q(C)

t

KHQZ

t

KHQV

t

KHKL

t

KHQX

Q(E)

t

GHQZ

Q(F)

MCM69Q618
8

MOTOROLA FAST SRAM

COMBINATION READ/WRITE CYCLE TIMING

K

A0 – A15

E

G

Q

W

t

KHKH

ABC DEFGH

Q[A] Q[C] Q(D) Q(E) D(F)

t

WVKH

t

KHAX

Q[B]

t

KLKH

t

KHWX

t

KHKL

PT

t

DVKH

D

NOTES:

1. E

low = E1 low and E2 high. E high = E1 high or E2 low.

2. Q[A] = Previous contents of array at address A.

3. Q(A) = Data presented at input port.

D(B) D(D) D(E) D(F) D(G)

t

PTVKH

t

KHDX

t

KHAX

MOTOROLA FAST SRAM

MCM69Q618

9

E CONTROLLED WRITE

K

A0 – A15

W

E

D

NOTES:

ABCDEFGH

D(B) D(D) D(E) D(F) D(G)D(A) D(C) D(H)

1. E

low = E1 low, E2 high. E high = E1 high or E2 low.

2. Only D(B) and D(D) are written to the array.

Motorola Memory Prefix

Part Number

MCM69Q618
10

ORDERING INFORMATION

(Order by Full Part Number)

MCM 69Q618 XX XX X

Shipping Method (R = Tape and Reel, Blank = Rails)
Speed (6 = 6 ns, 8 = 8 ns, 10 = 10 ns)
Package (TQ = TQFP)

Full Part Numbers — MCM69Q618TQ6 MCM69Q618TQ8 MCM69Q618TQ10

MCM69Q618TQ6R MCM69Q618TQ8R MCM69Q618TQ10R

MOTOROLA FAST SRAM

P ACKAGE DIMENSIONS

4X

A–B0.20 (0.008) H

D

80 51

–D–

TQFP PACKAGE

100 PIN

CASE 983A–01

2X 30 TIPS

A–B0.20 (0.008) C D

e

e/2

–A–

–H–
–C–

SEATING
PLANE

0.05 (0.002)

81

100

S

2X 20 TIPS

A

A2

A1

D1/2

C D

S

R1

VIEW AB

50

E/2

–B–

E1

E

E1/2

31

301

BASE

METAL

B
B

–X–

X=A, B, OR D

VIEW Y

PLATING

b1

c

c1

D/2

D1

D

0.13 (0.005) D

A–B0.20 (0.008)

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DATUM PLANE –H– IS LOCATED AT BOTTOM OF
LEAD AND IS COINCIDENT WITH THE LEAD
WHERE THE LEAD EXITS THE PLASTIC BODY AT
THE BOTTOM OF THE PARTING LINE.

4. DATUMS –A–, –B– AND –D– TO BE DETERMINED
AT DATUM PLANE –H–.

5. DIMENSIONS D AND E TO BE DETERMINED AT
SEATING PLANE –C–.

6. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS 0.25
(0.010) PER SIDE. DIMENSIONS D1 AND B1 DO
INCLUDE MOLD MISMATCH AND ARE
DETERMINED AT DATUM PLANE –H–.

7. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. DAMBAR PROTRUSION SHALL
NOT CAUSE THE b DIMENSION TO EXCEED 0.45
(0.018).

DIM MIN MAX MIN MAX

A ––– 1.60 ––– 0.063
A1 0.05 0.15 0.002 0.006
A2 1.35 1.45 0.053 0.057

b 0.22 0.38 0.009 0.015
b1 0.22 0.33 0.009 0.013

c 0.09 0.20 0.004 0.008
c1 0.09 0.16 0.004 0.006

D 22.00 BSC 0.866 BSC
D1 20.00 BSC 0.787 BSC

E 16.00 BSC 0.630 BSC
E1 14.00 BSC 0.551 BSC

e 0.65 BSC 0.026 BSC

L 0.45 0.75 0.018 0.030
L1 1.00 REF 0.039 REF
L2 0.50 REF

S 0.20 ––– 0.008 –––
R1 0.08 ––– 0.003 –––
R2 0.08 0.20 0.003 0.008

q
q

1

q

2

q

3

L1

L2

q

2

q

3

0.10 (0.004)

C

VIEW AB

q

1

0.25 (0.010)

GAGE PLANE

R2

L

q

b

M

S

A–B

C

SECTION B–B

INCHESMILLIMETERS

0.020 REF

0 7 0 7

_

_

_

0 ––– 0 –––

_

11 13 11 13

_

_

11 13 11 13

_

_

_
_
_

_
_

_

S

MOTOROLA FAST SRAM

MCM69Q618

11

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty , representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. “T ypical” parameters which may be provided in Motorola
data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”
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Opportunity/Affirmative Action Employer.

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MCM69Q618
12

◊

MOTOROLA FAST SRAM

MCM69Q618/D