Datasheet MCM69F819ZP8R, MCM69F819ZP11R, MCM69F819ZP7.5, MCM69F819ZP8.5, MCM69F819TQ8.5R Datasheet (Motorola)

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

256K x 18 Bit Flow–Through
BurstRAM Synchronous
Fast Static RAM

Order this document

by MCM69F819/D

MCM69F819

The MCM69F819 is a 4M bit synchronous fast static RAM designed to provide
a burstable, high performance, secondary cache for the PowerPC and other
high performance microprocessors. It is organized as 256K words of 18 bits
each. This device integrates input registers, a 2–bit address counter, and high
speed SRAM onto a single monolithic circuit for reduced parts count in cache
data RAM applications. Synchronous design allows precise cycle control with the
use of an external clock (K).

Addresses (SA), data inputs (DQx), and all control signals except output
enable (G
edge–triggered noninverting registers.

addresses can be generated internally by the MCM69F819 (burst sequence
operates in linear or interleaved mode dependent upon the state of LBO
controlled by the burst address advance (ADV) input pin.

clock (K) input. This feature eliminates complex off–chip write pulse generation
and provides increased timing flexibility for incoming signals.

nous write enable (SW) are provided to allow writes to either individual bytes or
to all bytes. The two bytes are designated as “a” and “b”. SBa
SBb
asserted with SW. All bytes are written if either SGW is asserted or if all SBx and
SW

from the memory array .
operate on a 2.5 V or 3.3 V power supply . All inputs and outputs are JEDEC stan-

dard JESD8–5 compatible.

• MCM69F819–7.5: 7.5 ns Access/ 8.5 ns Cycle (117 MHz)

• 3.3 V + 10%, – 5% Core Power Supply , 2.5 V or 3.3 V I/O Supply

• ADSP

• Selectable Burst Sequencing Order (Linear/Interleaved)

• Single–Cycle Deselect Timing

• Internally Self–Timed Write Cycle

• Byte Write and Global Write Control

• PB1 Version 2.0 Compatible

• JEDEC Standard 119–Pin PBGA and 100–Pin TQFP Packages

) and linear burst order (LBO) are clock (K) controlled through positive–

Bursts can be initiated with either ADSP

Write cycles are internally self–timed and are initiated by the rising edge of the

Synchronous byte write (SBx

controls DQb. Individual bytes are written if the selected byte writes SBx are

are asserted.

For read cycles, a flow–through SRAM allows output data to simply flow freely

The MCM69F819 operates from a 3.3 V core power supply and all outputs

MCM69F819–8: 8 ns Access/10 ns Cycle (100 MHz)
MCM69F819–8.5: 8.5 ns Access/11 ns Cycle 90 MHz)
MCM69F819–11: 11 ns Access/20 ns Cycle (50 MHz)

, ADSC, and ADV Burst Control Pins

), synchronous global write (SGW), and synchro-

or ADSC input pins. Subsequent burst

) and

controls DQa and

ZP PACKAGE

PBGA

CASE 999–02

TQ PACKAGE

TQFP

CASE 983A–01

The PowerPC name is a trademark of IBM Corp., used under license therefrom.

REV 7
1/22/98

 Motorola, Inc. 1998

MOTOROLA FAST SRAM

MCM69F819

1

LBO

ADV

K
ADSC
ADSP

SA
SA1
SA0

FUNCTIONAL BLOCK DIAGRAM

K2

ADDRESS

REGISTER

18

BURST

COUNTER

CLR

2

16

2

18

256K x 18

ARRAY

SGW

SW

SBa

SBb

SE1
SE2

SE3

G

WRITE

REGISTER

a

WRITE

REGISTER

b

K2

ENABLE

REGISTER

2

DATA–IN

REGISTER

K

18

18

DQa – DQb

MCM69F819
2

MOTOROLA FAST SRAM

PIN ASSIGNMENTS

6543217
A
B
C

D
E

F
G

H
J

K
L
M

N
P

R
T

U

SA SA SA SA

V

DDQ

NC SE2 SA ADSC

SA SA SA SA

NC

DQb NC VSSNC DQa

DQbNC

V

NC V

DDQ

DQb

NC VSSSGW

V

V

V

DD

DDQ
NC DQb V

NCDQb

DQb V

DDQ

NCDQb

NC DQb VSSSA0

SA SA

NC

SA SA SA SA

NC

DDQ

SS
SS

SBbDQbNC

NCV

SS

V

SS
SS
SS

LBO

NCNC

ADSP

SA

SE3

V

DD

V

SS

V

NCSE1V

SS

DQa

V

G

SS

NCADV

V

SS

V

DQa

SS

V

NCV

DD
KV

NC
SW

DD

NC

NC

V
V
V

SS

SS
SS
SS

NCV

NC

NC

DQaSBa

NC

DQaSA1V

NC

NC

DD

V

V

V

V

V

DDQ

NC
NC
NC

DQa

DDQ

DQa

NC

DDQ

DQa

NC
DDQ

NC

DQa

NC
NC

DDQ

V

V

DDQ

V

V

DDQ

NC
NC
NC

DDQ

V

SS
NC

NC
DQb
DQb

V

SS
DQb

DQb

NC

V

DD

NC

V

SS
DQb

DQb

DDQ

V

SS

DQb
DQb
DQb

NC

V

SS

NC

NC

NC

1
2
3
4
5
6
7
8

9

10
11
12
13
14
15
16
17
18
19
20

21
22
23
24
25
26
27
28
29
30

31 3233

SASASE1

DD

SE2

NC

SBa

SBb

NC

94 93979695 89889291 90 86858710099 98 81828384

3738343536 42433940 41 454644

SE3

K

VSSV

SW

SGW

G

ADSP

ADSC

ADV

SA

SA

SA

80
79

NC

78

NC
V

77

DDQ

76

V

SS

NC

75

DQa

74
73

DQa

72

DQa

71

V

SS

70

V

DDQ

69

DQa

68

DQa
V

67

SS

NC

66

V

65

DD

NC

64

DQa

63

DQa

62

V

61

DDQ

V

60

SS

DQa

59
58

DQa
NC

57

NC

56

V

55

SS

V

54

DDQ

NC

53
52

NC
NC

51

50494847

TOP VIEW 119 BUMP PBGA

SASASA

LBO

SA

SA1

TOP VIEW 100 PIN TQFP

SA0

NC

NC

V

SS

DD

V

NC

NC

SA

SASASA

SA

SA

SA

Not to Scale

MOTOROLA FAST SRAM

MCM69F819

3

PBGA PIN DESCRIPTIONS

Pin Locations Symbol

4B ADSC Input Synchronous Address Status Controller: Active low, interrupts any

4A ADSP Input Synchronous Address Status Processor: Active low, interrupts any

4G ADV Input Synchronous Address Advance: Increments address count in

(a) 6D, 7E, 6F, 7G, 6H, 7K, 6L, 6N, 7P

(b) 1D, 2E, 2G, 1H, 2K, 1L, 2M, 1N, 2P

4F G Input Asynchronous Output Enable Input:

4K K Input Clock: This signal registers the address, data in, and all control signals

3R LBO Input Linear Burst Order Input: This pin must remain in steady state (this

2A, 3A, 5A, 6A, 3B, 5B, 2C, 3C,

5C, 6C, 2R, 6R, 2T, 3T, 5T, 6T

4N, 4P SA1, SA0 Input Synchronous Address Inputs: These pins must be wired to the two

5L, 3G
(a) (b)

4E SE1 Input Synchronous Chip Enable: Active low to enable chip.

2B SE2 Input Synchronous Chip Enable: Active high for depth expansion.
6B SE3 Input Synchronous Chip Enable: Active low for depth expansion.
4H SGW Input Synchronous Global Write: This signal writes all bytes regardless of the

4M SW Input Synchronous Write: This signal writes only those bytes that have been

4C, 2J, 4J, 6J, 4R V

1A, 7A, 1F, 7F, 1J, 7J, 1M, 7M, 1U, 7U V

3D, 5D, 3E, 5E, 3F, 5F, 5G, 3H, 5H,
3K, 5K, 3L, 3M, 5M, 3N, 5N, 3P, 5P

1B, 7B, 1C, 7C, 2D, 4D, 7D, 1E, 6E,

2F, 1G, 6G, 2H, 7H, 3J, 5J, 1K, 6K,
2L, 4L, 7L, 6M, 2N, 7N, 1P, 6P, 1R,

5R, 7R, 1T, 4T, 7T, 2U, 3U, 4U, 5U, 6U

Type Description

ongoing burst and latches a new external address. Used to initiate a

READ, WRITE, or chip deselect.

ongoing burst and latches a new external address. Used to initiate a

new READ, WRITE, or chip deselect (exception — chip deselect does

not occur when ADSP

accordance with counter type selected (linear/interleaved).

DQx I/O Synchronous Data I/O: “x” refers to the byte being read or written

SA Input Synchronous Address Inputs: These inputs are registered and must

SBx Input Synchronous Byte Write Inputs: “x” refers to the byte being written (byte

DD

DDQ

V

SS

NC — No Connection: There is no connection to the chip.

Supply Core Power Supply.
Supply I/O Power Supply.
Supply Ground.

(byte a, b).

Low — enables output buffers (DQx pins).

High — DQx pins are high impedance.

except G

signal not registered or latched). It must be tied high or low.

Low — linear burst counter (68K/PowerPC).

High — interleaved burst counter (486/i960/Pentium).

meet setup and hold times.

LSBs of the address bus for proper burst operation. These inputs are

registered and must meet setup and hold times.

a, b). SGW

Negated high — blocks ADSP

asserted.

status of the SBx

being used, tie this pin high.

selected using the byte write SBx

are being used, tie this pin low.

and LBO.

overrides SBx.

is asserted and SE1 is high).

or deselects chip when ADSC is

and SW signals. If only byte write signals SBx are

pins. If only byte write signals SBx

MCM69F819
4

MOTOROLA FAST SRAM

TQFP PIN DESCRIPTIONS

Pin Locations Symbol

85 ADSC Input Synchronous Address Status Controller: Active low, interrupts any

84 ADSP Input Synchronous Address Status Processor: Active low, interrupts any

83 ADV Input Synchronous Address Advance: Increments address count in

(a) 58, 59, 62, 63, 68, 69, 72, 73, 74

(b) 8, 9, 12, 13, 18, 19, 22, 23, 24

86 G Input Asynchronous Output Enable Input:

89 K Input Clock: This signal registers the address, data in, and all control signals

31 LBO Input Linear Burst Order Input: This pin must remain in steady state (this

32, 33, 34, 35, 44, 45, 46, 47, 48, 49, 50,

80, 81, 82, 99, 100

36, 37 SA1, SA0 Input Synchronous Address Inputs: These pins must be wired to the two

93, 94

(a) (b)

88 SGW Input Synchronous Global Write: This signal writes all bytes regardless of the

98 SE1 Input Synchronous Chip Enable: Active low to enable chip.

97 SE2 Input Synchronous Chip Enable: Active high for depth expansion.
92 SE3 Input Synchronous Chip Enable: Active low for depth expansion.
87 SW Input Synchronous Write: This signal writes only those bytes that have been

15, 41, 65, 91 V

4, 11, 20, 27, 54, 61, 70, 77 V

5, 10, 17, 21, 26, 40,

55, 60, 67, 71, 76, 90

1, 2, 3, 6, 7, 14, 16, 25, 28, 29, 30, 38,

39, 42, 43, 51, 52, 53, 56, 57, 64, 66, 75,

78, 79, 95, 96

Type Description

ongoing burst and latches a new external address. Used to initiate a

READ, WRITE, or chip deselect.

ongoing burst and latches a new external address. Used to initiate a

new READ, WRITE, or chip deselect (exception — chip deselect does

not occur when ADSP

accordance with counter type selected (linear/interleaved).

DQx I/O Synchronous Data I/O: “x” refers to the byte being read or written

SA Input Synchronous Address Inputs: These inputs are registered and must

SBx Input Synchronous Byte Write Inputs: “x” refers to the byte being written (byte

DD

DDQ

V

SS

NC — No Connection: There is no connection to the chip.

Supply Core Power Supply.
Supply I/O Power Supply.
Supply Ground.

(byte a, b).

Low — enables output buffers (DQx pins).

High — DQx pins are high impedance.

except G

signal not registered or latched). It must be tied high or low.

Low — linear burst counter (68K/PowerPC).

High — interleaved burst counter (486/i960/Pentium).

meet setup and hold times.

LSBs of the address bus for proper burst operation. These inputs are

registered and must meet setup and hold times.

a, b). SGW

status of the SBx

being used, tie this pin high.

Negated high — blocks ADSP

asserted.

selected using the byte write SBx

are being used, tie this pin low.

and LBO.

overrides SBx.

is asserted and SE1 is high).

and SW signals. If only byte write signals SBx are

or deselects chip when ADSC is

pins. If only byte write signals SBx

MOTOROLA FAST SRAM

MCM69F819

5

TRUTH TABLE (See Notes 1 Through 5)

Address

Next Cycle

Deselect None 1 X X X 0 X X High–Z X
Deselect None 0 X 1 0 X X X High–Z X
Deselect None 0 0 X 0 X X X High–Z X
Deselect None X X 1 1 0 X X High–Z X
Deselect None X 0 X 1 0 X X High–Z X
Begin Read External 0 1 0 0 X X 0 High–Z X
Begin Read External 0 1 0 1 0 X 0 High–Z READ
Continue Read Next X X X 1 1 0 1 High–Z READ
Continue Read Next X X X 1 1 0 0 DQ READ
Continue Read Next 1 X X X 1 0 1 High–Z READ
Continue Read Next 1 X X X 1 0 0 DQ READ
Suspend Read Current X X X 1 1 1 1 High–Z READ
Suspend Read Current X X X 1 1 1 0 DQ READ
Suspend Read Current 1 X X X 1 1 1 High–Z READ
Suspend Read Current 1 X X X 1 1 0 DQ READ
Begin Write External 0 1 0 1 0 X X High–Z WRITE
Continue Write Next X X X 1 1 0 X High–Z WRITE
Continue Write Next 1 X X X 1 0 X High–Z WRITE
Suspend Write Current X X X 1 1 1 X High–Z WRITE
Suspend Write Current 1 X X X 1 1 X High–Z WRITE

NOTES:

1. X = Don’t Care. 1 = logic high. 0 = logic low.

2. Write is defined as either 1) any SBx

3. G

is an asynchronous signal and is not sampled by the clock K. G drives the bus immediately (t

4. On write cycles that follow read cycles, G
also remain negated at the completion of the write cycle to ensure proper write data hold times.

5. This read assumes the RAM was previously deselected.

Used

SE1 SE2 SE3 ADSP ADSC ADV G

and SW low or 2) SGW is low.

must be negated prior to the start of the write cycle to ensure proper write data setup times. G must

3

DQx Write 2,

) following G going low.

GLQX

4

5

5

LINEAR BURST ADDRESS TABLE (LBO = V

1st Address (External)

X . . . X00 X . . . X01 X . . . X10 X . . . X11
X . . . X01 X . . . X10 X . . . X11 X . . . X00
X . . . X10 X . . . X11 X . . . X00 X . . . X01
X . . . X11 X . . . X00 X . . . X01 X . . . X10

2nd Address (Internal) 3rd Address (Internal) 4th Address (Internal)

INTERLEAVED BURST ADDRESS TABLE (LBO = V

1st Address (External) 2nd Address (Internal) 3rd Address (Internal) 4th Address (Internal)

X . . . X00 X . . . X01 X . . . X10 X . . . X11
X . . . X01 X . . . X00 X . . . X11 X . . . X10
X . . . X10 X . . . X11 X . . . X00 X . . . X01
X . . . X11 X . . . X10 X . . . X01 X . . . X00

SS

)

)

DD

WRITE TRUTH TABLE

Cycle Type SGW SW SBa SBb

Read H H X X
Read H L H H
Write Byte a H L L H
Write Byte b H L H L
Write All Bytes H L L L
Write All Bytes L X X X

MCM69F819
6

MOTOROLA FAST SRAM

ABSOLUTE MAXIMUM RATINGS (See Note 1)

Rating Symbol Value Unit Notes

Power Supply Voltage V
I/O Supply Voltage V
Input Voltage Relative to VSS for

Any Pin Except V
Input Voltage (Three–State I/O) V

Output Current (per I/O) I
Package Power Dissipation P
Ambient Temperature T
Die Temperature T
Temperature Under Bias T
Storage Temperature T

NOTES:

1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED OPER­ATING CONDITIONS. Exposure to higher than recommended voltages for extended
periods of time could affect device reliability.

2. This is a steady–state DC parameter that is in effect after the power supply has
achieved its nominal operating level. Power sequencing is not necessary.

3. Power dissipation capability is dependent upon package characteristics and use
environment. See Package Thermal Characteristics.

DD

DD

DDQ

Vin, V

out

bias

stg

VSS – 0.5 to + 4.6 V
VSS – 0.5 to V

out

IT

D
A

J

VSS – 0.5 to

VDD + 0.5

VSS – 0.5 to

V

DDQ

0 to 70 °C

– 10 to 85 °C

– 55 to 125 °C

V 2

DD

V 2

+ 0.5

± 20 mA

1.6 W 3

110 °C 3

V 2

This device contains circuitry to protect the
inputs against damage due to high static volt­ages or electric fields; however, it is advised
that normal precautions be taken to avoid
application of any voltage higher than maxi­mum rated voltages to this high–impedance
circuit.

PACKAGE THERMAL CHARACTERISTICS — PBGA

Rating Symbol Max Unit Notes

Junction to Ambient (@ 200 lfm) Single Layer Board

Four Layer Board
Junction to Board (Bottom) R
Junction to Case (Top) R

NOTES:

1. Junction temperature is a function of on–chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient
temperature, air flow, board population, and board thermal resistance.

2. Per SEMI G38–87.

3. Indicates the average thermal resistance between the die and the printed circuit board.

4. Indicates the average thermal resistance between the die and the case top surface via the cold plate method (MIL SPEC–883 Method 1012.1).

R

θJA

θJB

θJC

38
22

14 °C/W 3

5 °C/W 4

°C/W 1, 2

PACKAGE THERMAL CHARACTERISTICS — TQFP

Rating Symbol Max Unit Notes

Junction to Ambient (@ 200 lfm) Single Layer Board

Four Layer Board
Junction to Board (Bottom) R
Junction to Case (Top) R

NOTES:

1. Junction temperature is a function of on–chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient
temperature, air flow, board population, and board thermal resistance.

2. Per SEMI G38–87.

3. Indicates the average thermal resistance between the die and the printed circuit board.

4. Indicates the average thermal resistance between the die and the case top surface via the cold plate method (MIL SPEC–883 Method 1012.1).

R

θJA

θJB

θJC

40
25

17 °C/W 3

9 °C/W 4

°C/W 1, 2

MOTOROLA FAST SRAM

MCM69F819

7

DC OPERA TING CONDITIONS AND CHARACTERISTICS

(VDD = 3.3 V + 10%, – 5%, TA = 0 to 70°C, Unless Otherwise Noted)

RECOMMENDED OPERATING CONDITIONS: 2.5 V I/O Supply

Parameter Symbol Min Typ Max Unit

Supply Voltage V
I/O Supply Voltage V
Input Low Voltage V
Input High Voltage V
Input High Voltage (I/O Pins) V

(Voltages Referenced to VSS = 0 V)

DD

DDQ

IL

IH

IH2

3.135 3.3 3.6 V

2.375 2.5 2.9 V
– 0.3 — 0.7 V

1.7 — VDD + 0.3 V

1.7 — V

RECOMMENDED OPERATING CONDITIONS: 3.3 V I/O Supply (Voltages Referenced to V

Parameter Symbol Min Typ Max Unit

Supply Voltage V
I/O Supply Voltage V
Input Low Voltage V
Input High Voltage V
Input High Voltage (I/O Pins) V

V

IH

V

SS

DD

DDQ

IL

IH

IH2

3.135 3.3 3.6 V

3.135 3.3 V
– 0.5 — 0.8 V

2 — VDD + 0.5 V
2 — V

SS

= 0 V)

+ 0.3 V

DDQ

DD

+ 0.5 V

DDQ

V

VSS – 1.0 V

20% t

KHKH

Figure 1. Undershoot Voltage

(MIN)

MCM69F819
8

MOTOROLA FAST SRAM

DC CHARACTERISTICS AND SUPPLY CURRENTS

Parameter Symbol Min Typ Max Unit Notes

Input Leakage Current (0 V ≤ Vin ≤ VDD) I
Output Leakage Current (0 V ≤ Vin ≤ V
AC Supply Current (Device Selected, MCM69F819–7.5

All Outputs Open, Freq = Max) MCM69F819–8
Includes VDD Only MCM69F819–8.5

CMOS Standby Supply Current (Device Deselected, Freq = 0,
VDD = Max, All Inputs Static at CMOS Levels)

TTL Standby Supply Current (Device Deselected, Freq = 0,
VDD = Max, All Inputs Static at TTL Levels)

Clock Running (Device Deselected, MCM69F819–7.5
Freq = Max, VDD = Max, MCM69F819–8
All Inputs Toggling at CMOS Levels) MCM69F819–8.5

Static Clock Running (Device Deselected, Freq = Max,
VDD = Max, All Inputs Static at TTL Levels)

Output Low Voltage (IOL = 2 mA) V
Output High Voltage (IOL = – 2 mA) V
Output Low Voltage (IOL = 8 mA) V
Output High Voltage (IOL = – 4 mA) V

NOTES:

1. Reference AC Operating Conditions and Characteristics for input and timing.

2. All addresses transition simultaneously low (LSB) then high (MSB).

3. Data states are all zero.

4. Device is deselected as defined by the Truth Table.

5. CMOS levels for I/O’s are VIT ≤ VSS + 0.2 V or ≥ V

6. TTL levels for I/O’s are VIT ≤ VIL or ≥ V

) I

DDQ

MCM69F819–11

MCM69F819–11

= 2.5 V V

DDQ

= 2.5 V V

DDQ

= 3.3 V V

DDQ

= 3.3 V V

DDQ

DDQ

. TTL levels for other inputs are Vin ≤ VIL or ≥ VIH.

IH2

lkg(O)
I

I

I

I

I

– 0.2 V. CMOS levels for other inputs are Vin ≤ VSS + 0.2 V or ≥ VDD – 0.2 V.

lkg(I)

DDA

SB2

SB3

SB4

SB5

OL

OH

OL2

OH2

— — ± 1 µA
— — ± 1 µA
— — 350

325
300
250

— — 45 mA 4, 5

— — 50 mA 4, 6

— — 190

175
165
145

— — 95 mA 4, 6

— — 0.7 V

1.7 — — V
— — 0.4 V

2.4 — — V

mA 1, 2, 3

mA 4, 5

CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, T

Parameter

Input Capacitance C
Input/Output Capacitance C

= 0 to 70°C, Periodically Sampled Rather Than 100% Tested)

A

Symbol Min Typ Max Unit

I/O

in

— 4 5 pF
— 7 8 pF

MOTOROLA FAST SRAM

MCM69F819

9

AC OPERA TING CONDITIONS AND CHARACTERISTICS

(VDD = 3.3 V + 10%, – 5%, TA = 0 to 70°C, Unless Otherwise Noted)

Input Timing Measurement Reference Level 1.25 V. . . . . . . . . . . . . .

Input Pulse Levels 0 to 2.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input Rise/Fall Time 1.0 V/ns (20 to 80%). . . . . . . . . . . . . . . . . . . . . .

READ/WRITE CYCLE TIMING (See Notes 1 and 2)

MCM69F819–7.5

117 MHz

Parameter Symbol

Cycle Time t
Clock High Pulse Width t
Clock Low Pulse Width t
Clock Access Time t
Output Enable to Output

Valid
Clock High to Output Active t
Clock High to Output

Change
Output Enable to Output

Active
Output Disable to Q High–Z t
Clock High to Q High–Z t
Setup Times: Address

Hold Times: Address

NOTES:

ADSP

, ADSC, ADV

Data In

Write

Chip Enable

ADSP

, ADSC, ADV

Data In

Write

Chip Enable

1. Write is defined as either any SBx
or ADSC is asserted.

2. All read and write cycle timings are referenced from K or G

3. Measured at

4. This parameter is sampled and not 100% tested.

5. At any given voltage and temperature, t

± 200 mV from steady state.

KHKH

KHKL
KLKH

KHQV

t

GLQV

KHQX1

t

KHQX2

t

GLQX

GHQZ
KHQZ

t

ADKH

t

ADSKH

t

DVKH

t

WVKH

t

EVKH

t

KHAX

t

KHADSX

t

KHDX

t

KHWX

t

KHEX

Min Max Min Max Min Max Min Max

8.5 — 10 — 11 — 20 — ns
3 — 4 — 4.5 — 4.5 — ns
3 — 4 — 4.5 — 4.5 — ns

— 7.5 — 8 — 8.5 — 11 ns
— 3.5 — 3.5 — 3.5 — 3.5 ns

0 — 0 — 0 — 0 — ns 3, 4, 5
2 — 2 — 2 — 2 — ns 3, 4

0 — 0 — 0 — 0 — ns 3, 4

— 3.5 — 3.5 — 3.5 — 3.5 ns 3, 4

2 3.5 2 3.5 2 3.5 2 3.5 ns 3, 4, 5

1.5 — 2 — 2 — 2 — ns

0.5 — 0.5 — 0.5 — 0.5 — ns

and SW low or SGW is low. Chip Enable is defined as SE1 low , SE2 high, and SE3 low whenever ADSP

max is less than t

KHQZ

Output Timing Reference Level 1.25 V. . . . . . . . . . . . . . . . . . . . . . . . .

Output Load See Figure 2 Unless Otherwise Noted. . . . . . . . . . . . . .

MCM69F819–8

100 MHz

.

KHQX1

MCM69F819–8.5

90 MHz

min for a given device and from device to device.

MCM69F819–1 1

50 MHz

Unit Notes

MCM69F819
10

OUTPUT

Z0 = 50

Ω

Figure 2. AC Test Load

RL = 50

1.25 V

Ω

MOTOROLA FAST SRAM

5

4

OUTPUT

WA VEFORM

3

C

L

CLOCK ACCESS TIME DELA Y (ns)

2

1

0

LUMPED CAP ACITANCE, CL (pF)

Figure 3. Lumped Capacitive Load and T ypical Derating Curve

OUTPUT LOAD

INPUT

OUTPUT
BUFFER

UNLOADED RISE AND FALL TIME MEASUREMENT

2.0

0.5

TEST POINT

2.0

0.5

100806040200

OUTPUT

WAVEFORM

NOTES:

1. Input waveform has a slew rate of 1 V/ns.

2. Rise time is measured from 0.5 to 2.0 V unloaded.

3. Fall time is measured from 2.0 to 0.5 V unloaded.

2.0

0.5 0.5

t

r

Figure 4. Unloaded Rise and Fall Time Characterization

2.0

t

f

MOTOROLA FAST SRAM

MCM69F819

11

VOLTAGE (V)

– 0.5

0

0.8

1.25

1.5

2.3

2.7

2.9

PULL–UP

I (mA) MIN I (mA) MAX

– 38
– 38
– 38
– 26

– 20

0
0
0

– 105
– 105
– 105

– 83
– 70

– 30
– 10

0

(a) Pull–Up for 2.5 V I/O Supply

2.9

2.5

2.3

2.1

1.25

VOLTAGE (V)

0.8

0

0 – 38 – 105

CURRENT (mA)

3.6

VOLTAGE (V)

– 0.5

0

1.4

1.65

2.0

3.135

3.6

VOLTAGE (V)

– 0.5

0

0.4

0.8

1.25

1.6

2.8

3.2

3.4

PULL–UP

I (mA) MIN I (mA) MAX

– 50
– 50
– 50
– 46

– 35

0
0

PULL–DOWN

I (mA) MIN I (mA) MAX

0
0

10
20

31
40
40
40
40

– 150
– 150
– 150
– 130

– 101

– 25

0

0
0

20
40

63
80
80
80
80

3.135

2.8

1.65

VOLTAGE (V)

1.4

0

0

(b) Pull–Up for 3.3 V I/O Supply

V

DD

1.6

1.25

VOLTAGE (V)

0.3

0

040 80

(c) Pull–Down

– 40

CURRENT (mA)

CURRENT (mA)

– 120– 80

MCM69F819
12

Figure 5. T ypical Output Buffer Characteristics

MOTOROLA FAST SRAM

CD

READ/WRITE CYCLES

GLQV

t

Q(B) D(C) D(C+1) D(C+2) D(C+3) Q(D)

GLQX

t

SE2, SE3

ADSP, SA

GHQZ

t

BURST WRITE

IGNORED

KLKH

t

KHKL

t

KHKH

t

Q(B+2) Q(B+3)

BURST WRAPS AROUND

KHQX2

Q(B) Q(B+1)

t

KHQV

t

AB

K

SA

ADSP

ADSC

ADV

SE1

E

W

G

Q(A)Q(n)

DQx

KHQX1

t

KHQZ

t

BURST READSINGLE READ

DESELECTED SINGLE READ

W low = SGW low and/or SW and SBx low.

NOTE: E low = SE2 high and SE3 low.

MOTOROLA FAST SRAM

MCM69F819

13

APPLICATION INFORMATION

STOP CLOCK OPERATION

In the stop clock mode of operation, the SRAM will hold all
state and data values even though the clock is not running
(full static operation). The SRAM design allows the clock to
start with ADSP

and ADSC, and stops the clock after the last

write data is latched, or the last read data is driven out.

When starting and stopping the clock, the AC clock timing
and parametrics must be strictly maintained. For example,
clock pulse width and edge rates must be guaranteed when
starting and stopping the clocks.To achieve the lowest power

STOP CLOCK WITH READ TIMING

K

ADSP

ADDRESS

A1 A2

operation for all three stop clock modes, stop read, stop
write, and stop deselect:

To achieve the lowest power operation for all three stop

clock modes, stop read, stop write, and stop deselect:

• Force the clock to a low state.

• Force the control signals to an inactive state (this

guarantees any potential source of noise on the clock
input will not start an unplanned on activity).

• Force the address inputs to a low state (VIL), preferably
< 0.2 V.

ADV

DQx

ADSP

(INITIATES

BURST READ)

NOTE: For lowest possible power consumption during stop clock, the addresses should be driven to a low state (VIL).

Best results are obtained if VIL < 0.2 V.

Q(A1)

CLOCK STOP

(CONTINUE

BURST READ)

WAKE UP ADSP

(INITIATES BURST READ)

Q(A2)Q(A1 + 1)

MCM69F819
14

MOTOROLA FAST SRAM

K

ADSC

STOP CLOCK WITH WRITE TIMING

ADDRESS

WRITE

ADV

DQx

NOTE: While the clock is stopped, DATA IN must be fixed in a high (VIH) or low (VIL) state to reduce the DC current of the

input buffers. For lowest power operation, all data and address lines should be held in a low (VIL) state and control
lines held in an inactive state.

A1 A2

D(A1)DATA IN D(A1 + 1) D(A2)

ADSC

(INITIATES

BURST WRITE)

CLOCK STOP

(CONTINUE

BURST WRITE)

VIH OR VIL FIXED (SEE NOTE)

HIGH–Z

WAKE UP ADSC

(INITIATES BURST WRITE)

MOTOROLA FAST SRAM

MCM69F819

15

K

ADSC

SE1

STOP CLOCK WITH DESELECT OPERATION TIMING

DATA IN

DQx

NOTE: While the clock is stopped, DATA IN must be fixed in a high (VIH) or low (VIL) state to reduce the DC current of the

DATA DATA

CONTINUE

BURST READ

input buffers. For lowest power operation, all data and address lines should be held in a low (VIL) state and control
lines held in an inactive state.

CLOCK STOP

(DESELECTED)

VIH OR VIL FIXED (SEE NOTE)

HIGH–Z

WAKE UP

(DESELECTED)

MCM69F819
16

MOTOROLA FAST SRAM

NON–BURST SYNCHRONOUS OPERATION

Although this BurstRAM has been designed for PowerPC–
based and other high end MPU–based systems, these
SRAMs can be used in other high speed L2 cache or
memory applications that do not require the burst address
feature. Most L2 caches designed with a synchronous inter­face can make use of the MCM69F819. The burst counter
feature of the BurstRAM can be disabled, and the SRAM can

CONTROL PIN TIE VALUES EXAMPLE

Non–Burst ADSP ADSC ADV SE1 SE2 LBO

Sync Non–Burst,
Flow–Through
SRAM

NOTE: Although X is specified in the table as a don’t care, the pin

must be tied either high or low.

H L H L H X

(H ≥ VIH, L ≤ VIL)

be configured to act upon a continuous stream of addresses.
See Figure 6.

K

ADDR A B CD EFGH

SE3

W

G

DQ

Motorola Memory Prefix
Part Number

Q(B)Q(A)

Q(D)Q(C) D(E)

D(F)

WRITESREADS

Figure 6. Example Configuration as Non–Burst Synchronous SRAM

ORDERING INFORMATION

(Order by Full Part Number)

MCM 69F819 XX X X

Blank = Trays, R = Tape and Reel
Speed (7.5 = 7.5 ns, 8 = 8 ns,

8.5 = 8.5 ns, 11 = 11 ns)

Package (ZP = PBGA, TQ = TQFP)

D(G)

D(H)

Full Part Numbers — MCM69F819ZP7.5 MCM69F819ZP8 MCM69F819ZP8.5 MCM69F819ZP11

MOTOROLA FAST SRAM

MCM69F819ZP7.5R MCM69F819ZP8R MCM69F819ZP8.5R MCM69F819ZP11R
MCM69F819TQ7.5 MCM69F819TQ8 MCM69F819TQ8.5 MCM69F819TQ11
MCM69F819TQ7.5R MCM69F819TQ8R MCM69F819TQ8.5R MCM69F819TQ1 1R

MCM69F819

17

P ACKAGE DIMENSIONS

ZP PACKAGE

7 x 17 BUMP PBGA

CASE 999–02

0.20

4X

C

E

D2

E2

B

7654321

D

D1

16X

e

6X e

E1

TOP VIEW

A3

BOTTOM VIEW

0.25 A

0.35 A

A2

A

119X

A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U

b

M

0.3 CA B

M

0.15 A

0.20 A

NOTES:

1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.

2. ALL DIMENSIONS IN MILLIMETERS.

3. DIMENSION b IS THE MAXIMUM SOLDER BALL
DIAMETER MEASURED PARALLEL TO DATUM A.

4. DATUM A, THE SEATING PLANE, IS DEFINED BY
THE SPHERICAL CROWNS OF THE SOLDER
BALLS.

MILLIMETERS

DIM MIN MAX

A ––– 2.40
A1 0.50 0.70
A2 1.30 1.70
A3 0.80 1.00

D 22.00 BSC
D1 20.32 BSC
D2 19.40 19.60

E 14.00 BSC
E1 7.62 BSC
E2 11.90 12.10

b 0.60 0.90

e 1.27 BSC

A1

SIDE VIEW

SEATING
PLANE

A

MCM69F819
18

MOTOROLA FAST SRAM

4X

A–B0.20 (0.008) H

D

80 51

–D–

TQ PACKAGE

TQFP

CASE 983A–01

2X 30 TIPS

C D

A–B0.20 (0.008)

e

e/2

–A–

–H–
–C–

SEATING
PLANE

0.05 (0.002)

81

100

S

2X 20 TIPS

A

A2

A1

D1/2

C D

S

R1

VIEW AB

D1

D

D/2

50

E/2

–B–

E1

E

E1/2

31

301

B

B

VIEW Y

BASE

METAL

b1

c

b

0.13 (0.005) D

M

–X–

X=A, B, OR D

PLATING

c1

S

A–B

C

S

SECTION B–B

A–B0.20 (0.008)

q

2

q

3

0.10 (0.004)

VIEW AB

q

1

0.25 (0.010)

GAGE PLANE

R2

L2

L

q

L1

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DATUM PLANE –H– IS LOCATED AT BOTTOM OF
LEAD AND IS COINCIDENT WITH THE LEAD

C

WHERE THE LEAD EXITS THE PLASTIC BODY AT
THE BOTTOM OF THE PARTING LINE.

4. DATUMS –A–, –B– AND –D– TO BE DETERMINED
AT DATUM PLANE –H–.

5. DIMENSIONS D AND E TO BE DETERMINED AT
SEATING PLANE –C–.

6. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS 0.25
(0.010) PER SIDE. DIMENSIONS D1 AND B1 DO
INCLUDE MOLD MISMATCH AND ARE
DETERMINED AT DATUM PLANE –H–.

7. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. DAMBAR PROTRUSION SHALL
NOT CAUSE THE b DIMENSION TO EXCEED 0.45
(0.018).

_
_

_

INCHESMILLIMETERS

0.020 REF

_
_
_
_

_
_

_

DIM MIN MAX MIN MAX

A ––– 1.60 ––– 0.063
A1 0.05 0.15 0.002 0.006
A2 1.35 1.45 0.053 0.057

b 0.22 0.38 0.009 0.015

b1 0.22 0.33 0.009 0.013

c 0.09 0.20 0.004 0.008

c1 0.09 0.16 0.004 0.006

D 22.00 BSC 0.866 BSC
D1 20.00 BSC 0.787 BSC

E 16.00 BSC 0.630 BSC

E1 14.00 BSC 0.551 BSC

e 0.65 BSC 0.026 BSC

L 0.45 0.75 0.018 0.030

L1 1.00 REF 0.039 REF
L2 0.50 REF

S 0.20 ––– 0.008 –––
R1 0.08 ––– 0.003 –––
R2 0.08 0.20 0.003 0.008

q

0 7 0 7

_

q

0 ––– 0 –––

1

_

q

11 13 11 13

2

_

q

11 13 11 13

3

_

MOTOROLA FAST SRAM

MCM69F819

19

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty , representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. “T ypical” parameters which may be provided in Motorola
data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”
must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of
others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other
applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury
or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal
Opportunity/Affirmative Action Employer.

How to reach us:
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Mfax is a trademark of Motorola, Inc.

MCM69F819
20

◊

MOTOROLA FAST SRAM

MCM69F819/D