Datasheet MCM69F817ZP6R, MCM69F817ZP6.5R, MCM69F817ZP6, MCM69F817ZP7, MCM69F817ZP6.5 Datasheet (Motorola)

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MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

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by MCM69F817/D

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256K x 18 Bit Flow–Through BurstRAM Synchronous Fast Static RAM

MCM69F817

The MCM69F817 is a 4M bit synchronous fast static RAM designed to provide a burstable, high performance, secondary cache for the PowerPC and other high performance microprocessors. It is organized as 256K words of 18 bits each. This device integrates input registers, a 2–bit address counter, and high speed SRAM onto a single monolithic circuit for reduced parts count in cache data RAM applications. Synchronous design allows precise cycle control with the use of an external clock (K).

Addresses (SA), data inputs (DQx), and all control signals except output enable (G edge–triggered noninverting registers.

addresses can be generated internally by the MCM69F817 (burst sequence operates in linear or interleaved mode dependent upon the state of LBO controlled by the burst address advance (ADV) input pin.

clock (K) input. This feature eliminates complex off–chip write pulse generation and provides increased timing flexibility for incoming signals.

nous write enable (SW) are provided to allow writes to either individual bytes or to all bytes. The two bytes are designated as “a” and “b”. SBa SBb asserted with SW SW

from the memory array . operate on a 3.3 V or 2.5 V power supply . All inputs and outputs are JEDEC stan-

dard JESD8–5 compatible.

• MCM69F817 Speed Options

• 3.3 V + 10%, – 5% Core Power Supply , Operates with a 3.3 V or 2.5 V I/O

• ADSP

• Selectable Burst Sequencing Order (Linear/Interleaved)

• Single–Cycle Deselect Timing

• Internally Self–Timed Write Cycle

• Byte Write and Global Write Control

• PB1 Version 2.0 Compatible

• JEDEC Standard 119–Pin PBGA Package

BurstRAM is a trademark of Motorola, Inc. The PowerPC name is a trademark of IBM Corp., used under license therefrom.

This document contains information on a new product under development. Motorola reserves the right to change or discontinue this product without notice.

REV 1 6/26/97

) and linear burst order (LBO) are clock (K) controlled through positive–

Bursts can be initiated with either ADSP

Write cycles are internally self–timed and are initiated by the rising edge of the

Synchronous byte write (SBx

controls DQb. Individual bytes are written if the selected byte writes SBx are

. All bytes are written if either SGW is asserted or if all SBx and

are asserted.

For read cycles, a flow–through SRAM allows output data to simply flow freely

The MCM69F817 operates from a 3.3 V core power supply and all outputs

Speed t

150 MHz 6.7 ns 6 ns 0.5 ns 1 ns 375 mA 133 MHz 7.5 ns 6.5 ns 0.5 ns 1 ns 350 mA 117 MHz 8.5 ns 7 ns 0.5 ns 1 ns 325 mA

Supply

, ADSC, and ADV Burst Control Pins

KHKH

), synchronous global write (SGW), and synchro-

Flow–Through

or ADSC input pins. Subsequent burst

controls DQa and

KHQV

Setup Hold I

) and

ZP PACKAGE

PBGA

CASE 999–01

 Motorola, Inc. 1997

MOTOROLA FAST SRAM

MCM69F817

Page 2

LBO

ADV

K ADSC ADSP

SA SA1 SA0

FUNCTIONAL BLOCK DIAGRAM

ADDRESS

BURST

COUNTER

CLR

256K x 18

ARRAY

SGW

SBa

SBb

SE1 SE2

SE3

WRITE

ENABLE

DATA–IN

DQa – DQb

MCM69F817 2

MOTOROLA FAST SRAM

Page 3

PIN ASSIGNMENT

6543217

SA SA SA SA

DDQ

NC SE2 SA ADSC

C D E

F G

H J

K L M N P

R T U

SA SA SA SA

DQb NC

DQbNC

DDQ

DQb

DDQ NC DQb

NCDQb

DQb

DDQ

NCDQb

NC DQb

SA SA

SA SA SA SA

NC DDQ

ADSP

NC DQa

SBbDQbNC V

SGW

SA0

LBO

NCNC

SE3

NCSE1

DQa

NCADV DQa V

NC DQaSBa

NC DQaSA1

DDQ

NC NC NC

DQa

DDQ

DQa

DDQ

DQa

NC DDQ

DQa

NC NC

DDQ

TOP VIEW 119 BUMP PBGA

Not to Scale

MOTOROLA FAST SRAM

MCM69F817

Page 4

PBGA PIN DESCRIPTIONS

Pin Locations Symbol

4B ADSC Input Synchronous Address Status Controller: Active low, interrupts any

4A ADSP Input Synchronous Address Status Processor: Active low, interrupts any

4G ADV Input Synchronous Address Advance: Increments address count in

(a) 6D, 7E, 6F, 7G, 6H, 7K, 6L, 6N, 7P

(b) 1D, 2E, 2G, 1H, 2K, 1L, 2M, 1N, 2P

4F G Input Asynchronous Output Enable Input:

4K K Input Clock: This signal registers the address, data in, and all control signals

3R LBO Input Linear Burst Order Input: This pin must remain in steady state (this

2A, 3A, 5A, 6A, 3B, 5B, 2C, 3C,

5C, 6C, 2R, 6R, 2T, 3T, 5T, 6T

4N, 4P SA1, SA0 Input Synchronous Address Inputs: These pins must be wired to the two

5L, 3G (a) (b)

4E SE1 Input Synchronous Chip Enable: Active low to enable chip.

2B SE2 Input Synchronous Chip Enable: Active high for depth expansion. 6B SE3 Input Synchronous Chip Enable: Active low for depth expansion. 4H SGW Input Synchronous Global Write: This signal writes all bytes regardless of the

4M SW Input Synchronous Write: This signal writes only those bytes that have been

4C, 2J, 4J, 6J, 4R V

1A, 7A, 1F, 7F, 1J, 7J, 1M, 7M, 1U, 7U V

3D, 5D, 3E, 5E, 3F, 5F, 5G, 3H, 5H, 3K, 5K, 3L, 3M, 5M, 3N, 5N, 3P, 5P

1B, 7B, 1C, 7C, 2D, 4D, 7D, 1E, 6E,

2F, 1G, 6G, 2H, 7H, 3J, 5J, 1K, 6K, 2L, 4L, 7L, 6M, 2N, 7N, 1P, 6P, 1R,

5R, 7R, 1T, 4T, 7T, 2U, 3U, 4U, 5U, 6U

Type Description

ongoing burst and latches a new external address. Used to initiate a READ, WRITE, or chip deselect.

ongoing burst and latches a new external address used to initiate a new READ or chip deselect (exception — chip deselect does not occur when ADSP

accordance with counter type selected (linear/interleaved).

DQx I/O Synchronous Data I/O: “x” refers to the byte being read or written

SA Input Synchronous Address Inputs: These inputs are registered and must

SBx Input Synchronous Byte Write Inputs: “x” refers to the byte being written (byte

DDQ

NC — No Connection: There is no connection to the chip.

Supply Core Power Supply. Supply I/O Power Supply. Supply Ground.

(byte a, b).

Low — enables output buffers (DQx pins). High — DQx pins are high impedance.

except G

signal not registered or latched). It must be tied high or low. Low — linear burst counter (68K/PowerPC). High — interleaved burst counter (486/i960/Pentium).

meet setup and hold times.

LSBs of the address bus for proper burst operation. These inputs are registered and must meet setup and hold times.

a, b). SGW

Negated high — blocks ADSP asserted.

status of the SBx being used, tie this pin high.

selected using the byte write SBx are being used, tie this pin low.

is asserted and SE1 is high).

and LBO.

overrides SBx.

or deselects chip when ADSC is

and SW signals. If only byte write signals SBx are

pins. If only byte write signals SBx

MCM69F817 4

MOTOROLA FAST SRAM

Page 5

TRUTH TABLE (See Notes 1 Through 5)

Address

Next Cycle

Deselect None 1 X X X 0 X X High–Z X Deselect None 0 X 1 0 X X X High–Z X Deselect None 0 0 X 0 X X X High–Z X Deselect None X X 1 1 0 X X High–Z X Deselect None X 0 X 1 0 X X High–Z X Begin Read External 0 1 0 0 X X X High–Z X Begin Read External 0 1 0 1 0 X X High–Z READ Continue Read Next X X X 1 1 0 1 High–Z READ Continue Read Next X X X 1 1 0 0 DQ READ Continue Read Next 1 X X X 1 0 1 High–Z READ Continue Read Next 1 X X X 1 0 0 DQ READ Suspend Read Current X X X 1 1 1 1 High–Z READ Suspend Read Current X X X 1 1 1 0 DQ READ Suspend Read Current 1 X X X 1 1 1 High–Z READ Suspend Read Current 1 X X X 1 1 0 DQ READ Begin Write External 0 1 0 1 0 X X High–Z WRITE Continue Write Next X X X 1 1 0 X High–Z WRITE Continue Write Next 1 X X X 1 0 X High–Z WRITE Suspend Write Current X X X 1 1 1 X High–Z WRITE Suspend Write Current 1 X X X 1 1 X High–Z WRITE

NOTES:

1. X = don’t care. 1 = logic high. 0 = logic low.

2. Write is defined as either (a) any SBx

3. G

is an asynchronous signal and is not sampled by the clock K. G drives the bus immediately (t

4. On write cycles that follow read cycles, G also remain negated at the completion of the write cycle to ensure proper write data hold times.

5. This read assumes the RAM was previously deselected.

Used

SE1 SE2 SE3 ADSP ADSC ADV G

and SW low or (b) SGW is low.

must be negated prior to the start of the write cycle to ensure proper write data setup times. G must

GLQX

DQx Write 2,

) following G going low.

LINEAR BURST ADDRESS TABLE (LBO = V

1st Address (External)

X . . . X00 X . . . X01 X . . . X10 X . . . X11 X . . . X01 X . . . X10 X . . . X11 X . . . X00 X . . . X10 X . . . X11 X . . . X00 X . . . X01 X . . . X11 X . . . X00 X . . . X01 X . . . X10

2nd Address (Internal) 3rd Address (Internal) 4th Address (Internal)

INTERLEAVED BURST ADDRESS TABLE (LBO = V

1st Address (External) 2nd Address (Internal) 3rd Address (Internal) 4th Address (Internal)

X . . . X00 X . . . X01 X . . . X10 X . . . X11 X . . . X01 X . . . X00 X . . . X11 X . . . X10 X . . . X10 X . . . X11 X . . . X00 X . . . X01 X . . . X11 X . . . X10 X . . . X01 X . . . X00

)

WRITE TRUTH TABLE

Cycle Type SGW SW SBa SBb

Read H H X X Read H L H H Write Byte a H L L H Write Byte b H L H L Write All Bytes H L L L Write All Bytes L X X X

MOTOROLA FAST SRAM

MCM69F817

Page 6

ABSOLUTE MAXIMUM RATINGS (See Note 1)

Rating Symbol Value Unit

Power Supply Voltage V I/O Supply Voltage (See Note 2) V Input Voltage Relative to VSS for Any

Pin Except VDD (See Note 2) Input Voltage (Three–State I/O)

(See Note 2) Output Current (per I/O) I Package Power Dissipation (See Note 3) P Temperature Under Bias T Storage Temperature T

NOTES:

1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability.

2. This is a steady–state DC parameter that is in effect after the power supply has achieved its nominal operating level. Power sequencing can not be controlled and is not allowed.

3. Power dissipation capability is dependent upon package characteristics and use environment. See Package Thermal Characteristics.

DDQ

Vin, V

out

bias

stg

VSS – 0.5 to + 4.6 V

VSS – 0.5 to V

out

VSS – 0.5 to

VDD + 0.5

VSS – 0.5 to

DDQ

– 10 to 85 °C

– 55 to 125 °C

+ 0.5

± 20 mA

1.6 W

V V

This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high–impedance circuit.

PACKAGE THERMAL CHARACTERISTICS — PBGA

Rating Symbol Max Unit Notes

Junction to Ambient (@ 200 lfm) Single Layer Board

Four Layer Board Junction to Board (Bottom) R Junction to Case (Top) R

NOTES:

1. Junction temperature is a function of on–chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, board population, and board thermal resistance.

2. Per SEMI G38–87.

3. Indicates the average thermal resistance between the die and the printed circuit board.

4. Indicates the average thermal resistance between the die and the case top surface via the cold plate method (MIL SPEC–883 Method 1012.1).

θJA

θJB θJC

41 19

11 °C/W 3 19 °C/W 4

°C/W 1, 2

MCM69F817 6

MOTOROLA FAST SRAM

Page 7

DC OPERA TING CONDITIONS AND CHARACTERISTICS

(3.6 V ≥ VDD ≥ 3.135 V, 70°C ≥ TA ≥ 0°C, Unless Otherwise Noted)

RECOMMENDED OPERATING CONDITIONS

Parameter Symbol Min Typ Max Unit

Supply Voltage V I/O Supply Voltage V Ambient Temperature T Input Low Voltage V Input High Voltage V Input High Voltage I/O Pins V

(Voltages Referenced to VSS = 0 V)

DDQ

A IL IH

IH2

3.135 3.3 3.6 V

2.375 3.3 V 0 — 70 °C

– 0.3 — 0.8 V

2.0 — VDD + 0.3 V

2.0 — V

DDQ

+ 0.3 V

VSS – 1.0 V

20% t

KHKH

(MIN)

Figure 1. Undershoot Voltage

DC CHARACTERISTICS AND SUPPLY CURRENTS

Parameter Symbol Min Typ Max Unit Notes

Input Leakage Current (0 V ≤ Vin ≤ VDD) I Output Leakage Current (0 V ≤ Vin ≤ V AC Supply Current (Device Selected, MCM69F817–6

All Outputs Open, Freq = Max) MCM69F817–6.5 Includes VDD and V

CMOS Standby Supply Current (Device Deselected, Freq = 0, VDD = Max, All Inputs Static at CMOS Levels Vin ≤ VSS + 0.2 V or ≥ VDD – 0.2 V)

TTL Standby Supply Current (Device Deselected, Freq = 0, VDD = Max, All Inputs Static at Vin ≤ VIL or ≥ VIH)

Clock Running (Device Deselected, MCM69F817–6 Freq = Max, VDD = Max, All Inputs Toggling at CMOS Levels Vin ≤ VSS + 0.2 V or ≥ VDD – 0.2 V)

Static Clock Running (Device Deselected, MCM69F817–6 Freq = Max, VDD = Max, All Inputs Static at Vin ≤ VIL or ≥ VIH)

Output Low Voltage (IOL = 2 mA) V Output High Voltage (IOH = – 2 mA) V Output Low Voltage (IOL = 8 mA) V Output High Voltage (IOH = – 4 mA) V

NOTES:

1. LBO

pin has an internal pullup and will exhibit leakage currents of ± 5 µA.

2. Reference AC Operating Conditions and Characteristics for input and timing (VIH/VIL, tr/tf, pulse level 0 to 3.0 V).

3. All addresses transition simultaneously low (LSB) and then high (MSB).

4. Data states are all zero.

5. Device in Deselected mode as defined by the Truth Table.

DDQ

) I

DDQ

MCM69F817–7

= 2.5 V V

DDQ

= 2.5 V V

DDQ

= 3.3 V V

DDQ

= 3.3 V V

DDQ

lkg(I)

lkg(O) I

DDA

SB2

SB3

SB4

SB5

OL1

OH1

OL2

OH2

— — ± 1 µA 1 — — ± 1 µA — — 375

— — TBD mA 5

— — 0.7 V

1.7 — — V — — 0.4 V

2.4 — — V

350

mA 2, 3, 4

325

CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, 70°C ≥ T

Parameter Symbol Min Typ Max Unit

Input Capacitance C Input/Output Capacitance C

≥ 0°C, Periodically Sampled Rather Than 100% Tested)

MOTOROLA FAST SRAM

I/O

— 4 5 pF — 7 8 pF

MCM69F817

Page 8

AC OPERA TING CONDITIONS AND CHARACTERISTICS

(3.6 V ≥ VDD ≥ 3.135 V, 70°C ≥ TA ≥ 0°C, Unless Otherwise Noted)

Input Timing Measurement Reference Level 1.5 V. . . . . . . . . . . . . . .

Input Pulse Levels 0 to 3.0 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input Slew Rate (See Note 1) 1.0 V/ns. . . . . . . . . . . . . . . . . . . . . . . . .

READ/WRITE CYCLE TIMING (See Notes 1 and 2)

Parameter Symbol

Cycle Time t Clock High Pulse Width t Clock Low Pulse Width t Clock Access Time t Output Enable to Output Valid t Clock High to Output Active t Clock High to Output Change t Output Enable to Output Active t Output Disable to Q High–Z t Clock High to Q High–Z t Setup Times: Address

ADSP

Hold Times: Address

NOTES:

1. Write is defined as either any SBx or ADSC is asserted.

2. All read and write cycle timings are referenced from K or G

3. Tested per AC Test Load, Figure 2.

4. Measured at

5. This parameter is sampled and not 100% tested.

± 200 mV from steady state.

ADSP

Data In

Write

Chip Enable

, ADSC, ADV

Data In

Write

Chip Enable

and SW low or SGW is low. Chip Enable is defined as SE1 low , SE2 high, and SE3 low whenever ADSP

KHKH KHKL KLKH

KHQV

GLQV KHQX1 KHQX2

GLQX

GHQZ

KHQZ t

ADKH t

DVKH

WVKH

EVKH

ADSKH t

KHAX

KHADSX

KHDX

KHWX

KHEX

Output Timing Reference Level 1.5 V. . . . . . . . . . . . . . . . . . . . . . . . . .

Output Load See Figure 2 Unless Otherwise Noted. . . . . . . . . . . . . .

Output Rise/Fall Times (Max) 2.0 ns. . . . . . . . . . . . . . . . . . . . . . . . . . .

MCM69F817–6

150 MHz

Min Max Min Max Min Max

6.7 — 7.5 — 8.5 — ns

2.5 — 2.5 — 3 — ns

2.5 — 2.5 — 3 — ns — 6 — 6.5 — 7 ns 3 — 3.5 — 3.5 — 3.5 ns 3

0 — 0 — 0 — ns 3, 4, 5 2 — 2 — 2 — ns 3, 5 0 — 0 — 0 — ns 3, 4, 5

— 3.5 — 3.5 — 3.5 ns 3, 4, 5

1 3.5 1 3.5 1 3.5 ns 3, 4, 5

0.5

1.5

1.0 — 1.0 — 1.0 — ns

MCM69F817–6.5

— 0.5

0.5

1.5

133 MHz

MCM69F817–7

— 0.5

0.5

1.5

117 MHz

Unit Notes

— ns

MCM69F817 8

MOTOROLA FAST SRAM

Page 9

OUTPUT

Z0 = 50

Ω

1.5 V

Figure 2. AC Test Load

OUTPUT LOAD

RL = 50

Ω

OUTPUT BUFFER

UNLOADED RISE AND FALL TIME MEASUREMENT

INPUT

WAVEFORM

OUTPUT

WAVEFORM

NOTES:

1. Input waveform has a slew rate of 1 V/ns.

2. Rise time is measured from 0.4 to 2.4 V unloaded.

3. Fall time is measured from 2.4 to 0.4 V unloaded.

2.4 2.4

0.4 0.4

2.4

0.4 0.4

Figure 3. Unloaded Rise and Fall Time Characterization

TEST POINT

2.4

MOTOROLA FAST SRAM

MCM69F817

Page 10

VOLTAGE (V)

– 0.5

1.4

1.65

2.0

3.135

3.6

VOLTAGE (V)

– 0.5

0.8

1.25

1.5

2.3

2.7

2.9

PULL–UP

I (mA) MIN I (mA) MAX

– 40 – 40 – 40 – 37

– 28

0 0

– 120 – 120 – 120 – 104

– 81 – 20

(a) Pull–Up for 3.3 V I/O Supply

PULL–UP

I (mA) MIN I (mA) MAX

– 26 – 26 – 26 – 18

– 14

0 0 0

– 75 – 75 – 75 – 58

– 49 – 21

– 7

(b) Pull–Up for 2.5 V I/O Supply

3.6

3.135

2.8

1.65

VOLTAGE (V)

1.4

0– 40

CURRENT (mA)

2.9

2.5

2.3

2.1

1.25

VOLTAGE (V)

0.8

0 – 26 – 75

CURRENT (mA)

– 120

VOLTAGE (V)

MCM69F817 10

– 0.5

0.5 1

1.65

1.8

3.6 4

PULL–DOWN

I (mA) MIN I (mA) MAX

– 34

17 35

45 46 46 46

– 126

90 114 120

120 120

Figure 4. T ypical Output Buffer Characteristics

1.8

1.65

VOLTAGE (V)

0.3

0 46 120

CURRENT (mA)

MOTOROLA FAST SRAM

Page 11

READ/WRITE CYCLES

GLQV

Q(B) D(C) D(C+1) D(C+2) D(C+3) Q(D)

GLQX

SE2, SE3

ADSP, SA

GHQZ

BURST WRITE

IGNORED

KLKH

KHKL

KHKH

Q(B+2) Q(B+3)

BURST WRAPS AROUND

KHQX2

Q(B) Q(B+1)

KHQV

ADSP

ADSC

ADV

SE1

Q(A)Q(n)

DQx

KHQX1

KHQZ

BURST READSINGLE READ

DESELECTED SINGLE READ

W low = SGW low and/or SW and SBx low.

NOTE: E low = SE2 high and SE3 low.

MOTOROLA FAST SRAM

MCM69F817

Page 12

APPLICATION INFORMATION

STOP CLOCK OPERATION

In the stop clock mode of operation, the SRAM will hold all state and data values even though the clock is not running (full static operation). The SRAM design allows the clock to start with ADSP

and ADSC, and stops the clock after the last

write data is latched, or the last read data is driven out.

When starting and stopping the clock, the AC clock timing and parametrics must be strictly maintained. For example, clock pulse width and edge rates must be guaranteed when

STOP CLOCK WITH READ TIMING

ADSP

ADDRESS

A1 A2

starting and stopping the clocks.

To achieve the lowest power operation for all three stop

clock modes, stop read, stop write, and stop deselect:

• Force the clock to a low state.

• Force the control signals to an inactive state (this guaran-

tees any potential source of noise on the clock input will not start an unplanned on activity).

• Force the address inputs to a low state (VIL), preferably < 0.2 V.

ADV

DQx

ADSP

(INITIATES

BURST READ)

NOTE: For lowest possible power consumption during stop clock, the addresses should be driven to a low state (VIL).

Best results are obtained if VIL < 0.2 V.

CLOCK STOP

(CONTINUE

BURST READ)

WAKE UP ADSP

(INITIATES BURST READ)

Q(A2) Q(A2+1)Q(A1)

MCM69F817 12

MOTOROLA FAST SRAM

Page 13

ADSC

STOP CLOCK WITH WRITE TIMING

ADDRESS

WRITE

ADV

DQx

NOTE: While the clock is stopped, DATA IN must be fixed in a high (VIH) or low (VIL) state to reduce the DC current of the

input buffers. For lowest power operation, all data and address lines should be held in a low (VIL) state and control lines held in an inactive state.

A1 A2

D(A1)DATA IN D(A1+1) D(A2)

ADSC

(INITIATES

BURST WRITE)

CLOCK STOP

(CONTINUE

BURST WRITE)

VIH OR VIL FIXED (SEE NOTE)

HIGH–Z

WAKE UP ADSC

(INITIATES BURST WRITE)

MOTOROLA FAST SRAM

MCM69F817

Page 14

ADSC

SE1

STOP CLOCK WITH DESELECT OPERATION TIMING

DATA IN

DQx

NOTE: While the clock is stopped, DAT A IN must be fixed in a high (VIH) or low (VIL) state to reduce the DC current of the

DATA DATA

CONTINUE

BURST READ

input buffers. For lowest power operation, all data and address lines should be held in a low (VIL) state and control lines held in an inactive state.

CLOCK STOP

(DESELECTED)

VIH OR VIL FIXED (SEE NOTE)

HIGH–Z

WAKE UP

(DESELECTED)

MCM69F817 14

MOTOROLA FAST SRAM

Page 15

NON–BURST SYNCHRONOUS OPERATION

Although this BurstRAM has been designed for PowerPC– based and other high end MPU–based systems, these SRAMs can be used in other high speed L2 cache or memory applications that do not require the burst address feature. Most L2 caches designed with a synchronous interface can make use of the MCM69F817. The burst counter feature of the BurstRAM can be disabled, and the SRAM can be configured to act upon a continuous stream of addresses. See Figure 5.

CONTROL PIN TIE VALUES

Non–Burst ADSP ADSC ADV SE1 LBO

Sync Non–Burst, Flow–Through SRAM

NOTE: Although X is specified in the table as a don’t care, the pin

must be tied either high or low.

(H ≥ VIH, L ≤ VIL)

H L H L X

ADDR

Motorola Memory Prefix

CD EFGH

Q(B)Q(A)

Q(D)Q(C) D(E)

D(F) D(G) D(H)

WRITESREADS

Figure 5. Configured as Non–Burst Synchronous SRAM

ORDERING INFORMATION

(Order by Full Part Number)

MCM 69F817 XX X X

Blank = Trays, R = Tape and Reel

Part Number

Full Part Numbers — MCM69F817ZP6 MCM69F817ZP6.5 MCM69F817ZP7

MOTOROLA FAST SRAM

Speed (6 = 6.0 ns, 6.5 = 6.5 ns, 7 = 7.0 ns) Package (ZP = PBGA)

MCM69F817ZP6R MCM69F817ZP6.5R MCM69F817ZP7R

MCM69F817

Page 16

PIN 1A IDENTIFIER

–W–

TOP VIEW

0.20 (0.008)

–L–

P ACKAGE DIMENSIONS

ZP PACKAGE

7 x 17 BUMP PBGA

CASE 999–01

7654321

16X

6X G

BOTTOM VIEW

A B C D E F G H

J K L M N P R T U

119X

NOTES:

0.10 (0.004)ST

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

MILLIMETERS

DIMAMIN MAX MIN MAX

14.00 BSC 0.551 BSC

B 22.00 BSC 0.866 BSC C ––– 2.40 ––– 0.094 D 0.60 0.90 0.024 0.035 E 0.50 0.70 0.020 0.028 F 1.30 1.70 0.051 0.067 G 1.27 BSC 0.050 BSC K 0.80 1.00 0.031 0.039 N 11.90 12.10 0.469 0.476 P 19.40 19.60 0.764 0.772 R 7.62 BSC 0.300 BSC S 20.32 BSC 0.800 BSC

L0.30 (0.012)STW

INCHES

0.35 (0.014) T

0.25 (0.010) T

0.15 (0.006) T

–T–

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MOTOROLA FAST SRAM

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