Datasheet MCM69F618CTQ10R, MCM69F618CTQ12, MCM69F618CTQ8.5R, MCM69F618CTQ9, MCM69F618CTQ10 Datasheet (Motorola)

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

64K x 18 Bit Flow–Through
BurstRAM Synchronous
Fast Static RAM

Order this document

by MCM69F618C/D

MCM69F618C

The MCM69F618C is a 1M–bit synchronous fast static RAM designed to pro­vide a burstable, high performance, secondary cache for the 68K Family,
PowerPC, 486, i960, and Pentium microprocessors. It is organized as 64K
words of 18 bits each. This device integrates input registers, a 2–bit address
counter, and high speed SRAM onto a single monolithic circuit for reduced parts
count in cache data RAM applications. Synchronous design allows precise cycle
control with the use of an external clock (K). BiCMOS circuitry reduces the overall
power consumption of the integrated functions for greater reliability .

Addresses (SA), data inputs (DQx), and all control signals except output
enable (G
positive–edge–triggered noninverting registers.

Bursts can be initiated with either ADSP
addresses can be generated internally by the MCM69F618C (burst sequence
operates in linear or interleaved mode dependent upon the state of LBO
controlled by the burst address advance (ADV

Write cycles are internally self–timed and initiated by the rising edge of the
clock (K) input. This feature eliminates complex off–chip write pulse generation
and provides increased timing flexibility for incoming signals.

Synchronous byte write (SBx
chronous write enable SW
or to both bytes. The two bytes are designated as “a” and “b”. SBa
and SBb
are asserted with SW. Both bytes are written if either SGW is asserted or if all SBx
and SW are asserted.

For read cycles, a flow–through SRAM allows output data to simply flow freely
from the memory array .

The MCM69F618C operates from a 3.3 V power supply and all inputs and
outputs are L VTTL compatible and 5 V tolerant.

• MCM69F618C–8.5 = 8.5 ns Access / 12 ns Cycle

• Single 3.3 V + 10%, – 5% Power Supply

• ADSP

• Selectable Burst Sequencing Order (Linear/Interleaved)

• Internally Self–Timed Write Cycle

• Byte Write and Global Write Control

• 5 V Tolerant on all Pins (Inputs and I/Os)

• 100–Pin TQFP Package

) and Linear Burst Order (LBO) are clock (K) controlled through

or ADSC input pins. Subsequent burst

) and

) input pin.

), synchronous global write (SGW), and syn-

are provided to allow writes to either individual bytes

controls DQa

controls DQb. Individual bytes are written if the selected byte writes SBx

MCM69F618C–9 = 9 ns Access / 12 ns Cycle
MCM69F618C–10 = 10 ns Access / 15 ns Cycle
MCM69F618C–12= 12 ns Access / 16.6 ns Cycle

, ADSC, and ADV Burst Control Pins

TQ PACKAGE

TQFP

CASE 983A–01

The PowerPC name is a trademark of IBM Corp., used under license therefrom.
i960 and Pentium are trademarks of Intel Corp.

REV 2
2/18/98

 Motorola, Inc. 1998

MOTOROLA FAST SRAM

MCM69F618C

1

LBO
ADV

K
ADSC
ADSP

FUNCTIONAL BLOCK DIAGRAM

FUNCTIONAL BLOCK DIAGRAM

K2

BURST

COUNTER

CLR

2

16

64K x 18 ARRAY

SA
SA1
SA0

SGW

SW

SBa

SBb

SE1
SE2
SE3

G

ADDRESS

REGISTER

WRITE

REGISTER

a

WRITE

REGISTER

b

K2

ENABLE

REGISTER

16

2

14

18 18

2

DATA–IN

REGISTER

K

DQa, DQb

MCM69F618C
2

MOTOROLA FAST SRAM

PIN ASSIGNMENT

NC
NC
NC

V

DD

V

SS

NC

NC
DQb
DQb

V

SS

V

DD

DQb
DQb

NC
V

DD

NC

V

SS

DQb
DQb
V

DD
V

SS

DQb
DQb
DQb

NC
V

SS

V

DD

NC

NC

NC

SASASE1

1
2
3
4
5
6
7
8
9
10
11
12
13

14
15

16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

31 32 33

SE2

NC

NC

SBb

94 9397 96 95 89 8892 91 90 86 8587100 99 98 81828384

37 3834 35 36 42 4339 40 41 45 4644

SBa

SE3

DD

VSSV

K

SGW

ADSC

ADV

SA

SA

80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

50494847

SA
NC
NC
V

DD

V

SS
NC
DQa

DQa
DQa
V

SS
V

DD
DQa

DQa
V

SS

NC

V

DD

NC

DQa
DQa
V

DD

V

SS

DQa
DQa
NC
NC

V

SS

V

DD
NC
NC
NC

ADSP

G

SW

SASASA

LBO

SA

SA1

SA0

SS

NCNCNC

DD

V

V

NC

SA

SASASA

SA

NC

NC

MOTOROLA FAST SRAM

MCM69F618C

3

PIN DESCRIPTIONS

Pin Locations Symbol

85 ADSC Input Synchronous Address Status Controller: Initiates READ, WRITE or chip

84 ADSP Input Synchronous Address Status Processor: Initiates READ, WRITE or

83 ADV Input Synchronous Address Advance: Increments address count in

(a) 58, 59, 62, 63, 68, 69, 72, 73, 74

(b) 8, 9, 12, 13, 18, 19, 22, 23, 24

86 G Input Asynchronous Output Enable Input:

89 K Input Clock: This signal registers the address, data in, and all control signals

31 LBO Input Linear Burst Order Input: This pin must remain in steady state (this

32, 33, 34, 35, 44, 45, 46,
47, 48, 80, 81, 82, 99, 100

36, 37 SA1,SA0 Input Synchronous Address Inputs: these pins must be wired to the two LSBs

93, 94

(a) (b)

98 SE1 Input Synchronous Chip Enable: Active low to enable chip.

97 SE2 Input Synchronous Chip Enable: Active high for depth expansion.
92 SE3 Input Synchronous Chip Enable: Active low for depth expansion.
88 SGW Input Synchronous Global Write: This signal writes all bytes regardless of the

87 SW Input Synchronous Write: This signal writes only those bytes that have been

4, 11, 15, 20, 27, 41, 54,

61, 65, 70, 77, 91

5, 10, 17, 21, 26, 40, 55,

60, 67, 71, 76, 90

64 NC Input No Connection: There is no connection to the chip. For compatibility

1, 2, 3, 6, 7, 14, 16, 25, 28, 29, 30,

38, 39, 42, 43, 49, 50, 51, 52,

53, 56, 57, 66, 75, 78, 79, 95, 96

Type Description

deselect cycle.

chip deselect cycle (exception — chip deselect does not occur when
ADSP

is asserted and SE1 is high).

accordance with counter type selected (linear/interleaved).

DQx I/O Synchronous Data I/O: “x” refers to the byte being read or written

SA Input Synchronous Address Inputs: These inputs are registered and must

SBx Input Synchronous Byte Write Inputs: “x” refers to the byte being written (byte

V

DD

V

SS

NC — No Connection: There is no connection to the chip.

Supply Power Supply: 3.3 V + 10%, – 5%.

Supply Ground.

(byte a, b).

Low — enables output buffers (DQx pins).
High — DQx pins are high impedance.

except G

signal not registered or latched). It must be tied high or low.
Low — linear burst counter (68K/PowerPC).
High — interleaved burst counter (486/i960/Pentium).

meet setup and hold times.

of the address bus for proper burst operation. These inputs are
registered and must meet setup and hold times.

a, b). SGW

Negated high–blocks ADSP

status of the SBx
being used, tie this pin high.

selected using the byte write SBx
are being used, tie this pin low.

reasons, it is recommended that this pin be tied low for system designs
that do not have a sleep mode associated with the cache/memory
controller. Other vendors’ RAMs may have implemented this Sleep
Mode (ZZ) feature.

and LBO.

overrides SBx.

or deselects chip when ADSC is asserted.

and SW signals. If only byte write signals SBx are

pins. If only byte write signals SBx

MCM69F618C
4

MOTOROLA FAST SRAM

TRUTH TABLE (See Notes 1 through 4)

Address

Next Cycle

Deselect None 1 X X X 0 X X High–Z X
Deselect None 0 X 1 0 X X X High–Z X
Deselect None 0 0 X 0 X X X High–Z X
Deselect None X X 1 1 0 X X High–Z X
Deselect None X 0 X 1 0 X X High–Z X
Begin Read External 0 1 0 0 X X 0 DQ READ
Begin Read External 0 1 0 1 0 X 0 DQ READ
Continue Read Next X X X 1 1 0 1 High–Z READ
Continue Read Next X X X 1 1 0 0 DQ READ
Continue Read Next 1 X X X 1 0 1 High–Z READ
Continue Read Next 1 X X X 1 0 0 DQ READ
Suspend Read Current X X X 1 1 1 1 High–Z READ
Suspend Read Current X X X 1 1 1 0 DQ READ
Suspend Read Current 1 X X X 1 1 1 High–Z READ
Suspend Read Current 1 X X X 1 1 0 DQ READ
Begin Write Current X X X 1 1 1 X High–Z WRITE
Begin Write Current 1 X X X 1 1 X High–Z WRITE
Begin Write External 0 1 0 1 0 X X High–Z WRITE
Continue Write Next X X X 1 1 0 X High–Z WRITE
Continue Write Next 1 X X X 1 0 X High–Z WRITE
Suspend Write Current X X X 1 1 1 X High–Z WRITE
Suspend Write Current 1 X X X 1 1 X High–Z WRITE

NOTES:

1. X = Don’t Care. 1 = logic high. 0 = logic low.

2. Write is defined as either 1) any SBx

3. G

is an asynchronous signal and is not sampled by the clock K. G drives the bus immediately (t

4. On write cycles that follow read cycles, G
also remain negated at the completion of the write cycle to ensure proper write data hold times.

Used

SE1 SE2 SE3 ADSP ADSC ADV G

and SW low or 2) SGW is low.

must be negated prior to the start of the write cycle to ensure proper write data setup times. G must

3

DQx Write 2,

) following G going low.

GLQX

4

LINEAR BURST ADDRESS TABLE (LBO = V

1st Address (External ) 2nd Address (Internal ) 3rd Address (Internal ) 4th Address (Internal )

X . . . X00 X . . . X01 X . . . X10 X . . . X11
X . . . X01 X . . . X10 X . . . X11 X . . . X00
X . . . X10 X . . . X11 X . . . X00 X . . . X01
X . . . X11 X . . . X00 X . . . X01 X . . . X10

INTERLEAVED BURST ADDRESS TABLE (LBO = V

1st Address (External ) 2nd Address (Internal ) 3rd Address (Internal ) 4th Address (Internal )

X . . . X00 X . . . X01 X . . . X10 X . . . X11
X . . . X01 X . . . X00 X . . . X11 X . . . X10
X . . . X10 X . . . X11 X . . . X00 X . . . X01
X . . . X11 X . . . X10 X . . . X01 X . . . X00

SS

)

)

DD

WRITE TRUTH TABLE

Cycle Type SGW SW SBa SBb

Read H H X X
Read H L H H
Write Byte a H L L H
Write Byte b H L H L
Write All Bytes H L L L
Write All Bytes L X X X

MOTOROLA FAST SRAM

MCM69F618C

5

ABSOLUTE MAXIMUM RATINGS (See Note 1)

Rating Symbol Value Unit

Power Supply Voltage V
Voltage Relative to VSS for Any

Pin Except V
Output Current (per I/O) I
Package Power Dissipation (See Note 2) P
Temperature Under Bias T
Storage Temperature T

NOTES:

1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are

2. Power dissipation capability is dependent upon package characteristics and use

DD

exceeded. Functional operation should be restricted to RECOMMENDED OPER–
ATING CONDITIONS. Exposure to higher than recommended voltages for extended
periods of time could affect device reliability.

environment. See Package Thermal Characteristics.

Vin, V

out

bias

DD

out

D

stg

– 0.5 to + 4.6 V

– 0.5 to 6.0 V

± 20 mA

1.6 W

– 10 to 85 °C

– 55 to 125 °C

This device contains circuitry to protect the
inputs against damage due to high static volt­ages or electric fields; however, it is advised
that normal precautions be taken to avoid
application of any voltage higher than maxi­mum rated voltages to this high–impedance
circuit.

PACKAGE THERMAL CHARACTERISTICS

Rating Symbol Max Unit Notes

Thermal Resistance Junction to Ambient (@ 200 lfm) Single–Layer Board

Four–Layer Board

Thermal Resistance Junction to Board (Bottom) R
Thermal Resistance Junction to Case (Top) R

NOTES:

1. Junction temperature is a function of on–chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient
temperature, air flow, board population, and board thermal resistance.

2. Per SEMI G38–87.

3. Indicates the average thermal resistance between the die and the printed circuit board.

4. Indicates the average thermal resistance between the die and the case top surface via the cold plate method (MIL SPEC–883 Method

1012.1).

R

θJA

θJB
θJC

40
25

17 °C/W 1, 3

9 °C/W 1, 4

°C/W 1, 2

MCM69F618C
6

MOTOROLA FAST SRAM

DC OPERA TING CONDITIONS AND CHARACTERISTICS

(VDD = 3.3 V + 10%, – 5%, TA = 0 to 70°C, Unless Otherwise Noted)

RECOMMENDED OPERATING CONDITIONS

Parameter

Supply Voltage V
Input Low Voltage V
Input High Voltage V

*VIL ≥ – 2 V for t ≤ t

**VIH ≤ 6 V for t ≤ t

KHKH

KHKH

/2.

/2.

(Voltages Referenced to VSS = 0 V)

Symbol Min Typ Max Unit

DD

DC CHARACTERISTICS AND SUPPLY CURRENTS

Parameter Symbol Min Max Unit Notes

Input Leakage Current (0 V ≤ Vin ≤ VDD) (Excluding LBO) I
Output Leakage Current (0 V ≤ Vin ≤ VDD) I
AC Supply Current (Device Selected, MCM69F618C–8.5

All Outputs Open, MCM69F618C–9
All Inputs Toggling at Vin ≤ VIL or ≥ VIH, MCM69F618C–10
Cycle Time ≥ t

CMOS Standby Supply Current (Deselected, MCM69F618C–8.5
Clock (K

) Cycle Time ≥ t

All Inputs Toggling at CMOS Levels MCM69F618C–10
Vin ≤ VSS + 0.2 V or ≥ VDD – 0.2 V) MCM69F618C–12

Clock Running Supply Current (Deselected, MCM69F618C–8.5
Clock (K) Cycle Time ≥ t
All Other Inputs Held to Static CMOS Levels MCM69F618C–10
Vin ≤ VSS + 0.2 V or ≥ VDD – 0.2 V)) MCM69F618C–12

Output Low Voltage (IOL = 8 mA) V
Output High Voltage (IOH = – 4 mA) V

NOTES:

1. Reference AC Operating Conditions and Characteristics for input and timing.

2. All addresses transition simultaneously low (LSB) and then high (MSB).

3. Data states are all zero.

4. Device in Deselected mode as defined by the Truth Table.

min) MCM69F618C–12

KHKH

, MCM69F618C–9

KHKH

, MCM69F618C–9

KHKH

IL

IH

lkg(I)

lkg(O)
I

DDA

I

SB1

I

SB2

OL

OH

3.135 3.3 3.6 V

– 0.5* — 0.8 V

2.0 — 5.5** V

— ± 1 µA
— ± 1 µA
— 225

225
215
210

— 110

110
100

95

— 40

40
35
35

— 0.4 V

2.4 — V

mA 1, 2, 3

mA 4

mA 4

CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, T

Parameter Symbol Min Typ Max Unit

Input Capacitance C
Input/Output Capacitance C

= 25°C, Periodically Sampled Rather Than 100% Tested)

A

MOTOROLA FAST SRAM

in

I/O

— 4 6 pF
— 7 9 pF

MCM69F618C

7

AC OPERA TING CONDITIONS AND CHARACTERISTICS

(VDD = 3.3 V + 10%, – 5%, TA = 0 to 70°C, Unless Otherwise Noted)

Input Timing Measurement Reference Level 1.5 V. . . . . . . . . . . . . . .

Input Pulse Levels 0 to 3.0 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input Rise/Fall Time 1 V/ns (20% to 80%). . . . . . . . . . . . . . . . . . . . . .

Output Timing Reference Level 1.5 V. . . . . . . . . . . . . . . . . . . . . . . . . .

Output Load See Figure 1 Unless Otherwise Noted. . . . . . . . . . . . . .

READ/WRITE CYCLE TIMING (See Notes 1, 2, and 3)

69F618C–8.5 69F618C–9 69F618C–10 69F618C–12

Parameter Symbol

Cycle Time t
Clock High Pulse Width t
Clock Low Pulse Width t
Clock Access Time t
Output Enable to Output Valid t
Clock High to Output Active t
Clock High to Output Change t
Output Enable to Output Active t
Output Disable to Q High–Z t
Clock High to Q High–Z t
Setup Times: Address

Hold Times: Address

NOTES:

1. Write is defined as either any SBx
or ADSC is asserted.

2. All read and write cycle timings are referenced from K or G

3. G

4. This parameter is sampled and not 100% tested.

5. Measured at

ADSP

, ADSC, ADV

Data In

Write

Chip Enable

ADSP

, ADSC, ADV

Data In

Write

Chip Enable

is a don’t care after write cycle begins. To prevent bus contention, G should be negated prior to start of write cycle.

± 200 mV from steady state.

KHKH
KHKL
KLKH
KHQV

GLQV
KHQX1
KHQX2

GLQX

GHQZ

KHQZ

t

AVKH

t

ADKH

t

DVKH
t

WVKH

t

EVKH

t

KHAX

t

KHADX

t

KHDX
t

KHWX

t

KHEX

and SW low or SGW is low. Chip Enable is defined as SE1 low , SE2 high, and SE3 low whenever ADSP

Min Max Min Max Min Max Min Max

12 — 12 — 15 — 16.6 — ns

4 — 4 — 5 — 6 — ns

4 — 4 — 5 — 6 — ns
— 8.5 — 9 — 10 — 12 ns
— 5 — 5 — 5 — 6 ns

0 — 0 — 0 — 0 — ns 4

3 — 3 — 3 — 3 — ns 4

0 — 0 — 0 — 0 — ns 4
— 5 — 5 — 5 — 6 ns 4, 5

2.5 5 3 5 3 5 3 6 ns 4, 5

2.5 — 2.5 — 2.5 — 2.5 — ns

0.5 — 0.5 — 0.5 — 0.5 — ns

.

Unit Notes

MCM69F618C
8

OUTPUT

Z0 = 50

Ω

VT = 1.5 V

Figure 1. AC Test Load

RL = 50

Ω

MOTOROLA FAST SRAM

CD

READ/WRITE CYCLES

GLQV

t

Q(B) D(C) D(C+1) D(C+2) D(C+3) Q(D)

GLQX

t

SE2, SE3

ADSP, SA

GHQZ

t

BURST WRITE

IGNORED

KLKH

t

KHKL

t

KHKH

t

Q(B+2) Q(B+3)

BURST WRAPS AROUND

KHQX2

Q(B) Q(B+1)

t

KHQV

t

AB

K

SA

ADSP

ADSC

ADV

SE1

E

W

G

Q(A)Q(n)

DQx

KHQX1

t

KHQZ

t

BURST READSINGLE READ

DESELECTED SINGLE READ

W low = SGW low and/or SW and SBx low.

NOTE: E low = SE2 high and SE3 low.

MOTOROLA FAST SRAM

MCM69F618C

9

APPLICATION INFORMATION

The MCM69F618C BurstRAM is a high speed synchro­nous SRAM that is intended for use primarily in secondary or
level two (L2) cache memory applications. L2 caches are
found in a variety of classes of computers — from the desk­top personal computer to the high–end servers and trans­action processing machines. For simplicity, the majority of L2
caches today are direct mapped and are single bank imple­mentations. These caches tend to be designed for bus
speeds in the range of 33 to 66 MHz. At these bus rates,
flow–through (non–pipelined) BurstRAMs can be used since
their access times meet the speed requirements for a mini­mum–latency , zero–wait state L2 cache interface. Latency is
a measure (time) of “dead” time the memory system exhibits
as a result of a memory request.

For those applications that demand bus operation at great­er than 66 MHz or multi–bank L2 caches at 66 MHz, the pipe­lined (register/register) version of the 64K x 18 BurstRAM
(MCM69P618) allows the designer to maintain zero–wait
state operation. Multiple banks of BurstRAMs create addi­tional bus loading and can cause the system to otherwise
miss its timing requirements. The access time (clock–to–
valid–data) of a pipelined BurstRAM is inherently faster than
a non–pipelined device by a few nanoseconds. This does not
come without cost. The cost is latency — “dead” time.

For L2 cache designs that must minimize both latency and
wait states, flow–through BurstRAMs are the best choice in
achieving the highest performance in L2 cache design.

NON–BURST SYNCHRONOUS OPERATION

Although this BurstRAM has been designed for 68K–,
PowerPC–, 486–, i960–, and Pentium–based systems,
these SRAMs can be used in other high speed L2 cache or
memory applications that do not require the burst address
feature. Most L2 caches designed with a synchronous inter­face can make use of the MCM69F618C. The burst counter
feature of the BurstRAM can be disabled, and the SRAM can
be configured to act upon a continuous stream of addresses.
See Figure 2.

CONTROL PIN TIE VALUES EXAMPLE

Non–Burst

Sync Non–Burst,
Flow–Through
SRAM

NOTE: Although X is specified in the table as a don’t care, the pin

must be tied either high or low.

ADSP ADSC ADV SE1 SE2 LBO

H L H L H X

(H ≥ VIH, L ≤ VIL)

K

ADDR A B CD EFGH

SE3

W

G

DQ

Q(B)Q(A)

Q(D)Q(C) D(E)

D(F) D(G) D(H)

WRITESREADS

Figure 2. Example Configuration as Non–Burst Synchronous SRAM

MCM69F618C
10

MOTOROLA FAST SRAM

Motorola Memory Prefix
Part Number

ORDERING INFORMATION

(Order by Full Part Number)

MCM 69F618C XX XX X

Blank = Trays, R = Tape and Reel
Speed (8.5 = 8.5 ns, 9 = 9 ns, 10 = 10 ns, 12 = 12 ns)
Package (TQ = TQFP)

Full Part Numbers — MCM69F618CTQ8.5 MCM69F618CTQ9 MCM69F618CTQ10 MCM69F618CTQ12

MCM69F618CTQ8.5R MCM69F618CTQ9R MCM69F618CTQ10R MCM69F618CTQ12R

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty , representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. “T ypical” parameters which may be provided in Motorola
data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”
must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of
others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other
applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury
or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal
Opportunity/Affirmative Action Employer.

MOTOROLA FAST SRAM

MCM69F618C

11

–A–

–H–
–C–

SEATING
PLANE

0.05 (0.002)

4X

A–B0.20 (0.008) H

D

80 51

81

100

D1/2

2X 20 TIPS

C D

A

S

S

A2

A1

R1

VIEW AB

–D–

D1

D

A–B0.20 (0.008)

L2

L

L1

P ACKAGE DIMENSIONS

TQ PACKAGE

TQFP

CASE 983A–01

2X 30 TIPS

A–B0.20 (0.008) C D

50

E/2

–B–

E1/2

31

301

D/2

q

2

q

3

q

1

0.25 (0.010)

GAGE PLANE

R2

q

0.10 (0.004)

VIEW AB

E1

e

e/2

B
B

–X–

X=A, B, OR D

VIEW Y

E

BASE

METAL

PLATING

b1

c

c1

b

0.13 (0.005) D

M

S

A–B

C

S

SECTION B–B

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DATUM PLANE –H– IS LOCATED AT BOTTOM OF
LEAD AND IS COINCIDENT WITH THE LEAD
WHERE THE LEAD EXITS THE PLASTIC BODY AT
THE BOTTOM OF THE PARTING LINE.

C

4. DATUMS –A–, –B– AND –D– TO BE DETERMINED
AT DATUM PLANE –H–.

5. DIMENSIONS D AND E TO BE DETERMINED AT
SEATING PLANE –C–.

6. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS 0.25
(0.010) PER SIDE. DIMENSIONS D1 AND B1 DO
INCLUDE MOLD MISMATCH AND ARE
DETERMINED AT DATUM PLANE –H–.

7. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. DAMBAR PROTRUSION SHALL
NOT CAUSE THE b DIMENSION TO EXCEED 0.45
(0.018).

_
_

_

INCHESMILLIMETERS

0.020 REF

_
_
_
_

_
_

_

DIM MIN MAX MIN MAX

A ––– 1.60 ––– 0.063
A1 0.05 0.15 0.002 0.006
A2 1.35 1.45 0.053 0.057

b 0.22 0.38 0.009 0.015
b1 0.22 0.33 0.009 0.013

c 0.09 0.20 0.004 0.008
c1 0.09 0.16 0.004 0.006

D 22.00 BSC 0.866 BSC
D1 20.00 BSC 0.787 BSC

E 16.00 BSC 0.630 BSC
E1 14.00 BSC 0.551 BSC

e 0.65 BSC 0.026 BSC

L 0.45 0.75 0.018 0.030
L1 1.00 REF 0.039 REF
L2 0.50 REF

S 0.20 ––– 0.008 –––
R1 0.08 ––– 0.003 –––
R2 0.08 0.20 0.003 0.008

q

0 7 0 7

_

q

0 ––– 0 –––

1

_

q

11 13 11 13

2

_

q

11 13 11 13

3

_

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