Datasheet MCM6926AWJ8R, MCM6926AWJ12R, MCM6926AWJ8, MCM6926AWJ10R, MCM6926AWJ12 Datasheet (Motorola)

MCM6926A

1

MOTOROLA FAST SRAM

Advance Information

128K x 8 Bit Fast Static Random
Access Memory

The MCM6926A is a 1,048,576 bit static random access memory organized
as 131,072 words of 8 bits. Static design eliminates the need for external clocks
or timing strobes.

Output enable (G

) is a special control feature that provides increased system

flexibility and eliminates bus contention problems.

This device meets JEDEC standards for functionality and revolutionary pinout,
and is available in a 400 mil plastic small–outline J–leaded package.

• Single 3.3 V Power Supply

• Fully Static — No Clock or Timing Strobes Necessary

• All Inputs and Outputs Are TTL Compatible

• Three State Outputs

• Fast Access Times: 8, 10, 12, 15 ns

• Center Power and I/O Pins for Reduced Noise

• Fully 3.3 V BiCMOS

BLOCK DIAGRAM

ROW

DECODER

MEMORY

MATRIX

512 ROWS x 256 x 8

COLUMNS

INPUT

DATA

CONTROL

COLUMN I/O

COLUMN DECODER

A
A
A
A
A
A
A
A

DQ

AA A A

E

W

V

DD

V

SS

A

A A A A

DQ

G

This document contains information on a new product. Motorola reserves the right to change or discontinue this product without notice.

Order this document

by MCM6926A/D

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

PIN ASSIGNMENT

MCM6926A

WJ PACKAGE

400 MIL SOJ

CASE 857A–02

32
31
30
29
28
27

26
25
24
23
22
21

2
3

1

5
6

4

7

9
10

8

12
13

11

14

20

15
16

19
18

17

A
A
A
E

A

W

A
A

A

V

DD

A

A
A

A

DQ

DQ

A
G

A

A

V

SS

DQ

DQ

AA

A

DQ

DQ

DQ

DQ

A Address Input. . . . . . . . . . . . . . . . . . . . . . .

E

Chip Enable. . . . . . . . . . . . . . . . . . . . . . . .

W

Write Enable. . . . . . . . . . . . . . . . . . . . . . .

G

Output Enable. . . . . . . . . . . . . . . . . . . . .

DQ Data Input/Output. . . . . . . . . . . . . . . . .

V

DD

+ 3.3 V Power Supply. . . . . . . . . . . . .

V

SS

Ground. . . . . . . . . . . . . . . . . . . . . . . . .

PIN NAMES

V

SS

V

DD

REV 1
2/25/97

 Motorola, Inc. 1997

MCM6926A
2

MOTOROLA FAST SRAM

TRUTH TABLE (X = Don’t Care)

E G W Mode VDD Current Output Cycle

H X X Not Selected I

SB1

, I

SB2

High–Z —

L H H Output Disabled I

DDA

High–Z —

L L H Read I

DDA

D

out

Read Cycle

L X L Write I

DDA

High–Z Write Cycle

ABSOLUTE MAXIMUM RATINGS (See Note)

Rating

Symbol Value Unit

Power Supply Voltage V

DD

– 0.5 to + 4.6 V

Voltage Relative to VSS for Any Pin
Except V

DD

Vin, V

out

– 0.5 to VDD + 0.5 V

Output Current I

out

± 30 mA

Power Dissipation P

D

0.6 W

Temperature Under Bias T

bias

– 10 to + 85 °C

Operating Temperature T

A

0 to + 70 °C

Storage Temperature — Plastic T

stg

– 55 to + 125 °C

NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are

exceeded. Functional operation should be restricted to RECOMMENDED OPER­ATING CONDITIONS. Exposure to higher than recommended voltages for
extended periods of time could affect device reliability.

DC OPERA TING CONDITIONS AND CHARACTERISTICS

(VDD = 3.3 V + 10%, – 5%, TA = 0 to 70°C, Unless Otherwise Noted)

RECOMMENDED OPERATING CONDITIONS

Parameter Symbol Min Typ Max Unit

Supply Voltage (Operating Voltage Range) V

DD

3.135 3.3 3.6 V

Input High Voltage V

IH

2.2 —

VDD + 0.3**

V

Input Low Voltage V

IL

– 0.5*

— 0.8 V

*VIL (min) = – 0.5 V dc; VIL (min) = – 2.0 V ac (pulse width ≤ 2.0 ns) for I ≤ 20.0 mA.

**VIH (max) = VDD + 0.3 V dc; VIH (max) = VDD + 2 V ac (pulse width ≤ 2.0 ns) for I ≤ 20.0 mA.

DC CHARACTERISTICS

Parameter Symbol Min Max Unit

Input Leakage Current (All Inputs, Vin = 0 to VDD) I

lkg(I)

— ± 1.0 µA

Output Leakage Current (E = VIH, V

out

= 0 to VDD) I

lkg(O)

— ± 1.0 µA

Output Low Voltage (IOL = + 8.0 mA) V

OL

— 0.4 V

Output High Voltage (IOH = – 4.0 mA) V

OH

2.4 — V

This device contains circuitry to protect the
inputs against damage due to high static volt­ages or electric fields; however, it is advised
that normal precautions be taken to avoid
application of any voltage higher than maxi­mum rated voltages to these high–impedance
circuits.

This BiCMOS memory circuit has been de­signed to meet the dc and ac specifications
shown in the tables, after thermal equilibrium
has been established. The circuit is in a test
socket or mounted on a printed circuit board
and transverse air flow of at least 500 linear feet
per minute is maintained.

MCM6926A

3

MOTOROLA FAST SRAM

POWER SUPPLY CURRENTS (See Note 1)

6926A–8 6926A–10 6926A–12 6926A–15

Parameter Symbol

Typ Max Typ Max Typ Max Typ Max

Unit Notes

AC Active Supply Current

(I

out

= 0 mA) (VDD = max, f = f

max

)

I

DDA

— 150 — 130 — 120 — 110 mA 2, 3, 4

Active Quiescent Current

(E

= VIL, VDD = max, f = 0 MHz)

I

DD2

— 80 — 80 — 80 — 80 mA

AC Standby Current

(E

= VIH, VDD = max, f = f

max

)

I

SB1

— 50 — 45 — 40 — 35 mA 2, 3, 4

CMOS Standby Current

(VDD = max, f = 0 MHz,
E

≥ VDD – 0.2 V,

Vin ≤ VSS + 0.2 V, or ≥ VDD – 0.2 V)

I

SB2

— 20 — 20 — 20 — 20 mA

NOTES:

1. Typical current = 25°C @ 3.3 V.

2. Reference AC Operating Conditions and Characteristics for input and timing (VIH/VIL, tr/tf, pulse level 0 to 3.0 V , VIH = 3.0 V).

3. All address transition simultaneously low (LSB) and then high (MSB).

4. Data states are all zero.

CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, T

A

= 25°C, Periodically Sampled Rather Than 100% Tested)

Parameter Symbol Typ Max Unit

Address Input Capacitance C

in

— 6 pF

Control Pin Input Capacitance C

in

— 6 pF

Input/Output Capacitance C

I/O

— 8 pF

MCM6926A
4

MOTOROLA FAST SRAM

AC OPERA TING CONDITIONS AND CHARACTERISTICS

(VDD = 3.3 V + 10%, – 5%, TA = 0 to +70°C, Unless Otherwise Noted)

Input Timing Measurement Reference Level 1.5 V. . . . . . . . . . . . . . .

Input Pulse Levels 0 to 3.0 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input Rise/Fall Time 2 ns. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output Timing Measurement Reference Level 1.5 V. . . . . . . . . . . . .

Output Load See Figure 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

READ CYCLE TIMING (See Notes 1 and 2)

6926A–8 6926A–10 6926A–12 6926A–15

Parameter Symbol

Min Max Min Max Min Max Min Max

Unit Notes

Read Cycle Time t

AVAV

8 — 10 — 12 — 15 — ns 3

Address Access Time t

AVQV

— 8 — 10 — 12 — 15 ns

Enable Access Time t

ELQV

— 8 — 10 — 12 — 15 ns

Output Enable Access Time t

GLQV

— 4 — 5 — 6 — 7 ns

Output Hold from Address Change t

AXQX

3 — 3 — 3 — 3 — ns

Enable Low to Output Active t

ELQX

3 — 3 — 3 — 3 — ns 4, 5, 6

Output Enable Low to Output Active t

GLQX

0 — 0 — 0 — 0 — ns 4, 5, 6

Enable High to Output High–Z t

EHQZ

— 4 — 5 — 6 — 7 ns 4, 5, 6

Output Enable High to Output High–Z t

GHQZ

— 4 — 5 — 6 — 7 ns 4, 5, 6

NOTES:

1. W

is high for read cycle.

2. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycles.

3. All read cycle timings are referenced from the last valid address to the first transitioning address.

4. At any given voltage and temperature, t

EHQZ

max < t

ELQX

min, and t

GHQZ

max < t

GLQX

min, both for a given device and from device

to device.

5. Transition is measured 200 mV from steady–state voltage.

6. This parameter is sampled and not 100% tested.

7. Device is continuously selected (E

= VIL, G = VIL).

8. Addresses valid prior to or coincident with E

going low.

The table of timing values shows either a minimum
or a maximum limit for each parameter. Input require­ments are specified from the external system point of
view. Thus, address setup time is shown as a mini­mum since the system must supply at least that much
time. On the other hand, responses from the memory
are specified from the device point of view. Thus, the
access time is shown as a maximum since the device
never provides data later than that time.

TIMING LIMITS

OUTPUT

Z0 = 50

Ω

RL = 50

Ω

VL = 1.5 V

Figure 1. AC Test Load

MCM6926A

5

MOTOROLA FAST SRAM

Q (DATA OUT)

A (ADDRESS)

DATA VALIDPREVIOUS DATA VALID

t

AVAV

t

AXQX

t

AVQV

READ CYCLE 1 (See Note 7)

t

EHQZ

DATA VALID

t

GHQZ

t

AVAV

t

ELQX

t

ELQV

E (CHIP ENABLE)

Q (DATA OUT)

A (ADDRESS)

t

AVQV

t

GLQX

t

GLQV

G (OUTPUT ENABLE)

READ CYCLE 2 (See Note 8)

MCM6926A
6

MOTOROLA FAST SRAM

WRITE CYCLE 1 (W Controlled, See Notes 1 and 2)

6926A–8 6926A–10 6926A–12 6926A–15

Parameter Symbol

Min Max Min Max Min Max Min Max

Unit Notes

Write Cycle Time t

AVAV

8 — 10 — 12 — 15 — ns 3

Address Setup Time t

AVWL

0 — 0 — 0 — 0 — ns

Address Valid to End of W rite t

AVWH

8 — 9 — 10 — 12 — ns

Address Valid to End of W rite, G High t

AVWH

7 — 8 — 9 — 10 — ns

Write Pulse Width t

WLWH

,

t

WLEH

8 — 9 — 10 — 12 — ns

Write Pulse Width, G High t

WLWH

,

t

WLEH

7 — 8 — 9 — 10 — ns

Data Valid to End of W rite t

DVWH

4 — 5 — 6 — 7 — ns

Data Hold Time t

WHDX

0 — 0 — 0 — 0 — ns

Write Low to Data High–Z t

WLQZ

— 4 — 5 — 6 — 7 ns 4,5,6

Write High to Output Active t

WHQX

3 — 3 — 3 — 3 — ns 4,5,6

Write Recovery Time t

WHAX

0 — 0 — 0 — 0 — ns

NOTES:

1. A write occurs during the overlap of E

low and W low.

2. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycles.

3. All write cycle timings are referenced from the last valid address to the first transitioning address.

4. Transition is measured 200 mV from steady–state voltage.

5. This parameter is sampled and not 100% tested.

6. At any given voltage and temperature, t

WLQZ

max < t

WHQX

min both for a given device and from device to device.

DATA VALID

t

DVWH

t

AVWL

t

AVWH

t

AVAV

t

WHAX

t

WLWH

t

WHDX

t

WLQZ

t

WHQX

HIGH–Z

HIGH–Z

A (ADDRESS)

W

(WRITE ENABLE)

E

(CHIP ENABLE)

Q (DATA OUT)

D (DATA IN)

t

WLEH

WRITE CYCLE 1

MCM6926A

7

MOTOROLA FAST SRAM

WRITE CYCLE 2 (E Controlled, See Notes 1 and 2)

6926A–8 6926A–10 6926A–12 6926A–15

Parameter Symbol

Min Max Min Max Min Max Min Max

Unit Notes

Write Cycle Time t

AVAV

8 — 10 — 12 — 15 — ns 3

Address Setup Time t

AVEL

0 — 0 — 0 — 0 — ns

Address Valid to End of W rite t

AVEH

7 — 8 — 9 — 10 — ns

Enable to End of Write t

ELEH

,

t

ELWH

7 — 8 — 9 — 10 — ns 4,5

Data Valid to End of W rite t

DVEH

4 — 5 — 6 — 7 — ns

Data Hold Time t

EHDX

0 — 0 — 0 — 0 — ns

Write Recovery Time t

EHAX

0 — 0 — 0 — 0 — ns

NOTES:

1. A write occurs during the overlap of E

low and W low.

2. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycles.

3. All write cycle timings are referenced from the last valid address to the first transitioning address.

4. If E

goes low coincident with or after W goes low, the output will remain in a high impedance condition.

5. If E

goes high coincident with or before W goes high, the output will remain in a high impedance condition.

t

EHDX

t

DVEH

t

EHAX

t

ELWH

t

ELEH

t

AVEL

t

AVEH

DATA VALID

t

AVAV

HIGH–Z

A (ADDRESS)

W

(WRITE ENABLE)

E

(CHIP ENABLE)

Q (DATA OUT)

D (DATA IN)

WRITE CYCLE 2

MCM6926A
8

MOTOROLA FAST SRAM

P ACKAGE DIMENSIONS

32–LEAD

400 MIL SOJ

CASE 857A–02

T

0.25 (0.010) A B

S S S

T

0.17 (0.007) A B

S S S

T

0.17 (0.007) B A

S S S

T

0.17 (0.007) B A

S S S

L

32

17

16

1

MIN MINMAX MAX

INCHES MILLIMETERS

DIM

A
B
C
D
E

F
G
K
L
N
P
R
S

20.83

10.03

3.26

0.41

2.24

0.67

0.89

0.76

11.05

9.27

0.77

21.08

10.29

3.75

0.50

2.48

0.81

1.14

1.14

11.30

9.52

1.01

0.820

0.395

0.128

0.016

0.088

0.026

0.035

0.030

0.435

0.365

0.030

0.830

0.405

0.148

0.020

0.098

0.032

0.045

0.045

0.445

0.375

0.040

1.27 BSC

0.64 BSC

0.050 BSC

0.025 BSC

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. TO BE DETERMINED AT PLANE -T-.

4. DIMENSION A & B DO NOT INCLUDE MOLD
PROTRUSION. MOLD PROTRUSION SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.

5. DIMENSION A & B INCLUDE MOLD MISMATCH AND
ARE DETERMINED AT THE PARTING LINE.

G

K

D

32 PL

DETAIL Z

S RADIUS

R

-B-

P

F

32 PL

N

NOTE 3

NOTE 3

DETAIL Z

C

E

-A-

0.10 (0.004)

SEATING
PLANE

-T-

ORDERING INFORMATION

(Order by Full Part Number)

Motorola Memory Prefix
Part Number

Package (WJ = 400 mil SOJ)

Full Part Numbers — MCM6926AWJ8 MCM6926AWJ10 MCM6926AWJ12 MCM6926AWJ15

MCM6926AWJ8R MCM6926AWJ10R MCM6926AWJ12R MCM6926AWJ15R

Shipping Method (R = Tape and Reel, Blank = Rails)
Speed (8 = 8 ns, 10 = 10 ns, 12 = 12 ns, 15 = 15 ns)

MCM 6926A WJ XX X

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty , representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. “T ypical” parameters which may be provided in Motorola
data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”
must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of
others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other
applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury
or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal
Opportunity/Affirmative Action Employer.

Mfax is a trademark of Motorola, Inc.

How to reach us:
USA/EUROPE/ Locations Not Listed: Motorola Literature Distribution; JAPAN: Nippon Motorola Ltd.: SPD, Strategic Planning Office, 4–32–1,

P.O. Box 5405, Denver, Colorado 80217. 303–675–2140 or 1–800–441–2447 Nishi–Gotanda, Shinagawa–ku, Tokyo 141, Japan. 81–3–5487–8488
Mfax: [e-mail] – TOUCHTONE 602–244–6609 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park,

– US & Canada ONLY 1–800–774–1848 51 T ing Kok Road, Tai Po, N.T., Hong Kong. 852–26629298

INTERNET: http://motorola.com/sps

MCM6926A/D

◊