Page 1
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Advance Information
64K x 18 Bit BurstRAM
Synchronous Fast Static RAM
With Burst Counter and Self–Timed Write
The MCM67M618B is a 1,179,648 bit synchronous static random access
memory designed to provide a burstable, high–performance, secondary cache
for the MC68040 and PowerPC microprocessors. It is organized as 65,536
words of 18 bits, fabricated using Motorola’s high–performance silicon–gate
BiCMOS technology . The device integrates input registers, a 2–bit counter, high
speed SRAM, and high drive capability outputs onto a single monolithic circuit
for reduced parts count implementation of cache data RAM applications. Synchronous design allows precise cycle control with the use of an external clock
(K). BiCMOS circuitry reduces the overall power consumption of the integrated
functions for greater reliability .
Addresses (A0 – A15), data inputs (DQ0 – DQ17), and all control signals, except output enable (G
tive–edge–triggered noninverting registers.
Bursts can be initiated with either transfer start processor (TSP
transfer start cache controller (TSC
addresses are generated internally by the MCM67M618B (burst
sequence imitates that of the MC68040) and controlled by the burst
address advance (BAA
detailed information on burst controls.
Write cycles are internally self–timed and are initiated by the rising
edge of the clock (K) input. This feature eliminates complex off–chip
write pulse generation and provides increased flexibility for incoming
signals.
Dual write enables (LW
writeable bytes. LW controls DQ0 – DQ8 (the lower bits), while UW
controls DQ9 – DQ17 (the upper bits).
This device is ideally suited for systems that require wide data bus
widths and cache memory .
• Single 5 V ± 5% Power Supply
• Fast Access Times: 9/10/12 ns Max
• Byte Writeable via Dual Write Strobes
• Internal Input Registers (Address, Data, Control)
• Internally Self–Timed Write Cycle
• TSP
, TSC, and BAA Burst Control Pins
• Asynchronous Output Enable Controlled Three–State Outputs
• Common Data Inputs and Data Outputs
• High Board Density 52–PLCC Package
• 3.3 V I/O Compatible
), are clock (K) controlled through posi-
) or
) input pins. Subsequent burst
) input pin. The following pages provide more
and UW) are provided to allow individually
DQ10
V
CC
V
SS
DQ11
DQ12
DQ13
DQ14
V
SS
V
CC
DQ15
DQ16
DQ17
Order this document
by MCM67M618B/D
MCM67M618B
FN PACKAGE
PLASTIC
CASE 778–02
PIN ASSIGNMENT
A6A7E
7654321525150494847
8DQ9
9
10
11
12
13
14
15
16
17
18
19
20
21 22 23 24 25 26 27 28 29 30 31 32 33
A5
UW
A4A3A2
LW
A1
TSC
A0
TSP
SS
V
PIN NAMES
A0 – A15 Address Inputs. . . . . . . . . . . . . . . .
K Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BAA
LW
UW
TSP
, TSC Transfer Start. . . . . . . . . . . . . . . .
E
G
DQ0 – DQ17 Data Input/Output. . . . . . . . . .
V
CC
V
SS
All power supply and ground pins must be connected for proper operation of the device.
G
K
A8A9A10
BAA
46
45
44
43
42
41
40
39
38
37
36
35
34
CC
A15
A14
V
Burst Address Advance. . . . . . . . . . . .
Lower Byte Write Enable. . . . . . . . . . . .
Upper Byte Write Enable. . . . . . . . . . . .
+ 5 V Power Supply. . . . . . . . . . . . . . . .
A13
Output Enable. . . . . . . . . . . . . . . . . . . . . .
Chip Enable. . . . . . . . . . . . . . . . . . . . . . . . .
A12
A11
Ground. . . . . . . . . . . . . . . . . . . . . . . . . .
DQ8
DQ7
DQ6
V
CC
V
SS
DQ5
DQ4
DQ3
DQ2
V
SS
V
CC
DQ1
DQ0
The PowerPC name is a trademark of IBM Corp., used under license therefrom.
This document contains information on a new product under development. Motorola reserves the right to change or discontinue this product without notice.
REV 1
7/15/97
Motorola, Inc. 1997
MOTOROLA FAST SRAM
MCM67M618B
1
Page 2
BAA
TSC
TSP
BLOCK DIAGRAM (See Note)
BURST LOGIC
INTERNAL
ADDRESS
A1
A0
′
16
′
64K x 18
MEMORY
ARRAY
K
BINARY
COUNTER
LOAD
D1
Q1
Q0
D0
A1
EXTERNAL
A15 – A0
UW
LW
DQ0 – DQ8
DQ9 – DQ17
NOTE: All registers are positive–edge triggered. The TSC or TSP signals control the duration of the burst and the start of the next
ADDRESS
E
G
9
9
ADDRESS
REGISTERS
16
WRITE
REGISTER
ENABLE
REGISTER
A0
A15 – A2
18
DATA–IN
REGISTERS
99
9
9
OUTPUT
BUFFER
burst. When TSP is sampled low, any ongoing burst is interrupted and a read (independent of W and TSC) is performed
using the new external address. Alternatively , a TSP
–initiated two cycle WRITE can be performed by asserting TSP and
a valid address on the first cycle, then negating both TSP and TSC and asserting LW and/or UW with valid data on the
second cycle (see Single Write Cycle in WRITE CYCLES timing diagram).
When TSC
is sampled low (and TSP is sampled high), any ongoing burst is interrupted and a read or write (dependent on
W) is performed using the new external address. Chip enable (E) is sampled only when a new base address is loaded. After
the first cycle of the burst, BAA
controls subsequent burst cycles. When BAA is sampled low, the internal address is
advanced prior to the operation. When BAA is sampled high, the internal address is not advanced, thus inserting a wait
state into the burst sequence accesses. Upon completion of a burst, the address will wrap around to its initial state.
See BURST SEQUENCE TABLE. Write refers to either or both byte write enables (L W
, UW).
MCM67M618B
2
BURST SEQUENCE GRAPH (See Note)
0,0
′
, A0′ =
A1
NOTE: The external two values for A1 and A0
provide the starting point for the burst
sequence graph. The burst logic advances A1 and A0 as shown above.
1,1
0,1
1,0
MOTOROLA FAST SRAM
Page 3
SYNCHRONOUS TRUTH TABLE (See Notes 1, 2, and 3)
E
H L X X X L–H N/A Deselected
H X L X X L–H N/A Deselected
L L X X X L–H External Address Read Cycle, Begin Burst
L H L X L L–H External Address Write Cycle, Begin Burst
L H L X H L–H External Address Read Cycle, Begin Burst
X H H L L L–H Next Address Write Cycle, Continue Burst
X H H L H L–H Next Address Read Cycle, Continue Burst
X H H H L L–H Current Address Write Cycle, Suspend Burst
X H H H H L–H Current Address Read Cycle, Suspend Burst
NOTES:
1. X means Don’t Care.
2. All inputs except G
3. Wait states are inserted by suspending burst.
TSP TSC BAA LW or UW K Address Operation
must meet setup and hold times for the low–to–high transition of clock (K).
ASYNCHRONOUS TRUTH TABLE (See Notes 1 and 2)
Operation
Read L Data Out
Read H High–Z
Write X High–Z — Data In
Deselected X High–Z
NOTES:
1. X means Don’t Care.
2. For a write operation following a read operation, G
required setup time and held high through the input data hold time.
G I/O Status
must be high before the input data
ABSOLUTE MAXIMUM RATINGS (Voltages Referenced to V
Rating
Power Supply Voltage V
Voltage Relative to VSS for Any Pin
Except V
Output Current (per I/O) I
Power Dissipation P
Temperature Under Bias T
Ambient Temperature T
Storage Temperature T
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
CC
exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for
extended periods of time could affect device reliability.
Symbol Value Unit
CC
Vin, V
out
D
bias
A
stg
– 0.5 to VCC + 0.5 V
out
= 0 V)
SS
– 0.5 to + 7.0 V
± 30 mA
1.6 W
– 10 to + 85 °C
0 to +70 °C
– 55 to + 125 °C
This device contains circuitry to protect the
inputs against damage due to high static voltages or electric fields; however, it is advised that
normal precautions be taken to avoid application
of any voltage higher than maximum rated voltages to this high–impedance circuit.
This BiCMOS memory circuit has been
designed to meet the dc and ac specifications
shown in the tables, after thermal equilibrium
has been established.
This device contains circuitry that will
ensure the output devices are in High–Z at
power up.
MOTOROLA FAST SRAM
MCM67M618B
3
Page 4
DC OPERA TING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V ± 5%, TA = 0 to + 70°C, Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS
Parameter
Supply Voltage (Operating Voltage Range) V
Input High Voltage V
Input Low Voltage V
*VIL (min) = – 0.5 V dc; VIL (min) = – 2.0 V ac (pulse width ≤ 20.0 ns) for I ≤ 20.0 mA.
**VIH (max) = VCC + 0.3 V dc; VIH (max) = VCC + 2.0 V ac (pulse width ≤ 20.0 ns) for I ≤ 20.0 mA.
(Voltages Referenced to VSS = 0 V)
Symbol Min Max Unit
CC
IH
IL
4.75 5.25 V
2.2 VCC + 0.3** V
– 0.5* 0.8 V
DC CHARACTERISTICS AND SUPPLY CURRENTS
Parameter Symbol Min Max Unit
Input Leakage Current (All Inputs, Vin = 0 to VCC) I
Output Leakage Current (G = VIH) I
AC Supply Current (Device Selected, All Outputs Open, MCM67M618B–9
Freq = Max) MCM67M618B–10
MCM67M618B–12
CMOS Standby Supply Current (Device Deselected, Freq = 0, VCC = Max,
All Inputs Static at CMOS Levels Vin ≤ VSS + 0.2 V or ≥ VCC – 0.2 V)
Clock Running (Device Deselected, Freq = Max, VCC = Max,
All Inputs Toggling at CMOS Levels Vin ≤ VSS + 0.2 V or ≥ VCC – 0.2 V)
Output Low Voltage (IOL = + 8.0 mA) V
Output High Voltage (IOH = – 4.0 mA) V
NOTE: Good decoupling of the local power supply should always be used. DC characteristics are guaranteed for all possible 68040 and PowerPC
bus cycles.
lkg(I)
lkg(O)
I
CCA
I
SB2
I
SB4
OL
OH
— ± 1.0 µA
— ± 1.0 µA
— TBD mA
— TBD mA
— TBD mA
— 0.4 V
2.4 3.3 V
CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, T
Parameter
Input Capacitance C
Input/Output Capacitance C
= 25°C, Periodically Sampled Rather Than 100% Tested)
A
Symbol Min Typ Max Unit
in
I/O
— 4 5 pF
— 6 8 pF
MCM67M618B
4
MOTOROLA FAST SRAM
Page 5
AC OPERA TING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V ± 5%, TA = 0 to + 70°C, Unless Otherwise Noted)
Input Timing Measurement Reference Level 1.5 V. . . . . . . . . . . . . . .
Input Pulse Levels 0 to 3.0 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Rise/Fall Time 3 ns. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Timing Reference Level 1.5 V. . . . . . . . . . . . . . . . . . . . . . . . . .
Output Load See Figure 1 Unless Otherwise Noted. . . . . . . . . . . . . .
READ/WRITE CYCLE TIMING (See Notes 1, 3, and 4)
MCM67M618B–9 MCM67M618B–10 MCM67M618B–12
Parameter Symbol
Cycle Time t
Clock Access Time t
Output Enable to Output Valid t
Clock High to Output Active t
Clock High to Output Change t
Output Enable to Output Active t
Output Disable to Q High–Z t
Clock High to Q High–Z t
Clock High Pulse Width t
Clock Low Pulse Width t
Setup Times: Address
Hold Times: Address
NOTES:
1. In setup and hold times, W (write) refers to either one or both byte write enables LW
2. A read cycle is defined by UW
high for the setup and hold times.
3. All read and write cycle timings are referenced from K or G
4. G
is a don’t care when UW or LW is sampled low.
5. Maximum access times are guaranteed for all possible MC68040 and PowerPC external bus cycles.
6. Transition is measured ± 500 mV from steady-state voltage. This parameter is sampled rather than 100% tested. At any given voltage and
temperature, t
7. This is a synchronous device. All addresses must meet the specified setup and hold times for
TSC
is low, and the chip is selected. All other synchronous inputs must meet the specified setup and hold times for
of K when the chip is enabled. Chip enable must be valid at each rising edge of clock for the device (when TSP
enabled.
Address Status
Data In
Address Advance
Address Status
Address Advance
KHQZ
Write
Chip Enable
Data In
Write
Chip Enable
max is less than t
KHKH
KHQV
GLQV
KHQX1
KHQX2
GLQX
GHQZ
KHQZ
KHKL
KLKH
t
AVKH
t
TSVKH
t
DVKH
t
WVKH
t
BAVKH
t
EVKH
t
KHAX
t
KHTSX
t
KHDX
t
KHWX
t
KHBAX
t
KHEX
and LW high or TSP low for the setup and hold times. A write cycle is defined by LW or UW low and TSP
KHQZ1
Min Max Min Max Min Max
15 — 16.6 — 20 — ns
— 9 — 10 — 12 ns 5
— 5 — 5 — 6 ns
6 — 6 — 6 — ns
3 — 3 — 3 — ns
0 — 0 — 0 — ns
— 6 — 7 — 7 ns 6
3 6 3 7 3 7 ns 6
5 — 5 — 6 — ns
5 — 5 — 6 — ns
2.5 — 2.5 — 2.5 — ns 7
0.5 — 0.5 — 0.5 — ns 7
and UW.
.
min for a given device and from device to device.
ALL
rising edges of K whenever TSP or
Unit Notes
ALL
or TSC is low) to remain
rising edges
MOTOROLA FAST SRAM
OUTPUT
Z0 = 50
Ω
VL = 1.5 V
Figure 1.T est Load
RL = 50
Ω
MCM67M618B
5
Page 6
KHQZ
t
(BURST WRAPS AROUND
TO ITS INITIAL STATE)
Q(A2 + 2)Q(A2 + 1)Q(A2)Q(A2 + 3)Q(A2 + 2)Q(A2 + 1)Q(A2)Q(A1)
READ CYCLES
KHKH
t
KLKH
t
KHKL
t
KHTSX
t
TSVKH
t
KHAX
t
KHWX
t
t
WVKH
KHEX
t
BAVKH
t
KHBAX
t
(BAA SUSPENDS BURST)
KHQV
t
GLQV
t
KHQV
t
KHQX2
t
GHQZ
t
BURST READ
SINGLE READ
KHTSX
t
K
MCM67M618B
6
TSVKH
t
TSP
TSC
AVKH
t
A1 A2
ADDRESS
LW, UW
EVKH
t
GLQX
t
E
BAA
G
DATA OUT
NOTE: Q(A2) represents the first output data from the base address A2; Q(A2 + 1) represents the next output data in the burst sequence with A2 as the base address.
MOTOROLA FAST SRAM
Page 7
TSC STAR TS NEW BURST
A3
KHWX
t
WVKH
t
KHBAX
t
BAVKH
t
KHDX
t
DVKH
t
D(A3 + 2)D(A3 + 1)D(A3)D(A2 + 3)D(A2 + 2)D(A2 + 1)D(A2) D(A2 + 1)D(A1)
NEW BURST WRITEBURST WRITE
WRITE CYCLES
KLKH
t
KHKH
t
KHKL
KHTSX
t
t
TSVKH
t
KHTSX
t
TSVKH
t
KHAX
t
AVKH
t
A1 A2
W IS IGNORED FOR FIRST CYCLE WHEN TSP INITIATES BURST
KHEX
t
t
EVKH
BAA SUSPENDS BURST
GHQZ
t
(WITH A SUSPENDED CYCLE)
SINGLE WRITEBURST READ
Q(An – 1) Q(An)
K
TSP
MOTOROLA FAST SRAM
TSC
A
LW, UW
E
BAA
G
D
Q
MCM67M618B
7
Page 8
COMBINATION READ/WRITE CYCLE (E Low, TSC High)
t
KHKH
K
TSP
ADDRESS
, UW
LW
BAA
G
DATA IN
t
TSVKH
t
AVKH
t
t
KHTSX
t
KHAX
A1 A2 A3
t
KHQV
KHKL
t
WVKH
t
BAVKH
t
DVKH
D(A2)
t
KLKH
t
KHWX
t
KHBAX
t
KHDX
t
GLQV
DATA OUT
t
KHQX1
t
GHQZ
Q(A1)
READ WRITE BURST READ
t
GLQX
t
KHQX2
Q(A3) Q(A3 + 1) Q(A3 + 2)
MCM67M618B
8
MOTOROLA FAST SRAM
Page 9
ADDRESS
MPC604
(PowerPC
SYSCLK
CONTROL
APPLICATION EXAMPLE
DATA BUS
DATA
ADDRESS BUS
CLOCK
)
TS
512K Byte Burstable, Secondary Cache
Using Four MCM67M618BFN9s with a 66 MHz MPC604 PowerPC
ADDR ADDR DATA
K
CACHE
CONTROL
LOGIC
K
G
TSC
W
MCM67M618BFN9
BAA
TSP
Figure 2.
MOTOROLA FAST SRAM
MCM67M618B
9
Page 10
Motorola Memory Prefix
ORDERING INFORMATION
(Order by Full Part Number)
MCM 67M618B XX XX
Speed (9 = 9 ns, 10 = 10 ns, 12 = 12 ns)
Part Number
Package (FN = PLCC)
Full Part Numbers — MCM67M618BFN9 MCM67M618BFN10 MCM67M618BFN12
MCM67M618B
10
MOTOROLA FAST SRAM
Page 11
P ACKAGE DIMENSIONS
FN PACKAGE
52–LEAD PLCC
CASE 778–02
–L–
C
–N–
52 1
Z
G
G1
0.010 (0.25) L–M
S
K1
K
VIEW S
V
A
R
VIEW S
STS
N
H
0.007 (0.18) L–M
0.007 (0.18) L–M
F
BRK
Y
D
–M–
W
D
0.007 (0.18) L–M
M
0.007 (0.18) L–M
E
0.004 (0.100)
SEATING
–T–
J
PLANE
M
M
M
STS
STS
0.007 (0.18) L–M
B
U
M
0.007 (0.18) L–M
M
STS
N
STS
N
Z
G1
X
0.010 (0.25) L–M
S
STS
N
VIEW D–D
STS
N
STS
N
N
N
NOTES:
1. DATUMS –L–, –M–, AND –N– DETERMINED WHERE
TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT
MOLD PARTING LINE.
2. DIMENSION G1, TRUE POSITION TO BE MEASURED
AT DATUM –T–, SEATING PLANE.
3. DIMENSIONS R AND U DO NOT INCLUDE MOLD
FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250)
PER SIDE.
4. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
5. CONTROLLING DIMENSION: INCH.
6. THE PACKAGE TOP MAY BE SMALLER THAN THE
PACKAGE BOTTOM BY UP TO 0.012 (0.300).
DIMENSIONS R AND U ARE DETERMINED AT THE
OUTERMOST EXTREMES OF THE PLASTIC BODY
EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE
BURRS AND INTERLEAD FLASH, BUT INCLUDING
ANY MISMATCH BETWEEN THE TOP AND BOTTOM
OF THE PLASTIC BODY.
7. DIMENSION H DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTRUSION(S) SHALL NOT CAUSE THE H
DIMENSION TO BE GREATER THAN 0.037 (0.940).
THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE
H DIMENSION TO BE SMALLER THAN 0.025 (0.635).
DIM MIN MAX MIN MAX
A 0.785 0.795 19.94 20.19
B 0.785 0.795 19.94 20.19
C 0.165 0.180 4.20 4.57
E 0.090 0.110 2.29 2.79
F 0.013 0.019 0.33 0.48
G 0.050 BSC 1.27 BSC
H 0.026 0.032 0.66 0.81
J 0.020 ––– 0.51 –––
K 0.025 ––– 0.64 –––
R 0.750 0.756 19.05 19.20
U 0.750 0.756 19.05 19.20
V 0.042 0.048 1.07 1.21
W 0.042 0.048 1.07 1.21
X 0.042 0.056 1.07 1.42
Y ––– 0.020 ––– 0.50
Z 2 10 2 10
____
G1 0.710 0.730 18.04 18.54
K1 0.040 ––– 1.02 –––
MILLIMETERSINCHES
MOTOROLA FAST SRAM
MCM67M618B
11
Page 12
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty , representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. “T ypical” parameters which may be provided in Motorola
data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”
must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of
others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other
applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury
or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal
Opportunity/Affirmative Action Employer.
How to reach us:
USA/EUROPE/ Locations Not Listed: Motorola Literature Distribution; JAPAN: Nippon Motorola Ltd.; SPD, Strategic Planning Office; 4–32–1,
P.O. Box 5405, Denver , Colorado, 80217. 303–675–2140 or 1–800–441–2447 Nishi–Gotanda; Shinagawa–ku, T okyo 141, Japan. 81–3–5487–8488
Mfax: RMF AX0@email.sps.mot.com – TOUCHTONE 602–244–6609 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B T ai Ping Industrial Park,
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INTERNET: http:// motorola.com/sps
Mfax is a trademark of Motorola, Inc.
MCM67M618B
12
◊
MOTOROLA FAST SRAM
MCM67M618B/D
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