Datasheet MCM69D536TQ6R, MCM69D536TQ8, MCM69D536TQ8R, MCM67J618AFN5, MCM69D536TQ6 Datasheet (Motorola)

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Page 1

MCM69D536

MOTOROLA FAST SRAM

32K x 36 Bit Synchronous Dual I/O, Dual Address SRAM

The MCM69D536 is a 1M–bit static random access memory, organized as 32K words of 36 bits. It features common data input and data output buffers and incorporates input and output registers on–board with high speed SRAM.

The MCM69D536 allows the user to concurrently perform reads, writes, or pass–through cycles in combination on the two data ports. The two address ports (AX, AY) determine the read or write locations for their respective data ports (DQX, DQY).

The synchronous design allows for precise cycle control with the use of an external single clock (K). All signal pins except output enables (GX

, GY) are

registered on the rising edge of clock (K).

The pass–through feature allows data to be passed from one port to the other, in either direction. The PTX

input must be asserted to pass data from port X to

port Y. The PTY

will likewise pass data from port Y to port X. A pass–through

operation takes precedence over a read operation.

For the case when AX and AY are the same, certain protocols are followed. If both ports are read, the reads occur normally . If one port is written and the other is read, the read from the array will occur before the data is written. If both ports are written, only the data on DQY will be written to the array.

• Single 3.3 V ± 5% Power Supply

• Fast Access Times: 6/8 ns Max

• Throughput of 2.98 Gigabits/Second

• Single Clock Operation

• Address, Data Input, E1

, E2, PTX, PTY, WX, WY, and Data Output

Registers On–Chip

• 83 MHz Maximum Clock Frequency

• Self–Timed Write

• Two Bi–Directional Data Buses

• Can be Configured as Separate I/O

• Pass–Through Feature

• Asynchronous Output Enables (GX

, GY)

• L VTTL Compatible I/O

• Concurrent Reads and Writes

• 176–Pin TQFP Package

Suggested Applications

— ATM — Ethernet Switches — Routers — Cell/Frame Buffers — SNA Switches — Shared Memory

Product Family Configurations

Part

Number

Dual

Address

Single

Address

Dual

I/O

Separate

I/O

Configuration V

MCM69D536

Note 1

Note 2 32K x 36 3.3 V

MCM69D618

Note 1

Note 2 64K x 18 3.3 V

MCM67Q709A

n n

128K x 9 5.0 V

MCM67Q909

n n

512K x 9 5.0 V

NOTES:

1. Tie AX and AY address ports together for the part to function as a single address part.

2. Tie GX

high for DQX to be inputs and tie WY high and GY low for DQY to be outputs.

Order this document

by MCM69D536/D

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

MCM69D536

TQ PACKAGE

176 LEAD TQFP

CASE 1101–01

REV 4 1/16/98

 Motorola, Inc. 1998

Page 2

MCM69D536 2

MOTOROLA FAST SRAM

BLOCK DIAGRAM

PTX

ADDRESS

32K x 36 ARRAY

ADDRESS

WRITE X

PTX

PASS–THROUGH

DQX

WRITE

DRIVER

SENSE

AMPS

SENSE

AMPS

WRITE

DRIVER

WRITE Y

PTY

DATA IN

OUTPUT

DATA IN

ENABLE

REG 1

DQY

ENABLE

REG 2

Page 3

MCM69D536

MOTOROLA FAST SRAM

PIN ASSIGNMENT

DQX20

51 524849 50 56 575354 55 59605845 46 47 64636261

DQY20

DQX21

DQY21

DQX22

DQY22

DQX23

DQY23

DQX24

DQX35

DQY34

DQX34

SSi

DQY35

DQX25

DQY24

DQY28

DQX28

DQY25

SS DQY27 DQX27

SSi

21 22 23 24 25 26 27 28 29 30

DQX26 DQY26

SS DQY29

71 726968 70 76 7773 74 75 79 8078656667 84838281

DQY0

NCNCNC

DQX0

88878685

DQY1

DQX1

DQY30

DQX30

DQY31 DQX31 DQY32

DQX32

DQY33 DQX33

SSi

DQX29

DQX2

DQY2

DQX3

DQY3

DQX4

DQY4

DQX5

DQY5

DQX6

DQX17

DQY16

DQX16

DQY17

DQX7

DQY6

DQY10

DQX10

DQY7

DQY9

DQX9

SSi

98 97

100

103 102 101

105 104

108 107 106

109

110

111

112

113

114

115

116

117

118

95 94

93 92 91

DQX8

DQY8

DQY11

PTY

PTX

NCKNC

DQY18

AX7

AY6

AX6

DQX18

AY7

DQY19

DQX19

DQY12

DQX12

DQY13

DQX13

DQY14

DQX14

DQY15

DQX15

SSi

DQX11

128 127

130 129

132 131

125 124 123 122 121 120 119

126

170

175

174

173

172

168

169

165

164

167

176

171

166

158

157

162

161

160

159

163

150

155

154

153

152

148

149

145

144

147

156

151

138

137

142

141

140

139

143

134

133

136

135

146

SSi

AY5

AX5

AY4

AX4

AY3

AX3

AY2

AX2

AY1

AX1

AY0

AX0

AX10

AY10

AX11

AY11

AX12

AY12

AX13

AY13

AX14

AY14

SSi

AX9

AY9

AX8

AY8

VDDV

SSi

Page 4

MCM69D536 4

MOTOROLA FAST SRAM

PIN DESCRIPTIONS

Pin Locations Symbol Type Description

65, 63, 61, 59, 57, 55, 169, 167,

145, 143, 68, 70, 72, 74, 76

AX0 –

AX14

Input Address Port X. Never allow floating addresses for inputs AX0 – AX14.

A pullup resistor is needed.

64, 62, 60, 58, 56, 54, 168, 166,

144, 142, 69, 71, 73, 75, 77

AY0 –

AY14

Input Address Port Y. Never allow floating addresses for inputs AY0 – A Y14.

A pullup resistor is needed.

82, 86, 90, 94, 96, 100, 102, 106, 108,

113. 115, 119, 121, 125, 127, 131,

135, 139, 170, 174, 2, 6, 8, 12, 14, 18,

20, 25, 27, 31, 33, 37, 39, 43, 47, 51

DQX0 –

DQX35

I/O Data Input/Output Port X.

83, 87, 91, 95, 97, 101, 103, 107, 109,

112, 114, 118, 120, 124, 126, 130, 134,

138, 171, 175, 3, 7, 9, 13, 15, 19, 21,

24, 26, 30, 32, 36, 38, 42, 46, 50

DQY0 –

DQY35

I/O Data Input/Output Port Y.

150 E1 Input Synchronous Chip Enable: Active low. 151 E2 Input Synchronous Chip Enable: Active high. 152 GX Input Asynchronous Output Enable Port X Input:

Low — enables output buffers (DQXx pins). High — DQXx pins are high impedance.

153 GY Input Asynchronous Output Enable Port Y Input:

Low — enables output buffers (DQYx pins). High — DQYx pins are high impedance.

156 K Input Clock: This signal registers the address, data in, and all control signals

except G

. 146 PTX Input Pass–Through Port X. 147 PTY Input Pass–Through Port Y. 148 WX Input Synchronous Write Enable Port X. 149 WY Input Synchronous Write Enable Port Y.

4, 10, 16, 22, 28, 34, 40, 49,

67, 84, 92, 98, 104, 110,

116, 122, 128, 137, 155, 172

Supply + 3.3 V Power Supply.

5, 11, 17, 23, 29, 35, 41, 48,

66, 85, 93, 99, 105, 111,

117, 123. 129, 136, 154, 173

Supply Ground.

1, 44, 45, 52, 53, 88,

89, 132, 133, 165, 176

SSi

Input Bonded to die flag. No chip current flows through these pins.

78– 81, 140, 141, 157 – 164 NC — No Connection: There is no connection to the chip.

Page 5

MCM69D536

MOTOROLA FAST SRAM

TRUTH TABLE (See Notes 1 through 5)

Input at tn Clock

Operation Number

E1 E2 WX WY PTX PTY Operation

1 H X X X X X Deselected 2 X L X X X X Deselected 3 L H 0 X X X Write X Port 4 L H X 0 X X Write Y Port 5 L H X X 0 X Pass–Through X to Y 6 L H X X X 0 Pass–Through Y to X 7 L H 1 X 1 1 Read X 8 L H X 1 1 1 Read Y

NOTES:

1. GX

/GY must be controlled to avoid bus contention issues during write and pass–through cycles.

2. Operation numbers 3 – 6 can be used in any combination.

3. Operation numbers 4 and 7, 3 and 8, 7 and 8 can be combined.

4. Operation number 5 can not be combined with operation number 7 or 8 because pass–through takes precedence over a read operation.

5. Operation number 6 can not be combined with operation number 7 or 8 because pass–through takes precedence over a read operation.

ADDRESS & CONTROL

VALID

tn +

VALID

DATA INPUT D

VALID

DATA OUTPUT Q

PIPELINED READ ACCESS

PASS–THROUGH

ABSOLUTE MAXIMUM RATINGS (See Note)

Rating

Symbol Value Unit

Power Supply Voltage V

– 0.5 to + 4.6 V

Voltage Relative to VSS for Any Pin Except V

Vin, V

out

– 0.5 to VDD + 0.5 V

Output Current I

out

± 20 mA

Power Dissipation P

TBD W

Temperature Under Bias T

bias

– 10 to + 85 °C

Operating Temperature T

0 to + 70 °C

Storage Temperature — Plastic T

stg

– 55 to + 125 °C

NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are

exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability.

This is a synchronous device. All synchronous inputs must meet specified setup and hold times with stable logic levels for

ALL

rising

edges of clock (K) while the device is selected.

This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to these high–impedance circuits.

Page 6

MCM69D536 6

MOTOROLA FAST SRAM

PACKAGE THERMAL CHARACTERISTICS (See Note 1)

Rating

Symbol TQFP Unit Notes

Junction to Ambient (@ 200 lfm) Single–Layer Board

Four–Layer Board

θJA

40 35

°C/W 2

Junction to Board (Bottom) R

θJB

23 °C/W 3

Junction to Case (Top) R

θJC

9 °C/W 4

NOTES:

1. Junction temperature is a function of on–chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, board population, and board thermal resistance.

2. Per SEMI G38–87.

3. Indicates the average thermal resistance between the die and the printed circuit board.

4. Indicates the average thermal resistance between the die and the case top surface via the cold plate method (MIL SPEC–883 Method 1012.1).

DC OPERA TING CONDITIONS AND CHARACTERISTICS

(VDD = 3.3 V ± 5%, TA = 0 to + 70°C, Unless Otherwise Noted)

RECOMMENDED OPERATING CONDITIONS AND SUPPLY CURRENTS

Parameter Symbol Min Max Unit

Supply Voltage (Operating Voltage Range) V

3.135 3.465 V

Input High Voltage V

2.0 VDD + 0.5** V

Input Low Voltage V

– 0.5* 0.8 V

Input Leakage Current (All Inputs, Vin = 0 to VDD) I

lkg(I)

— ± 1.0 µA

Output Leakage Current (E = VIH, V

out

= 0 to VDD) I

lkg(O)

— ± 1.0 µA

AC Supply Current (I

out

= 0 mA) (VDD = max, f = f

max

) MCM69D536–6 ns

MCM69D536–8 ns

DDA

— —

300 300

CMOS Standby Supply Current (Deselected, Clock (K) MCM69D536–6 ns Cycle Time ≥ t

KHKH

, All Inputs Toggling at CMOS Levels MCM69D536–8 ns

Vin ≤ VSS + 0.2 V or ≥ VDD – 0.2 V)

SB1

— —

100 100

Output Low Voltage (IOL = + 8.0 mA) V

— 0.4 V

Output High Voltage (IOH = – 4.0 mA) V

2.4 V

*VIL ≥ – 1.5 V for t ≤ t

KHKH

/2.

**VIH ≤ VDD + 1.0 V for t ≤ t

KHKH

/2.

CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, T

= 0 to 70°C, Periodically Sampled Rather Than 100% Tested)

Parameter Symbol Max Unit

Address and Data Input Capacitance C

6 pF

Control Pin Input Capacitance C

6 pF

Output Capacitance C

out

8 pF

Page 7

MCM69D536

MOTOROLA FAST SRAM

AC OPERA TING CONDITIONS AND CHARACTERISTICS

(VDD = 3.3 V ± 5%, TA = 0 to + 70°C, Unless Otherwise Noted)

Input Timing Measurement Reference Level 1.5 V. . . . . . . . . . . . . . .

Input Pulse Levels 0 to 3.0 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input Rise/Fall Time 3 ns. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output Timing Reference Level 1.5 V. . . . . . . . . . . . . . . . . . . . . . . . . .

Output Load Figure 1 Unless Otherwise Noted. . . . . . . . . . . . . . . . . .

READ/WRITE CYCLE TIMING (See Notes 1, 2, and 3)

MCM69D536–6 MCM69D536–8

Parameter Symbol Min Max Min Max Unit Notes

Cycle Time t

KHKH

12 — 15 — ns 1

Clock Access Time t

KHQV

— 6 — 8 ns

Clock Low Pulse Width t

KLKH

4 — 6 — ns

Clock High Pulse Width t

KHKL

4 — 6 — ns

Clock High to Data Output Active t

KHQX1

0 — 0 — ns

Clock High to Data Output Invalid t

KHQX2

2 — 2 — ns

Clock High to Data Output High–Z t

KHQZ

— 5 — 5 ns 2

Output Enable Low to Data Output Valid t

GLQV

— 6 — 8 ns

Output Enable Low to Data Output Low–Z t

GLQX

—

0 — ns

Output Enable High to Data Output High–Z t

GHQZ

— 5 — 8 ns 2

Setup Times: AWR0 – AWR14

ARD0 – ARD14

E1, E2

D0 – D35

AVKH

WVKH

PTVKH t

EVKH

DVKH

2.5 — 3 — ns 3

Hold Times: AWR0 – AWR14

ARD0 – ARD14

E1, E2

D0 – D35

KHAX

KHWX

KHPTX t

KHEX

KHDX

0.5 — 1 — ns 3 3 3 3 3

3, 4

NOTES:

1. All read and write cycles are referenced from K.

2. This parameter is sampled and not 100% tested.

3. This is a synchronous device. All synchronous inputs must meet the specified setup and hold times with stable logic levels for

ALL

rising

edges of clock (K) while the device is selected.

4. t

KHDX

minimum for Port Y only extends to 4.0 ns only for the special case when the Y– and X–address are identical on the same rising

clock edge.

OUTPUT

Z0 = 50

Ω

RL = 50

Ω

VL = 1.5 V

Figure 1. AC Test Load

Page 8

MCM69D536 8

MOTOROLA FAST SRAM

KHKH t

KLKH

KHKL

2 3 4 5 6 7 8 9

DQX

GLQV

GHQZ

KHQV

KHQX1

Q(1) Q(2) Q(3) Q(5) Q(6)

13 14 15 16 6 7 19 20

DQY

KHQZ

Q(12) Q(13) Q(14) Q(16) Q(6) Q(7)

Q(7)

GLQX

EVKH

KHEX

KHQV

PORT X

PORT Y

NOTE: E Low = E1 Low and E2 High. E High = E1 High or E2 Low.

AVKH

KHAX

READ CYCLE TIMING FROM BOTH PORTS (WX, WY, PTX, PTY HIGH)

Page 9

MCM69D536

MOTOROLA FAST SRAM

KHKH

KLKH

KHKL

DQX

D(2) D(3) D(4)

D(5) D(6)

D(8) D(9)

KHWX

PORT X

PORT Y

DQY

D(14) D(15) D(19)D(18)

WVKH

KHDX

DVKH

NOTE: E Low = E1 Low and E2 High. E High = E1 High or E2 Low.

PORT Y TAKES PRECEDENCE OVER PORT X WHEN AX = AY

AND WRITING BOTH PORTS.

WRITE CYCLE TIMING TO BOTH PORTS (PTX, PTY HIGH)

1 2 3 4 5 6 7 8 9

12 13 14

5 6 18 19 20

Page 10

MCM69D536 10

MOTOROLA FAST SRAM

KHPTX

KHKH

KLKH

KHKL

DQX

D(2) D(3) D(X) D(Y) D(6)

KHQV

PORT X

PORT Y

DQY

KHQX2

KHDX

DVKH

E Low = E1 Low and E2 High. E High = E1 High or E2 Low. NOTE: The timing diagram is valid for the opposite case as well, i.e., writing to Port Y and passing through to Port X.

PTX

PTY

D(3) D(X)

D(Y)

D(17)

KHQZ

PTVKH

WRITE TO PORT X AND PASS–THROUGH TO PORT Y (SEE NOTE)

1 2 3 4 5 6 7 8 9

12 13 14

16 17 18 19 20

Page 11

MCM69D536

MOTOROLA FAST SRAM

DQY

D(PQR) D(XYZ) Q(PQR) D(JKL) Q(JKL)

PORT Y TAKES PRECEDENCE

OVER PORT X WHEN AX = AY

AND WRITING BOTH PORTS.

KHKH

KLKH

KHKL

2 1 2 3

DQX

D(ABC) D(DEF)

PORT X

READ READ READ READ READ READ

Q(XYZ) Q(JKL)Q(PQR)

TRY TO

WRITE

TRY TO

WRITE

COMBINATION READ/WRITE WITH SAME ADDRESS ON EACH PORT

1 2 1 2 3

WRITE WRITE

READ READ READ WRITE READ READ

PORT Y

PTX = PTY = high. D(Value) = Value is the input to the data port. Q(Value) = Value is the output from the data port.

Page 12

MCM69D536 12

MOTOROLA FAST SRAM

Motorola Memory Prefix Part Number

Package (TQ = TQFP)

Full Part Numbers — MCM69D536TQ6 MCM69D536TQ8

MCM69D536TQ6R MCM69D536TQ8R

Shipping Method (R = Tape and Reel,

Blank = Rails)

Speed (6 = 6ns, 8 = 8 ns)

MCM 69D536 XX XX X

ORDERING INFORMATION

(Order by Full Part Number)

Page 13

MCM69D536

MOTOROLA FAST SRAM

TQFP PACKAGE

176 LEAD

CASE 1101–01

P ACKAGE DIMENSIONS

–M–

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DATUM PLANE –H– IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE.

4. DATUMS –L–, –M–, AND –N– TO BE DETERMINED AT DATUM PLANE –H–.

5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE –T–.

6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 (0.010) PER SIDE. DIMENSIONS A AND B DO INLCUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE –H–.

7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED 0.35 (0.014) MINIMUM SPACE BETWEEN PROTRUSION AND ADJACENT LEAD 0.07 (0.003).

PIN 1

DIM MIN MAX

MILLIMETERS

A 24.00 BSC

A1 12.00 BSC

B 24.00 BSC

B1 12.00 BSC

C ––– 1.60 C1 0.05 ––– C2 1.35 1.45

D 0.17 0.23

E 0.45 0.75 F 0.17 0.27

G 0.50 BSC

J 0.09 0.20

K 0.50 REF

P 0.25 BSC

R1 0.10 0.20

S 26.00 BSC

S1 13.00 BSC

U 0.09 0.16

V 26.00 BSC

V1 13.00 BSC

W 0.20 REF

Z 1,00 REF

0 7

1 0 ––– 2 12 REF

q q

___

X=L, M, N

–X–

VIEW Y

ROTATED 90 CLOCKWISE

IDENT

SEATING PLANE

GAGE PLANE

VIEW AA

0.25

R12X R

0.05

0.08 T

BASE

PLATING

METAL

VIEW Y

4X 44 TIPS

L–MSN

SECTION AB–AB

176 133

132

45 88

44 89

–N–

–L–

L–M NT0.20L–M NH0.20

VIEW AA

–H–

–T–

T0.08

Page 14

MCM69D536 14

MOTOROLA FAST SRAM

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