Page 1
MCM67C618
1
MOTOROLA FAST SRAM
64K x 18 Bit BurstRAM
Synchronous Fast Static RAM
With Burst Counter and Registered Outputs
The MCM67C618 is a 1,179,648 bit synchronous static random access
memory designed to provide a burstable, high–performance, secondary cache
for the i486 and Pentium microprocessors. It is organized as 65,536 words
of 18 bits, fabricated with Motorola’s high–performance silicon–gate BiCMOS
technology. The device integrates input registers, a 2–bit counter, high speed
SRAM, and high drive registered output drivers onto a single monolithic circuit
for reduced parts count implementation of cache data RAM applications. Synchronous design allows precise cycle control with the use of an external clock (K).
BiCMOS circuitry reduces the overall power consumption of the integrated
functions for greater reliability.
Addresses (A0 – A15), data inputs (D0 – D17), and all control signals except
output enable (G
) are clock (K) controlled through positive–edge–triggered non-
inverting registers.
This device contains output registers for pipeline operations. At the rising edge
of K, the RAM provides the output data from the previous cycle.
Output enable (G
) is asynchronous for maximum system design flexibility.
Burst can be initiated with either address status processor (ADSP
) or address
status cache controller (ADSC
) input pins. Subsequent burst addresses can be
generated internally by the MCM67C618 (burst sequence imitates that of the
i486) and controlled by the burst address advance (ADV
) input pin. The following
pages provide more detailed information on burst controls.
Write cycles are internally self–timed and are initiated by the rising edge of the
clock (K) input. This feature eliminates complex off–chip write pulse generation
and provides increased flexibility for incoming signals.
Dual write enables (LW
and UW) are provided to allow individually writeable
bytes. LW
controls DQ0 – DQ8 (the lower bits), while UW controls DQ9 – DQ17
(the upper bits).
This device is ideally suited for systems that require wide data bus widths and
cache memory. See Figure 2 for applications information.
• Single 5 V
± 5% Power Supply
• Fast Access Time/Fast Cycle Time = 6 ns/100 MHz, 7 ns/80 MHz, 9 ns/66 MHz
• Byte Writeable via Dual Write Enables
• Internal Input Registers (Address, Data, Control)
• Output Registers for Pipelined Applications
• Internally Self–Timed Write Cycle
• ADSP
, ADSC, and ADV Burst Control Pins
• Asynchronous Output Enable Controlled Three–State Outputs
• Common Data Inputs and Data Outputs
• 3.3 V I/O Compatible
• High Board Density 52–Lead PLCC Package
BurstRAM is a trademark of Motorola, Inc.
i486 and Pentium are trademarks of Intel Corp.
PIN ASSIGNMENTS
10
9
8
DQ9
V
CC
DQ8
12
11
15
14
13
17
16
20
19
18
37
38
34
35
36
42
43
39
40
41
45
46
44
21 22 23 24 25 26 2728 29 30 31 32 33
7 6 5 4 3 2 1 52 51 50 49 48 47
DQ6
DQ7
V
SS
DQ4
DQ5
DQ2
DQ3
V
SS
V
CC
DQ0
DQ1
V
CC
V
SS
V
SS
V
CC
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
A6A7E
UW
K
A8A9A10
LW
ADV
G
ADSC
ADSP
A15
A4A3A2
A1
A13
A14
A12
A11
V
SS
A5
A0
V
CC
All power supply and ground pins must be
connected for proper operation of the device.
PIN NAMES
A0 – A15 Address Inputs. . . . . . . . . . . . . . . .
K Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ADV Burst Address Advance. . . . . . . . . . . .
LW
Lower Byte Write Enable. . . . . . . . . . . .
UW
Upper Byte Write Enable. . . . . . . . . . . .
ADSC
Controller Address Status. . . . . . . . .
ADSP
Processor Address Status. . . . . . . . .
E
Chip Enable. . . . . . . . . . . . . . . . . . . . . . . . .
G
Output Enable. . . . . . . . . . . . . . . . . . . . . .
DQ0 – DQ17 Data Input/Output. . . . . . . . . .
V
CC
+ 5 V Power Supply. . . . . . . . . . . . . . . .
V
SS
Ground. . . . . . . . . . . . . . . . . . . . . . . . . .
NC No Connection. . . . . . . . . . . . . . . . . . . . .
Order this document
by MCM67C618/D
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
MCM67C618
FN PACKAGE
PLASTIC
CASE 778–02
REV 6
5/95
Motorola, Inc. 1994
Page 2
MCM67C618
2
MOTOROLA FAST SRAM
BLOCK DIAGRAM (See Note)
DQ0 – DQ8
CLR
Q0
Q1
A0
A1
K
ADSC
ADSP
A0 – A15
E
G
ADDRESS
REGISTER
WRITE
REGISTER
ENABLE
REGISTER
DATA–IN
REGISTERS
OUTPUT
BUFFER
64K x 18
MEMORY
ARRAY
ADV
BURST LOGIC
INTERNAL
ADDRESS
A0
′
A1
′
16
9
18
16
2
A2 – A15
A1 – A0
DQ9 – DQ17
9
9 9
9
9
BINARY
COUNTER
DATA–OUT
REGISTERS
UW
LW
NOTE: All registers are positive–edge triggered. The ADSC or ADSP signals control the duration of the burst and the start of the
next burst. When ADSP
is sampled low, any ongoing burst is interrupted and a read (independent of W and ADSC) is per-
formed using the new external address. Alternatively, an ADSP
–initiated two cycle WRITE can be performed by asserting
ADSP
and a valid address on the first cycle, then negating both ADSP and ADSC and asserting LW and/or UW with valid
data on the second cycle (see Single Write cycle in WRITE CYCLES timing diagram).
When ADSC
is sampled low (and ADSP is sampled high), any ongoing burst is interrupted and a read or write (dependent
on W
) is performed using the new external address. Chip enable (E) is sampled only when a new base address is loaded.
After the first cycle of the burst, ADV
controls subsequent burst cycles. When ADV is sampled low, the internal address is
advanced prior to the operation. When ADV
is sampled high, the internal address is not advanced, thus inserting a wait state
into the burst sequence accesses. Upon completion of a burst, the address will wrap around to its initial state. See BURST
SEQUENCE TABLE. Write refers to either or both byte write enables (LW
, UW).
BURST SEQUENCE TABLE
(See Note)
External Address A15 – A2
A1 A0
1st Burst Address A15 – A2 A1 A0
2nd Burst Address A15 – A2 A1 A0
3rd Burst Address A15 – A2 A1 A0
NOTE: The burst wraps around to its initial state upon completion.
Page 3
MCM67C618
3
MOTOROLA FAST SRAM
SYNCHRONOUS TRUTH TABLE (See Notes 1, 2, and 3)
E
ADSP ADSC ADV UW or LW K Address Used Operation
H L X X X L–H N/A Deselected
H X L X X L–H N/A Deselected
L L X X X L–H External Address Read Cycle, Begin Burst
L H L X L L–H External Address Write Cycle, Begin Burst
L H L X H L–H External Address Read Cycle, Begin Burst
X H H L L L–H Next Address Write Cycle, Continue Burst
X H H L H L–H Next Address Read Cycle, Continue Burst
X H H H L L–H Current Address Write Cycle, Suspend Burst
X H H H H L–H Current Address Read Cycle, Suspend Burst
NOTES:
1. X means Don’t Care.
2. All inputs except G
must meet setup and hold times for the low–to–high transition of clock (K).
3. Wait states are inserted by suspending burst.
ASYNCHRONOUS TRUTH TABLE (See Notes 1 and 2)
Operation
G I/O Status
Read L Data Out
Read H High–Z
Write X High–Z — Data In
Deselected X High–Z
NOTES:
1. X means Don’t Care.
2. For a write operation following a read operation, G
must be high before the input data
required setup time and held high through the input data hold time.
ABSOLUTE MAXIMUM RATINGS (Voltages Referenced to V
SS
= 0 V)
Rating Symbol Value Unit
Power Supply Voltage V
CC
– 0.5 to + 7.0 V
Voltage Relative to VSS for Any
Pin Except V
CC
Vin, V
out
– 0.5 to VCC + 0.5 V
Output Current (per I/O) I
out
± 30 mA
Power Dissipation P
D
1.6 W
Temperature Under Bias T
bias
– 10 to + 85 °C
Operating Temperature T
A
0 to +70 °C
Storage Temperature T
stg
– 55 to + 125 °C
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for
extended periods of time could affect device reliability.
ages or electric fields; however, it is advised
that normal precautions be taken to avoid
application of any voltage higher than maximum rated voltages to this high–impedance
circuit.
This BiCMOS memory circuit has been
designed to meet the dc and ac specifications
shown in the tables, after thermal equilibrium
has been established.
This device contains circuitry that will ensure
the output devices are in High–Z at power up.
This device contains circuitry to protect the
inputs against damage due to high static volt
Page 4
MCM67C618
4
MOTOROLA FAST SRAM
DC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V ± 5%, TA = 0 to + 70°C, Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS
(Voltages referenced to VSS = 0 V)
Parameter
Symbol Min Max Unit
Supply Voltage (Operating Voltage Range) V
CC
4.75 5.25 V
Input High Voltage V
IH
2.2 VCC + 0.3** V
Input Low Voltage V
IL
– 0.5* 0.8 V
*VIL (min) = – 0.5 V dc; VIL (min) = – 2.0 V ac (pulse width ≤ 20 ns) for I ≤ 20.0 mA.
**VIH (max) = VCC + 0.3 V dc; VIH (max) = VCC + 2.0 V ac (pulse width ≤ 20 ns) for I ≤ 20.0 mA.
DC CHARACTERISTICS
Parameter Symbol Min Max Unit
Input Leakage Current (All Inputs, Vin = 0 to VCC) I
lkg(I)
— ± 1.0 µA
Output Leakage Current (G = VIH) I
lkg(O)
— ± 1.0 µA
AC Supply Current (G = VIH, E = VIL, I
out
= 0 mA, All Inputs = VIL or VIH,
VIL = 0.0 V and VIH ≥ 3.0 V, Cycle Time ≥ t
KHKH
min)
I
CCA6
I
CCA7
I
CCA9
— 310
290
275
mA
AC Standby Current (E = VIH, I
out
= 0 mA, All Inputs = VIL and V
IH,
VIL = 0.0 V and VIH ≥ 3.0 V, Cycle Time ≥ t
KHKH
min)
I
SB1
— 95 mA
Output Low Voltage (IOL = + 8.0 mA) V
OL
— 0.4 V
Output High Voltage (IOH = – 4.0 mA) V
OH
2.4 3.3 V
NOTE: Good decoupling of the local power supply should always be used. DC characteristics are guaranteed for all possible i486 and Pentium
bus cycles.
CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, T
A
= 25°C, Periodically Sampled Rather Than 100% Tested)
Parameter
Symbol Typ Max Unit
Input Capacitance (All Pins Except DQ0 – DQ17) C
in
4 5 pF
Input/Output Capacitance (DQ0 – DQ17) C
I/O
6 8 pF
Page 5
MCM67C618
5
MOTOROLA FAST SRAM
AC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V ± 5% TA = 0 to + 70°C, Unless Otherwise Noted)
Input Timing Measurement Reference Level 1.5 V. . . . . . . . . . . . . . .
Input Pulse Levels 0 to 3.0 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Rise/Fall Time 3 ns. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Timing Reference Level 1.5 V. . . . . . . . . . . . . . . . . . . . . . . . . .
Output Load See Figure 1A Unless Otherwise Noted. . . . . . . . . . . .
READ/WRITE CYCLE TIMING (See Notes 1, 2, 3, and 4)
MCM67C618–6 MCM67C618–7 MCM67C618–9
Parameter Symbol Min Max Min Max Min Max Unit Notes
Cycle Time t
KHKH
10 — 12.5 — 15 — ns
Clock Access Time t
KHQV
— 6 — 7 — 9 ns 5
Output Enable to Output Valid t
GLQV
— 5 — 5 — 6 ns
Clock High to Output Active t
KHQX1
2 — 2 — 2 — ns
Clock High to Output Change t
KHQX2
2 — 2 — 2 — ns
Output Enable to Output Active t
GLQX
0 — 0 — 0 — ns
Output Disable to Q High–Z t
GHQZ
— 6 — 6 — 6 ns 6
Clock High to Q High–Z t
KHQZ
2 6 2 6 2 6 ns
Clock High Pulse Width t
KHKL
4.5 — 5 — 5 — ns
Clock Low Pulse Width t
KLKH
4.5 — 5 — 5 — ns
Setup Times: Address
Address Status
Data In
Write
Address Advance
Chip Enable
t
AVKH
t
ADSVKH
t
DVKH
t
WVKH
t
ADVVKH
t
EVKH
2.5 — 2.5 — 2.5 — ns 7
Hold Times: Address
Address Status
Data In
Write
Address Advance
Chip Enable
t
KHAX
t
KHADSX
t
KHDX
t
KHWX
t
KHADVX
t
KHEX
0.5 — 0.5 — 0.5 — ns 7
NOTES:
1. In setup and hold times, W (write) refers to either one or both byte write enables LW
and UW.
2. A read cycle is defined by UW
and LW high or ADSP low for the setup and hold times. A write cycle is defined by L W or UW low and ADSP
high for the setup and hold times.
3. All read and write cycle timings are referenced from K or G
.
4. G
is a don’t care when UW or LW is sampled low.
5. Maximum access times are guaranteed for all possible i486 and Pentium external bus cycles.
6. Transition is measured ± 500 mV from steady–state voltage with load of Figure 1B. This parameter is sampled rather than 100% tested. At
any given voltage and temperature, t
KHQZ
max is less than t
KHQZ1
min for a given device and from device to device.
7. This is a synchronous device. All addresses must meet the specified setup and hold times for
ALL
rising edges of K whenever ADSP or ADSC
is low, and the chip is selected. All other synchronous inputs must meet the specified setup and hold times for
ALL
rising edges of K when
the chip is enabled. Chip enable must be valid at each rising edge of clock for the device (when ADSP
or ADSC is low) to remain enabled.
AC TEST LOADS
Figure 1B
5 pF
+ 5 V
OUTPUT
255
Ω
480
Ω
Figure 1A
OUTPUT
Z0 = 50
Ω
RL = 50
Ω
VL = 1.5 V
Page 6
MCM67C618
6
MOTOROLA FAST SRAM
t
ADSVKH
t
KHADSX
t
KHKH
t
KHKL
t
KLKH
t
AVKH
t
KHAX
t
ADSVKH
t
KHADSX
t
WVKH
t
KHWX
t
ADVVKH
t
KHADVX
t
GLQV
t
GLQX
t
KHQV
t
KHQX2
t
EVKH
t
KHEX
t
KHQX1
t
KHQV
t
GHQZ
SINGLE READ
BURST READ
t
KHQZ
(BURST WRAPS AROUND
TO ITS INITIAL STATE)
A1 A2 A3 A4
(ADV SUSPENDS BURST)
ADSP STARTS NEW READ
A
K
ADSP
LW, UW
G
Q
ADV
E
ADSC
Q(A1) Q(A2) Q(A2 +1) Q(A2 + 2) Q(A2 + 3) Q(A2) Q(A2 +1) Q(A3)
CHIP
DESELECT
READ CYCLES
Page 7
MCM67C618
7
MOTOROLA FAST SRAM
W IS IGNORED FOR FIRST CYCLE WHEN ADSP INITIATES BURST
NEW BURST WRITEBURST WRITE
ADV SUSPENDS BURST
t
KHDX
t
DVKH
t
KHADVX
t
ADVVKH
t
KHWX
t
WVKH
ADSC STARTS NEW BURST
A3
D(A3 + 2)D(A3 + 1)D(A3)D(A2 + 3)D(A2 + 2)D(A2 + 1)D(A2) D(A2 + 1)
t
KHADSX
t
ADSVKH
t
KHKH
t
KHKL
t
KLKH
D(A1)
t
KHADSX
t
ADSVKH
t
KHAX
t
AVKH
t
KHEX
t
EVKH
SINGLE WRITEBURST READ
t
GHQZ
K
ADSP
ADSC
ADDRESS
ADV
G
DATA IN
DATA OUT
A1 A2
E
LW, UW
WRITE CYCLES
Q(An – 1) Q(An)
(WITH A SUSPENDED CYCLE)
Page 8
MCM67C618
8
MOTOROLA FAST SRAM
COMBINATION READ/WRITE CYCLES (E low, ADSC high)
t
ADVSKH
t
KHADSX
t
KHKH
t
KHKL
t
KLKH
t
AVKH
t
KHAX
t
KHWX
t
WVKH
t
ADVKH
t
KHQX1
t
KHQV
t
GHQZ
t
DVKH
t
KHDX
t
GLQX
t
KHQX2
Q(A1) Q(A3) Q(A3 + 1) Q(A3 + 2)
READ BURST READWRITE
D(A2)
A
K
ADSP
LW, UW
G
Q
ADV
D
t
KHADVX
A1 A2 A3
t
KHQV
Page 9
MCM67C618
9
MOTOROLA FAST SRAM
APPLICATION EXAMPLE
Pentium
DATA
ADDRESS
CLK
ADS
CONTROL
MCM67C618
CLOCK
ADDR
K
CACHE
CONTROL LOGIC
ADDR DATA
K
ADSC
W
G
ADV ADSP
DATA BUS
ADDRESS BUS
512K Byte Burstable, Secondary Cache Using
Four MCM67C618FN7s With a 75 MHz (bus speed) Pentium
16 72
Figure 2
Page 10
MCM67C618
10
MOTOROLA FAST SRAM
ORDERING INFORMATION
(Order by Full Part Number)
MCM
Motorola Memory Prefix
Part Number
Full Part Number — MCM67C618FN6 MCM67C618FN7 MCM67C618FN9
Speed (6 = 6 ns, 7 = 7 ns, 9 = 9 ns)
Package (FN = PLCC)
X67C618 XX
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty , representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “T ypical” parameters can and do vary in different
applications. All operating parameters, including “T ypicals” must be validated for each customer application by customer’s technical experts. Motorola does
not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in
systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of
the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such
unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless
against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part.
Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
Page 11
MCM67C618
11
MOTOROLA FAST SRAM
PACKAGE DIMENSIONS
FN PACKAGE
52–LEAD PLCC
CASE 778–02
A
B
C
E
F
G
H
J
K
R
U
V
W
X
Y
Z
G1
K1
MIN MINMAX MAX
INCHES MILLIMETERS
DIM
19.94
19.94
4.20
2.29
0.33
0.66
0.51
0.64
19.05
19.05
1.07
1.07
1.07
—
2
°
18.04
1.02
20.19
20.19
4.57
2.79
0.48
0.81
—
—
19.20
19.20
1.21
1.21
1.42
0.50
10
°
18.54
—
0.785
0.785
0.165
0.090
0.013
0.026
0.020
0.025
0.750
0.750
0.042
0.042
0.042
—
2
°
0.710
0.040
0.795
0.795
0.180
0.110
0.019
0.032
—
—
0.756
0.756
0.048
0.048
0.056
0.020
10
°
0.730
—
1.27 BSC0.050 BSC
NOTES:
1. DUE TO SPACE LIMITATION, CASE 778-02 SHALL BE
REPRESENTED BY A GENERAL (SMALLER) CASE
OUTLINE DRAWING RATHER THAN SHOWING ALL 52
LEADS.
2. DATUMS -L-, -M-, AND -N- DETERMINED WHERE TOP OF
LEAD SHOULDER EXITS PLASTIC BODY AT MOLD
PARTING LINE.
3. DIM G1, TRUE POSITION TO BE MEASURED AT DATUM -T-,
SEATING PLANE.
4. DIM R AND U DO NOT INCLUDE MOLD FLASH.
ALLOWABLE MOLD FLASH IS 0.010 (0.250) PER SIDE.
5. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M,
1982.
6. CONTROLLING DIMENSION: INCH.
7. THE PACKAGE TOP MAY BE SMALLER THAN THE
PACKAGE BOTTOM BY UP TO 0.012 (0.300). DIMENSIONS
R AND U ARE DETERMINED AT THE OUTERMOST
EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD
FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD
FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE
TOP AND BOTTOM OF THE PLASTIC BODY.
8. DIMENSION H DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION
TO BE GREATER THAN 0.037 (0.940). THE DAMBAR
INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO
BE SMALLER THAN 0.025 (0.635).
G1
VIEW S
-N-
-M-
-L-
C
E
J
G
Z
A
R
D
W
D
1
V
Y BRK
52
LEADS
ACTUAL
(NOTE 1)
52
B
U
Z
VIEW D-D
H
K1
K
VIEW S
F
G1
X
0.007 (0.180) T L
–M
SNSM
0.007 (0.180) T L
–M
SNSM
0.007 (0.180) T L
–M
SNSM
0.007 (0.180) T L
–M
SNSM
0.007 (0.180) T L
–M
SNSM
0.007 (0.180) T L
–M
SNSM
0.010 (0.250) T L
–M
SNSS
0.010 (0.250) T L
–M
SNSS
0.004 (0.100)
SEATING
PLANE
-T-
(NOTE 1)
52
Page 12
MCM67C618
12
MOTOROLA FAST SRAM
Literature Distribution Centers:
USA/EUROPE: Motorola Literature Distribution; P .O. Box 20912; Phoenix, Arizona 85036.
JAPAN: Nippon Motorola Ltd.; 4–32–1, Nishi–Gotanda, Shinagawa–ku, Tokyo 141, Japan.
ASIA PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Center, No. 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong.
MCM67C618/D
*MCM67C618/D*
◊
CODELINE TO BE PLACED HERE
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