Datasheet MCM67C618AFN7, MCM67C618AFN5 Datasheet (Motorola)

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

64K x 18 Bit BurstRAM
Synchronous Fast Static RAM

With Burst Counter and Registered Outputs

The MCM67C618A is a 1,179,648 bit synchronous static random access
memory designed to provide a burstable, high–performance, secondary cache
for the i486 and Pentium microprocessors. It is organized as 65,536 words
of 18 bits, fabricated with Motorola’s high–performance silicon–gate BiCMOS
technology. The device integrates input registers, a 2–bit counter, high speed
SRAM, and high drive registered output drivers onto a single monolithic circuit
for reduced parts count implementation of cache data RAM applications. Syn­chronous design allows precise cycle control with the use of an external clock (K).
BiCMOS circuitry reduces the overall power consumption of the integrated
functions for greater reliability .

Addresses (A0 – A15), data inputs (D0 – D17), and all control signals
except output enable (G
triggered noninverting registers.

This device contains output registers for pipeline operations. At the ris­ing edge of K, the RAM provides the output data from the previous cycle.

Output enable (G
ity.

Burst can be initiated with either address status processor (ADSP
dress status cache controller (ADSC
dresses can be generated internally by the MCM67C618A (burst
sequence imitates that of the i486 and Pentium) and controlled by the burst
address advance (ADV
tailed information on burst controls.

Write cycles are internally self–timed and are initiated by the rising edge
of the clock (K) input. This feature eliminates complex off–chip write pulse
generation and provides increased flexibility for incoming signals.

Dual write enables (L W
able bytes. LW

controls DQ0 – DQ8 (the lower bits), while UW controls

DQ9 – DQ17 (the upper bits).

This device is ideally suited for systems that require wide data bus
widths and cache memory . See Figure 2 for applications information.

• Single 5 V

± 5% Power Supply

• Fast Access Time/Fast Cycle Time = 5 ns/100 MHz, 7 ns/80 MHz

• Byte Writeable via Dual Write Enables

• Internal Input Registers (Address, Data, Control)

• Output Registers for Pipelined Applications

• Internally Self–Timed Write Cycle

• ADSP

, ADSC, and ADV Burst Control Pins

• Asynchronous Output Enable Controlled Three–State Outputs

• Common Data Inputs and Data Outputs

• 3.3 V I/O Compatible

• High Board Density 52–Lead PLCC Package

) are clock (K) controlled through positive–edge–

) is asynchronous for maximum system design flexibil-

) or ad-

) input pins. Subsequent burst ad-

) input pin. The following pages provide more de-

and UW) are provided to allow individually write-

DQ9

DQ10

V

CC

V

SS
DQ11
DQ12
DQ13
DQ14

V

SS

V

CC

DQ15
DQ16
DQ17

Order this document

by MCM67C618A/D

MCM67C618A

FN PACKAGE

PLASTIC

CASE 778–02

PIN ASSIGNMENTS

A6A7E

7 654 321525150494847

8
9

10
11
12

13
14
15
16
17
18
19
20

21 22 23 24 25 26 2728 29 30 31 3233

A5

UW

A4A3A2

LW

A1

ADSP

ADSC

A0

SS

V

PIN NAMES

A0 – A15 Address Inputs. . . . . . . . . . . . . . . .

K Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

ADV
LW
UW
ADSC
ADSP
E
G

DQ0 – DQ17 Data Input/Output. . . . . . . . . .

V

CC

V

SS

NC No Connection. . . . . . . . . . . . . . . . . . . . .

All power supply and ground pins must be
connected for proper operation of the device.

Burst Address Advance. . . . . . . . . . . .

Lower Byte Write Enable. . . . . . . . . . . .

Upper Byte Write Enable. . . . . . . . . . . .

Controller Address Status. . . . . . . . .

Processor Address Status. . . . . . . . .

ADV

CC

V

+ 5 V Power Supply. . . . . . . . . . . . . . . .

K

A15

G

A8A9A10

A13

A14

Chip Enable. . . . . . . . . . . . . . . . . . . . . . . . .

Output Enable. . . . . . . . . . . . . . . . . . . . . .

A12

Ground. . . . . . . . . . . . . . . . . . . . . . . . . .

46
45

44
43
42
41
40
39
38
37
36
35
34

A11

DQ8
DQ7
DQ6
V

CC

V

SS

DQ5
DQ4

DQ3
DQ2
V

SS

V

CC

DQ1
DQ0

BurstRAM is a trademark of Motorola, Inc.
i486 and Pentium are trademarks of Intel Corp.

REV 2
11/5/96

 Motorola, Inc. 1996

MOTOROLA FAST SRAM

MCM67C618A

1

BLOCK DIAGRAM (See Note)

ADV

K

ADSC
ADSP

A0 – A15

UW

LW

E

G

DQ0 – DQ8

DQ9 – DQ17

NOTE: All registers are positive–edge triggered. The ADSC or ADSP signals control the duration of the burst and the start of the

9
9

next burst. When ADSP

ADDRESS

REGISTER

WRITE

REGISTER

ENABLE

REGISTER

is sampled low, any ongoing burst is interrupted and a read (independent of W and ADSC) is per-

CLR

BURST LOGIC

Q0

BINARY

COUNTER

Q1

A1 – A0

16

A0

A1

2

A2 – A15

A0

′

INTERNAL
ADDRESS

16

18

DATA–IN

REGISTERS

9 9

64K x 18

MEMORY

ARRAY

9

9

DATA–OUT

REGISTERS

OUTPUT
BUFFER

formed using the new external address. Alternatively , an ADSP–initiated two cycle WRITE can be performed by asserting

and a valid address on the first cycle, then negating both ADSP and ADSC and asserting LW and/or UW with valid

ADSP
data on the second cycle (see Single Write cycle in WRITE CYCLES timing diagram).
When ADSC
on W

is sampled low (and ADSP is sampled high), any ongoing burst is interrupted and a read or write (dependent

) is performed using the new external address. Chip enable (E) is sampled only when a new base address is loaded.
After the first cycle of the burst, ADV controls subsequent burst cycles. When ADV is sampled low, the internal address is
advanced prior to the operation. When ADV

is sampled high, the internal address is not advanced, thus inserting a wait state
into the burst sequence accesses. Upon completion of a burst, the address will wrap around to its initial state. See BURST
SEQUENCE TABLE. W rite refers to either or both byte write enables (LW

, UW).

MCM67C618A
2

BURST SEQUENCE TABLE (See Note)

External Address A15 – A2
1st Burst Address A15 – A2 A1 A0
2nd Burst Address A15 – A2 A1 A0
3rd Burst Address A15 – A2 A1 A0

NOTE: The burst wraps around to its initial state upon completion.

A1 A0

MOTOROLA FAST SRAM

SYNCHRONOUS TRUTH TABLE (See Notes 1, 2, and 3)

E

H L X X X L–H N/A Deselected
H X L X X L–H N/A Deselected

X H H L L L–H Next Address Write Cycle, Continue Burst
X H H L H L–H Next Address Read Cycle, Continue Burst
X H H H L L–H Current Address Write Cycle, Suspend Burst
X H H H H L–H Current Address Read Cycle, Suspend Burst

NOTES:

1. X means Don’t Care.

2. All inputs except G

3. Wait states are inserted by suspending burst.

ADSP ADSC ADV UW or LW K Address Used Operation

L L X X X L–H External Address Read Cycle, Begin Burst
L H L X L L–H External Address Write Cycle, Begin Burst
L H L X H L–H External Address Read Cycle, Begin Burst

must meet setup and hold times for the low–to–high transition of clock (K).

ASYNCHRONOUS TRUTH TABLE (See Notes 1 and 2)

Operation

Read L Data Out
Read H High–Z
Write X High–Z — Data In

Deselected X High–Z

NOTES:

1. X means Don’t Care.

2. For a write operation following a read operation, G
required setup time and held high through the input data hold time.

G I/O Status

must be high before the input data

ABSOLUTE MAXIMUM RATINGS (Voltages Referenced to V

Rating

Power Supply Voltage V
Voltage Relative to VSS for Any

Pin Except V
Output Current (per I/O) I
Power Dissipation P
Temperature Under Bias T
Operating Temperature T
Storage Temperature T

NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are

CC

exceeded. Functional operation should be restricted to RECOMMENDED OPER­ATING CONDITIONS. Exposure to higher than recommended voltages for
extended periods of time could affect device reliability.

Symbol Value Unit

CC

Vin, V

– 0.5 to VCC + 0.5 V

out

out

D

bias

A

stg

= 0 V)

SS

– 0.5 to + 7.0 V

± 30 mA

1.6 W

– 10 to + 85 °C

0 to +70 °C

– 55 to + 125 °C

This device contains circuitry to protect the
inputs against damage due to high static volt­ages or electric fields; however, it is advised
that normal precautions be taken to avoid
application of any voltage higher than maxi­mum rated voltages to this high–impedance
circuit.

This BiCMOS memory circuit has been
designed to meet the dc and ac specifications
shown in the tables, after thermal equilibrium
has been established.

This device contains circuitry that will ensure
the output devices are in High–Z at power up.

MOTOROLA FAST SRAM

MCM67C618A

3

DC OPERA TING CONDITIONS AND CHARACTERISTICS

(VCC = 5.0 V ± 5%, TA = 0 to + 70°C, Unless Otherwise Noted)

RECOMMENDED OPERATING CONDITIONS

Parameter

Supply Voltage (Operating Voltage Range) V
Input High Voltage V
Input Low Voltage V

*VIL (min) = – 0.5 V dc; VIL (min) = – 2.0 V ac (pulse width ≤ 20 ns) for I ≤ 20.0 mA.

**VIH (max) = VCC + 0.3 V dc; VIH (max) = VCC + 2.0 V ac (pulse width ≤ 20 ns) for I ≤ 20.0 mA.

(Voltages Referenced to VSS = 0 V)

Symbol Min Max Unit

CC

IH

IL

4.75 5.25 V

2.2 VCC + 0.3** V

– 0.5* 0.8 V

DC CHARACTERISTICS

Parameter Symbol Min Max Unit

Input Leakage Current (All Inputs, Vin = 0 to VCC) I
Output Leakage Current (G = VIH) I
AC Supply Current (G = VIH, E = VIL, I

VIL = 0.0 V and VIH ≥ 3.0 V, Cycle Time ≥ t

AC Standby Current (E = VIH, I

VIL = 0.0 V and VIH ≥ 3.0 V, Cycle Time ≥ t
Output Low Voltage (IOL = + 8.0 mA) V
Output High Voltage (IOH = – 4.0 mA) V

NOTE: Good decoupling of the local power supply should always be used. DC characteristics are guaranteed for all possible i486 and Pentium

bus cycles.

out

CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, T

Input Capacitance (All Pins Except DQ0 – DQ17) C
Input/Output Capacitance (DQ0 – DQ17) C

= 0 mA, All Inputs = VIL or VIH,

out

= 0 mA, All Inputs = VIL and V

Parameter

min)

KHKH

min)

KHKH

= 25°C, Periodically Sampled Rather Than 100% Tested)

A

IH,

lkg(I)

lkg(O)

I

CCA5

I

CCA7

I

SB1

OL
OH

Symbol Typ Max Unit

in

I/O

— ± 1.0 µA
— ± 1.0 µA
— 310

290

— 95 mA

— 0.4 V

2.4 3.3 V

4 5 pF
6 8 pF

mA

MCM67C618A
4

MOTOROLA FAST SRAM

AC OPERA TING CONDITIONS AND CHARACTERISTICS

(VCC = 5.0 V ± 5% TA = 0 to + 70°C, Unless Otherwise Noted)

Input Timing Measurement Reference Level 1.5 V. . . . . . . . . . . . . . .

Input Pulse Levels 0 to 3.0 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input Rise/Fall Time 3 ns. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output Timing Reference Level 1.5 V. . . . . . . . . . . . . . . . . . . . . . . . . .

Output Load See Figure 1a Unless Otherwise Noted. . . . . . . . . . . . .

READ/WRITE CYCLE TIMING (See Notes 1, 2, 3, and 4)

MCM67C618A–5 MCM67C618A–7

Parameter Symbol Min Max Min Max Unit Notes

Cycle Time t
Clock Access Time t
Output Enable to Output Valid t
Clock High to Output Active t
Clock High to Output Change t
Output Enable to Output Active t
Output Disable to Q High–Z t
Clock High to Q High–Z t
Clock High Pulse Width t
Clock Low Pulse Width t
Setup Times: Address

Hold Times: Address

NOTES:

1. In setup and hold times, W (write) refers to either one or both byte write enables LW

2. A read cycle is defined by UW
high for the setup and hold times.

3. All read and write cycle timings are referenced from K or G

4. G

is a don’t care when UW or LW is sampled low.

5. Maximum access times are guaranteed for all possible i486 and Pentium external bus cycles.

6. Transition is measured ± 500 mV from steady–state voltage with load of Figure 1b. This parameter is sampled rather than 100% tested. At
any given voltage and temperature, t

7. This is a synchronous device. All addresses must meet the specified setup and hold times for
is low, and the chip is selected. All other synchronous inputs must meet the specified setup and hold times for
the chip is enabled. Chip enable must be valid at each rising edge of clock for the device (when ADSP

and LW high or ADSP low for the setup and hold times. A write cycle is defined by LW or UW low and ADSP

KHQZ

Address Status

Data In

Write

Address Advance

Chip Enable

Address Status

Data In

Write

Address Advance

Chip Enable

max is less than t

.

KHQZ1

KHKH
KHQV

GLQV
KHQX1
KHQX2

GLQX

GHQZ

KHQZ

KHKL
KLKH

t

AVKH

t

ADSVKH

t

DVKH
t

WVKH

t

ADVVKH

t

EVKH

t

KHAX

t

KHADSX

t

KHDX
t

KHWX

t

KHADVX

t

KHEX

min for a given device and from device to device.

10 — 12.5 — ns
— 5 — 7 ns 5
— 5 — 5 ns

0 — 0 — ns
2 — 2 — ns
0 — 0 — ns

— 6 — 6 ns 6

2 6 2 6 ns

4.5 — 5 — ns

4.5 — 5 — ns

2.5 — 2.5 — ns 7

0.5 — 0.5 — ns 7

and UW.

ALL

rising edges of K whenever ADSP or ADSC

ALL

or ADSC is low) to remain enabled.

rising edges of K when

OUTPUT

MOTOROLA FAST SRAM

Z0 = 50

(a)

Ω

RL = 50

VL = 1.5 V

Ω

Figure 1. T est Loads

OUTPUT

255

+ 5 V

480

Ω

Ω

5 pF

(b)

MCM67C618A

5

CHIP

DESELECT

ADSP ST ARTS NEW READ

KHQZ

t

(BURST WRAPS AROUND

TO ITS INITIAL STATE)

READ CYCLES

KHKH

t

KLKH

t

KHKL

t

ADSVKH

t

KHADSX

t

ADSVKH

t

A1 A2 A3 A4

KHWX

t

WVKH

t

KHADVX

t

ADVVKH

t

(ADV SUSPENDS BURST)

KHQV

KHQX2

t

t

GLQV

t

GLQX

t

KHQV

t

GHQZ

t

KHQX1

t

Q(A1) Q(A2) Q(A2 +1) Q(A2 + 2) Q(A2 + 3) Q(A2) Q(A2 +1) Q(A3)

BURST READ

SINGLE READ

K

MCM67C618A
6

KHADSX

t

ADSP

ADSC

AVKH

t

KHAX

t

KHEX

t

EVKH

t

A

LW, UW

E

ADV

G

DESELECT

Q

MOTOROLA FAST SRAM

ADSC STAR TS NEW BURST

A3

KHWX

t

WVKH

t

KHADVX

t

ADVVKH

t

KHDX

t

DVKH

t

D(A3 + 2)D(A3 + 1)D(A3)D(A2 + 3)D(A2 + 2)D(A2 + 1)D(A2) D(A2 + 1)D(A1)

NEW BURST WRITEBURST WRITE

WRITE CYCLES

KLKH

t

KHKH

t

KHKL

t

KHADSX

t

ADSVKH

t

KHADSX

t

ADSVKH

t

KHAX

t

AVKH

t

A1 A2

W IS IGNORED FOR FIRST CYCLE WHEN ADSP INITIATES BURST

KHEX

t

EVKH

t

ADV SUSPENDS BURST

GHQZ

t

(WITH A SUSPENDED CYCLE)

SINGLE WRITEBURST READ

Q(An)

Q(An – 1)

K

ADSP

MOTOROLA FAST SRAM

ADSC

A

LW, UW

E

ADV

G

D

Q

MCM67C618A

7

KHKH

t

KLKH

t

KHWX

t

WVKH

t

KHADVX

t

t

ADVVKH

KHDX

t

DVKH

t

GLQX

t

D(A2)

t

KHQV

t

t

KHQX2

GHQZ

COMBINATION READ/WRITE CYCLES (E low, ADSC high)

MCM67C618A
8

K

KHKL

t

KHADSX

t

ADSVKH

t

ADSP

AVKH

t

KHAX

t

A1 A2 A3

Q(A1) Q(A3) Q(A3 + 1) Q(A3 + 2)

READ BURST READWRITE

KHQV

t

KHQX1

t

DESELECT

A

ADV

LW, UW

G

D

Q

MOTOROLA FAST SRAM

APPLICATION EXAMPLE

ADDRESS

Pentium

CONTROL

DATA BUS

ADDRESS BUS

ADDR

CACHE

CONTROL LOGIC

ADDR DATA

K
ADSC

W
G

ADV ADSP



DATA

CLK

ADS

CLOCK

K

512K Byte Burstable, Secondary Cache Using

Four MCM67C618AFN7s With a 75 MHz (bus speed) Pentium

Figure 2

16 72

MCM67C618A

MOTOROLA FAST SRAM

MCM67C618A

9

Motorola Memory Prefix

ORDERING INFORMATION

(Order by Full Part Number)

MCM 67C618A XX X

Speed (5 = 5 ns, 7 = 7 ns)

Part Number

Package (FN = PLCC)

Full Part Numbers — MCM67C618AFN5 MCM67C618AFN7

MCM67C618A
10

MOTOROLA FAST SRAM

P ACKAGE DIMENSIONS

FN PACKAGE

52–LEAD PLCC

CASE 778–02

0.007 (0.180) T L

B

–M

SNSM

-L­LEADS

ACTUAL

(NOTE 1)

52

Z

C

(NOTE 1)

52

0.010 (0.250) T L

G1

52

-N-

Y BRK

0.007 (0.180) T L

U

–M

SNSM

D

-M-

Z

W

1

V

A

0.007 (0.180) T L

R

0.007 (0.180) T L

E

G

-T-

J

VIEW S

D

0.004 (0.100)

SEATING
PLANE

–M

–M

X

VIEW D-D

SNSM

SNSM

G1

0.010 (0.250) T L

H

0.007 (0.180) T L

–M

–M

SNSS

SNSM

K1

K

F

0.007 (0.180) T L

–M

SNSM

VIEW S

SNSS

–M

NOTES:

1. DUE TO SPACE LIMITATION, CASE 778-02 SHALL BE
REPRESENTED BY A GENERAL (SMALLER) CASE
OUTLINE DRAWING RATHER THAN SHOWING ALL 52
LEADS.

2. DATUMS -L-, -M-, AND -N- DETERMINED WHERE TOP OF
LEAD SHOULDER EXITS PLASTIC BODY AT MOLD
PARTING LINE.

3. DIM G1, TRUE POSITION TO BE MEASURED AT DATUM -T-,
SEATING PLANE.

4. DIM R AND U DO NOT INCLUDE MOLD FLASH.
ALLOWABLE MOLD FLASH IS 0.010 (0.250) PER SIDE.

5. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M,

1982.

6. CONTROLLING DIMENSION: INCH.

7. THE PACKAGE TOP MAY BE SMALLER THAN THE
PACKAGE BOTTOM BY UP TO 0.012 (0.300). DIMENSIONS
R AND U ARE DETERMINED AT THE OUTERMOST
EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD
FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD
FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE
TOP AND BOTTOM OF THE PLASTIC BODY.

8. DIMENSION H DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION
TO BE GREATER THAN 0.037 (0.940). THE DAMBAR
INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO
BE SMALLER THAN 0.025 (0.635).

INCHES MILLIMETERS

MIN MINMAX MAX

DIM

A

0.785

0.785

0.165

0.090

0.013

0.026

0.020

0.025

0.750

0.750

0.042

0.042

0.042
—

°

2

0.710

0.040

0.795

0.795

0.180

0.110

0.019

0.032
—
—

0.756

0.756

0.048

0.048

0.056

0.020
10

0.730
—

W

G1
K1

B
C
E
F
G
H
J
K
R
U
V

X
Y
Z

19.94

20.19

19.94

20.19

4.20

4.57

2.29

2.79

0.33

0.48

1.27 BSC0.050 BSC

0.66

0.81

0.51

—

0.64

—

19.05

19.20

19.05

19.20

1.07

1.21

1.07

1.21

1.07

1.42

—

0.50

°

2

18.04

1.02

°

10

18.54
—

°

MOTOROLA FAST SRAM

MCM67C618A

11

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty , representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. “T ypical” parameters which may be provided in Motorola
data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”
must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of
others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other
applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury
or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal
Opportunity/Affirmative Action Employer.

How to reach us:
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INTERNET: http://motorola.com/sps

Mfax is a trademark of Motorola, Inc.

MCM67C618A
12

◊

MOTOROLA FAST SRAM

MCM67C618A/D