Datasheet MCM67A618BFN10, MCM67A618BFN12, MCM67A618BFN15 Datasheet (Motorola)

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Advance Information

64K x 18 Bit Asynchronous/ Latched Address Fast Static RAM

The MCM67A618B is a 1,179,648 bit latched address static random access memory organized as 65,536 words of 18 bits. The device integrates a 64K x 18 SRAM core with advanced peripheral circuitry consisting of address and data input latches, active low chip enable, separate upper and lower byte write strobes, and a fast output enable. This device has increased output drive capability supported by multiple power pins.

Address, data in, and chip enable latches are provided. When latch enables (AL for address and chip enables and DL for data in) are high, the address, data in, and chip enable latches are in the transparent state. If latch enables are tied high the device can be used as an asynchronous SRAM. When latch enables are low the address, data in, and chip enable latches are in the latched state. This input latch simplifies read and write cycles by guaranteeing address and data–in hold time in a simple fashion.

Dual write enables (LW writeable bytes. LW

and UW) are provided to allow individually

controls DQ0 – DQ8 (the lower bits) while UW

controls DQ9 – DQ17 (the upper bits).

Six pair of power and ground pins have been utilized and placed on the package for maximum performance.

The MCM67A618B will be available in a 52–pin plastic leaded chip carrier (PLCC).

This device is ideally suited for systems that require wide data bus widths, cache memory , and tag RAMs.

• Single 5 V

± 5% Power Supply

• Fast Access Times: 10/12/15 ns Max

• Byte Writeable via Dual Write Enables

• Separate Data Input Latch for Simplified Write Cycles

• Address and Chip Enable Input Latches

• Common Data Inputs and Data Outputs

• Output Enable Controlled Three–State Outputs

• 3.3 V I/O Compatible

• High Board Density 52–Lead PLCC Package

DQ9

DQ10

V

CC

V DQ11 DQ12

DQ13 DQ14

V

CC

DQ15 DQ16

DQ17

MCM67A618B

FN PACKAGE

PIN ASSIGNMENT

A6A7E

8

9 10 11

SS

12 13 14 15 16

SS

17 18 19 20

A4A3A2

A5

A0 – A15 Address Inputs. . . . . . . . . . . . . . . .

AL Address Latch. . . . . . . . . . . . . . . . . . . . . .

DL Data Latch. . . . . . . . . . . . . . . . . . . . . . . . .

LW UW E G

DQ0 – DQ17 Data Input/Output. . . . . . . . . . .

V

CC

V

SS

LW

UW

A1

PIN NAMES

Order this document

by MCM67A618B/D

PLASTIC

CASE 778–02

SS

CC

AL

DL

V

A0

SS

CC

A15

V

Lower Byte Write Enable. . . . . . . . . . . .

Higher Byte Write Enable. . . . . . . . . . . .

+ 5 V Power Supply. . . . . . . . . . . . . . . .

G

A8A9A10

A13

A14

Chip Enable. . . . . . . . . . . . . . . . . . . . . . . . .

Output Enable. . . . . . . . . . . . . . . . . . . . . .

4748495051521234567

33323130292827262524232221

A12

46 45

44 43 42 41 40 39 38 37 36 35 34

Ground. . . . . . . . . . . . . . . . . . . . . . . . . . .

DQ8 DQ7 DQ6

V

CC

V

SS

DQ5 DQ4

DQ3 DQ2

V

SS

V

CC

DQ1 DQ0

A11

All power supply and ground pins must be connected for proper operation of the device.

This document contains information on a new product. Specifications and information herein are subject to change without notice.

REV 2 7/16/97

 Motorola, Inc. 1997

MOTOROLA FAST SRAM

MCM67A618B

1

BLOCK DIAGRAM

E

AL

A0 – A15

16

LATCH

16

MEMORY ARRAY

64K x 18

9 9

WRITE AMP

CONTROL

LW

UW G

18

OUTPUT BUFFER

18

DQ0 – DQ17

18

LATCH

DL

TRUTH TABLE

Supply

E LW UW AL* DL* G Mode

H X X X X X Deselected Cycle I L X X L X X Read or Write Using Latched Addresses I L X X H X X Read or Write Using Unlatched Addresses I L H H X X L Read Cycle I L H H X X H Read Cycle I L L L X L X Write Both Bytes Using Latched Data In I L L L X H X Write Both Bytes Using Unlatched Data In I L L H X X X Write Cycle, Lower Byte I L H L X X X Write Cycle, Lower Byte I

*E and Addresses satisfy the specified setup and hold times for the falling edge of AL. Data–in satisfies the specified setup

*and hold times for falling edge of DL.

NOTE: This truth table shows the application of each function. Combinations of these functions are valid.

Current

SB CC CC CC CC CC CC CC CC

I/O

Status

High–Z

— —

Data Out

High–Z High–Z High–Z High–Z High–Z

ABSOLUTE MAXIMUM RATINGS (Voltages Referenced to V

Rating

Power Supply Voltage V Voltage Relative to VSS for Any

Pin Except V Output Current (per I/O) I

Power Dissipation P Temperature Under Bias T Ambient Temperature T Storage Temperature T

NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are

CC

exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability.

Symbol Value Unit

CC

Vin, V

out

bias

stg

– 0.5 to VCC + 0.5 V

out

D

A

– 55 to + 125 °C

= 0)

SS

– 0.5 to 7.0 V

± 30

1.6 W

– 10 to + 85 °C

0 to + 70 °C

mA

MCM67A618B 2

This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high–impedance circuit.

This BiCMOS memory circuit has been designed to meet the dc and ac specifications shown in the tables, after thermal equilibrium has been established.

This device contains circuitry that will ensure the output devices are in High–Z at power up.

MOTOROLA FAST SRAM

DC OPERA TING CONDITIONS AND CHARACTERISTICS

(VCC = 5.0 V ± 5%, TA = 0 to + 70°C, Unless Otherwise Noted)

RECOMMENDED OPERATING CONDITIONS

Parameter

Supply Voltage (Operating Voltage Range) V Input High Voltage V Input Low Voltage V

*VIL (min) = – 0.5 V dc; VIL (min) = – 2.0 V ac (pulse width ≤ 20 ns) for I ≤ 20.0 mA.

**VIH (max) = VCC + 0.3 V dc; VIH (max) = VCC + 2.0 V ac (pulse width ≤ 20 ns) for I ≤ 20.0 mA.

(Voltages referenced to VSS = 0 V)

Symbol Min Max Unit

DC CHARACTERISTICS

Parameter Symbol Min Max Unit

Input Leakage Current (All Inputs, Vin = 0 to VCC) I Output Leakage Current (G = VIH) I AC Supply Current (Device Selected, All Outputs Open, MCM67A618B–10

Freq = Max, VCC = Max) MCM67A618B–12

MCM67A618B–15

CMOS Standby Supply Current (Device Deselected, Freq = 0, VDD = Max, All Inputs Static at CMOS Levels Vin ≤ VSS + 0.2 V or ≥ VCC – 0.2 V)

AC Standby Supply Current (Device Deselected, MCM67A618B–10 Freq = Max, VDD = Max, All Inputs Toggling at CMOS Levels Vin ≤ VSS + 0.2 V or ≥ VCC – 0.2 V)

Output Low Voltage (IOL = + 8.0 mA) V Output High Voltage (IOH = – 4.0 mA) V

lkg(I)

lkg(O) I

CCA

I

SB2

I

SB4

CC

IH

IL

OL OH

4.75 5.25 V

2.2

– 0.5*

— ± 1.0 µA — ± 1.0 µA — TBD mA

— TBD mA

— 0.4 V

2.4 3.3 V

VCC + 0.3**

0.8 V

V

CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, T

Characteristic

Input Capacitance C Input/Output Capacitance C

= 25°C, Periodically Sampled Rather Than 100% Tested)

A

Symbol Typ Max Unit

in

I/O

4 5 pF 6 8 pF

MOTOROLA FAST SRAM

MCM67A618B

3

AC OPERA TING CONDITIONS AND CHARACTERISTICS

(VCC = 5.0 V ± 5%, TA = 0 to + 70°C, Unless Otherwise Noted)

Input Timing Measurement Reference Level 1.5 V. . . . . . . . . . . . . . .

Input Pulse Levels 0 to 3.0 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input Rise/Fall Time 3 ns. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

ASYNCHRONOUS READ CYCLE TIMING (See Notes 1 and 2)

MCM67A618B–10 MCM67A618B–12 MCM67A618B–15

Parameter Symbol Min Max Min Max Min Max Unit Notes

Read Cycle Times t Access Times:

Output Hold from Address Change t Output Buffer Control:

Power Up Time t

NOTES:

1. AL and DL are equal to VIH for all asynchronous cycles.

2. Both Write Enable signals (L W

3. All read cycle timing is referenced from the last valid address to the first transitioning address.

4. Addresses valid prior to or coincident with E

5. Transition is measured ± 500 mV from steady–state voltage. This parameter is sampled and not 100% tested. At any given voltage and temperature, t

Address Valid to Output Valid

E

Output Enable Low to Output Valid

EHQZ

Low to Output Valid

E

Low to Output Active

G

Low to Output Active

E

High to Output High–Z

G

High to Output High–Z

is less than t

ELQX

, UW) are equal to VIH for all read cycles.

and t

GHQZ

AVAV

t

AVQV

t

ELQV

t

GLQV AXQX

t

ELQX

t

GLQX

t

EHQZ

t

GHQZ

ELICCA

going low.

is less than t

10 — 12 — 15 — ns 3

— — —

4 — 4 — 4 — ns

3 1 2 2

0 — 0 — 0 — ns

GLQX

Output Timing Reference Level 1.5 V. . . . . . . . . . . . . . . . . . . . . . . . . .

Output Load Figure 1 Unless Otherwise Noted. . . . . . . . . . . . . . . . . .

10 10

5

— —

5 5

for a given device.

— — —

3 1 2 2

12 12

— —

—

6

6 6

— —

3 1 2 2

15 15

7

— —

7 7

ns 4

ns 5

OUTPUT

Z0 = 50

Ω

VL = 1.5 V

Figure 1. AC Test Load

RL = 50

Ω

MCM67A618B 4

MOTOROLA FAST SRAM

AL (ADDRESS

LATCH)

ASYNCHRONOUS READ CYCLES

A (ADDRESS)

E

(CHIP ENABLE)

Q (DATA OUT)

G

(OUTPUT ENABLE)

LW, UW

(WRITE ENABLE)

DL

(DATA LATCH)

t

ELQX

A1 A2 A3

t

AVAV

t

ELQV

t

AXQX

t

AVQV

t

GHQZ

t

GLQV

t

GLQX

t

EHQZ

Q(A3)Q(A2)Q(A1)

MOTOROLA FAST SRAM

MCM67A618B

5

ASYNCHRONOUS WRITE CYCLE TIMING (See Notes 1, 2, and 3)

MCM67A618B–10 MCM67A618B–12 MCM67A618B–15

Parameter Symbol Min Max Min Max Min Max Unit Notes

Write Cycle Times t Setup Times: Address Valid to End of Write

Hold Times: W High to Address Invalid

Write Pulse Width: Write Pulse Width (G Low)

Output Buffer Control: W High to Output Active

NOTES:

1. In setup and hold times, W (write) refers to either one or both byte write enables LW

2. AL and DL are equal to VIH for all asynchronous cycles.

3. Both Write Enables must be equal to VIH for all address transitions.

4. All write cycle timing is referenced from the last valid address to the first transitioning address.

5. If E

goes high coincident with or before W goes high the output will remain in a high impedance state.

6. If E

goes low coincident with or after W goes low the output will remain in a high impedance state.

7. Transition is measured ± 500 mV from steady–state voltage with output load of Figure 1b. This parameter is sampled and not 100% tested. At any given voltage and temperature, t

8. If G

goes low coincident with or after W goes low the output will remain in a high impedance state.

Address Valid to E

Address Valid to W

Address Valid to E

DataValid to W

Data Valid E

E

High to Address Invalid

W

High to Data Invalid

E

High to Data Invalid

Write Pulse Width (G

Write Pulse Width Enable to End of Write Enable to End of Write

W

Low to Output High–Z

High

Low

Low High High

High)

WLQZ

AVAV

t

AVWH

t

AVEH

t

AVWL

t

AVEL

t

DVWH

t

DVEH

t

WHAX

t

EHAX

t

WHDX

t

EHDX

t

WLWH

t

WLWH

t

WLEH

t

ELWH

t

ELEH

t

WHQX

t

WLQZ

is less than t

10 — 12 — 15 — ns 4

9 9 0 0 5 5

0 0 0 0

9 8 9 9 9

3

—

WHQX

— — — — — —

— — — —

— — — — —

—

5

for a given device.

10 10

0 0 6 6

0 0 0 0

10

9 10 10 10

3

—

and UW.

— — — — — —

— — — —

— — — — —

—

13 13

0 0 7 7

0 0 0 0

13 12 13 13 13

6

3

—

— — — — — —

— — — —

— — — — —

—

ns

ns 7

9

5 6

5, 6

7, 8

MCM67A618B 6

MOTOROLA FAST SRAM

AL (ADDRESS

LATCH)

ASYNCHRONOUS WRITE CYCLE

A (ADDRESS)

(CHIP ENABLE)

(WRITE ENABLE)

(DATA LATCH)

Q (DATA OUT)

E

LW

, UW

DATA–IN

DL

A1 A2 A3

t

DVWH

t

AVAV

t

ELWH

t

WHAX

t

AVWH

t

AVWL

t

WHDX

t

WLWH

t

WHQX

t

DVEH

t

EHAX

t

WLEH

t

EHDX

D(A3)D(A2)D(A1) D(A4)

t

WLQZ

t

AVEH

t

AVEL

t

A4

ELEH

(OUTPUT ENABLE)

G

MOTOROLA FAST SRAM

MCM67A618B

7

LATCHED READ CYCLE TIMING (See Notes 1 and 2)

MCM67A618B–10 MCM67A618B–12 MCM67A618B–15

Parameter Symbol Min Max Min Max Min Max Unit Notes

Read Cycle Times t Access Times:

Setup Times:

Hold Times:

Output Hold:

Address Latch Pulse Width t Output Buffer Control:

NOTES:

1. Both Write Enable Signals (L W

2. All read cycle timing is referenced from the last valid address to the first transitioning address.

3. Addresses valid prior to or coincident with E

4. All latched inputs must meet the specified setup and hold times with stable logic levels for ALL falling edges of address latch (AL) and data latch (DL).

5. Transition is measured ± 500 mV from steady–state voltage with output load of Figure 1b. This parameter is sampled and not 100% tested. At any given voltage and temperature, t a given device.

Address Valid to Output Valid

E

Low to Output Valid

Output Enable Low to Output Valid

Address Invalid to Output Invalid

AL High to Output Valid

Address Valid to AL Low

E

Address Valid to AL High

AL Low to Address Invalid

AL High to Output Invalid

AL High to Output Active

AL High to Output High–Z

G

Valid to AL Low

E

Valid to AL High

AL Low to E

E

Low to Output Active

G

Low to Output Active

E

High to Output High–Z

Invalid

, UW) are equal to VIH for all read cycles.

t

going low.

EHQZ

t

ALHQX1

ALHQX2 t

AVAV

t

AVQV

t

ELQV

ALHQV t

GLQV

t

AVALL

t

EVALL

t

AVALH

t

EVALH

t

ALLAX

t

ALLEX

t

AXQX

ALHALL

t

ELQX

t

GLQX

t

EHQZ

ALHQZ

t

GHQZ

is less than t

10 — 12 — 15 — ns 3

— — — —

2 2 0 0

2 2

4 4

5 — 5 — 5 — ns

3 1 3 2 2 2

ELQX

and t

10 10 10

5

— — — —

— —

— — —

5 5 5

ALHQZ

— — — —

2 2 0 0

2 2

4 4

3 1 3 2 2 2

is less than t

12 12 12

6

— — — —

— —

— — —

6 6 6

ALHQX2

— — — —

2 2 0 0

3 3

4 4

3 1 3 2 2 2

and t

15 15 15

7

— — — —

— —

— — —

9 9 7

GHQZ

ns

ns 4

ns

ns 5

is less than t

GLQX

3 4

4 4

for

MCM67A618B 8

MOTOROLA FAST SRAM

AL (ADDRESS

LATCH)

t

AVALL

t

ALLAX

LATCHED READ CYCLES

t

AVALH

t

ALHALL

A (ADDRESS)

LW

G

, UW

DL

E

t

EHQZ

(CHIP ENABLE)

Q (DATA OUT)

(OUTPUT ENABLE)

(WRITE ENABLE)

(DATA LATCH)

t

EVALL

t

ALHQX2

A1 A2 A3

t

AVAV

t

AVQV

t

AXQX

t

GHQZ

t

GLQX

t

ELQX

t

ELQV

t

ALLEX

t

ALHQX1

t

GLQV

t

EVALH

t

ALHQV

t

ALHQZ

Q(A3)Q(A2)Q(A1) Q(A2)

MOTOROLA FAST SRAM

MCM67A618B

9

LATCHED WRITE CYCLE TIMING (See Notes 1, 2, and 3)

MCM67A618B–10 MCM67A618B–12 MCM67A618B–15

Parameter Symbol Min Max Min Max Min Max Unit Notes

Write Cycle Times:

Setup Times:

Hold Times:

Write Pulse Width:

Address Latch Pulse Width t Output Buffer Control:

NOTES:

1. W (write) refers to either one or both byte write enables (LW

2. A write occurs during the overlap of E

3. Both Write Enables must be equal to VIH for all address transitions.

4. All write cycle timing is referenced from the last valid address to the first transitioning address.

5. All latched inputs must meet the specified setup and hold times with stable logic levels for ALL falling edges of address latch (AL) and data latch (DL).

6. If E

7. If E

8. Transition is measured ± 500 mV from steady–state voltage with output load of Figure 1b. This parameter is sampled and not 100% tested. At any given voltage and temperature, t

9. If G

Address Valid to Address Valid

Address Valid to End of W rite Address Valid to End of W rite

AL Low to Address Invalid

Write Pulse Width (G

goes high coincident with or before W goes high the output will remain in a high impedance state. goes low coincident with or after W goes low the output will remain in a high impedance state.

goes low coincident with or after W goes low the output will remain in a high impedance state.

E

Valid to AL Low

Address Valid to AL Low

E

Valid to AL High

Address Valid to AL High

AL High to W

Address Valid to W

Address Valid to E

Data Valid to DL Low

Data Valid to W

Data Valid to E

DL High to W

DL High to E

AL Low to E

DL Low to Data Invalid

W

High to Address Invalid

E

High to Address Invalid

W

High to Data Invalid

E

High to Data Invalid

W

High to DL High

E

High to DL High

W

High to AL High

AL High to W

Write Pulse Width Enable to End of Write Enable to End of Write

W

High to Output Active

W

Low to Output High–Z

Low Low Low

High High High High

High

Low)

High)

t

AVAV

t

AVWH

t

AVEH

t

EVALL

t

AVALL

t

EVALH

t

AVALH

t

ALHWL

t

AVWL

t

AVEL

t

DVDLL

t

DVWH

t

DVEH

t

DLHWH

t

DLHEH

t

ALLEH

t

ALLAX

t

DLLDX

t

WHAX

t

EHAX

t

WHDX

t

EHDX

t

WHDLH

t

EHDLH

t

WHALH

t

ALHWH t

WLWH

t

WLWH

t

WLEH

t

ELWH

t

ELEH

ALHALL

t

WHQX

t

WLQZ

low and W low.

is less than t

WLQZ

10 — 12 — 15 — ns 4

9 9 2 2 0 0 0 0 0 2 5 5 5 5

2 2 2 0 0 0 0 0 0 0

9 9 8 9 9 9

5 — 5 — 5 — ns 4

3

—

, UW).

WHQX

— — — — — — — — — — — — — —

— — — — — — — — — —

— — — — — —

—

5

for a given device.

10 10

2 2 0 0 0 0 0 2 6 6 6 6

2 2 2 0 0 0 0 0 0 0

10 10

9 10 10 10

3 —

— — — — — — — — — — — — — —

— — — — — — — — — —

— — — — — —

—

6

13 13

13 13 12 13 13 13

—

2 2 0 0 0 0 0 2 7 7 7 7

3 3 3 0 0 0 0 0 0 0

3

— — — — — — — — — — — — —

— — — — — — — — — —

— — — — — —

—

9

ns

4 4

5

6 7

6, 7

8

8, 9

MCM67A618B 10

MOTOROLA FAST SRAM

AL (ADDRESS

LATCH)

t

ALHALL

LATCHED WRITE CYCLES

t

AVALL

t

ALLAX

A (ADDRESS)

E

(CHIP ENABLE)

LW

, UW

(WRITE ENABLE)

DATA–IN

DL

(DATA LATCH)

t

ALHWH

A1 A2 A3

t

DVWH

t

DLHWH

AVALH

WHAX

t

EVALH

t

ALHWL

t

DVDLL

t

DLLDX

t

AVWL

t

WHDX

t

EVALL

t

WLWH

t

WHQX

t

ALLEH

t

WHALH

t

DLHEH

t

DVEH

t

WHDLH

t

AVAV

t

AVEL

t

WLEH

D(A3)D(A2)D(A1) D(A4)

t

WLQZ

t

EHDX

t

AVEH

t

ELEH

t

ELWH

t

AVWH

A4

t

EHAX

t

EHDLH

Q (DATA OUT)

ORDERING INFORMATION

(Order by Full Part Number)

MCM 67A618B X XX

Motorola Memory Prefix Part Number

Full Part Numbers — MCM67A618BFN10 MCM67A618BFN12 MCM67A618BFN15

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty , representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “T ypical” parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.

Speed (10 = 10 ns, 12 = 12 ns, 15 = 15 ns)

Package (FN = PLCC)

MOTOROLA FAST SRAM

MCM67A618B

11

-L-

52

LEADS

ACTUAL

-N-

Y BRK

-M-

P ACKAGE DIMENSIONS

FN PACKAGE

52–LEAD PLCC

CASE 778–02

D

W

0.007 (0.180) T L

B

U

Z

SNSM

–M

0.007 (0.180) T L

–M

SNSM

(NOTE

1)

52

Z

C

(NOTE

1)

52

0.010 (0.250) T L

G1

1

V

A

0.007 (0.180) T L

R

0.007 (0.180) T L

E

G

-T-

J

VIEW S

D

M

0.004 (0.100)

SEATING PLANE

–M

SNS

SNSM

K1

X

VIEW D-D

K

G1

0.010 (0.250) T L

H

0.007 (0.180) T L

F

0.007 (0.180) T L

SNSS

–M

SNS

SNSM

M

VIEW S

SNSS

–M

NOTES:

1. DUE TO SPACE LIMITATION, CASE 778-02 SHALL BE REPRESENTED BY A GENERAL (SMALLER) CASE OUTLINE DRAWING RATHER THAN SHOWING ALL 52 LEADS.

2. DATUMS -L-, -M-, AND -N- DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD PARTING LINE.

3. DIM G1, TRUE POSITION TO BE MEASURED AT DATUM -T-, SEATING PLANE.

4. DIM R AND U DO NOT INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250) PER SIDE.

5. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M,

1982.

6. CONTROLLING DIMENSION: INCH.

7. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM BY UP TO 0.012 (0.300). DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY.

8. DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE GREATER THAN 0.037 (0.940). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE SMALLER THAN 0.025 (0.635).

INCHES MILLIMETERS

MIN MINMAX MAX

DIM

A

0.785

0.165

0.090

0.013

0.026

0.020

0.025

0.750

0.042

0.042 —

°

2

0.710

0.040

0.795

0.180

0.110

0.019

0.032 — —

0.756

0.048

0.056

0.020 10

0.730 —

G1 K1

B C E F G H J K R U V W X Y Z

19.94

20.19

19.94

20.19

4.20

4.57

2.29

2.79

0.33

0.48

1.27 BSC0.050 BSC

0.66

0.81

0.51

—

0.64

—

19.05

19.20

19.05

19.20

1.07

1.21

1.07

1.21

1.07

1.42

—

0.50

°

2

18.04

1.02

°

10

18.54 —

°

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