Page 1
MCM6728B
1
MOTOROLA FAST SRAM
256K x 4 Bit Fast Static Random
Access Memory
The MCM6728B is a 1,048,576 bit static random access memory organized
as 262,144 words of 4 bits. This device is fabricated using high performance silicon–gate BiCMOS technology. Static design eliminates the need for external
clocks or timing strobes.
This device meets JEDEC standards for functionality and revolutionary pinout,
and is available in a 400 mil plastic small–outline J–leaded package.
• Single 5 V ± 10% Power Supply
• Fully Static — No Clock or Timing Strobes Necessary
• All Inputs and Outputs Are TTL Compatible
• Three State Outputs
• Fast Access Times: 8, 10, 12 ns
• Center Power and I/O Pins for Reduced Noise
BLOCK DIAGRAM
ROW
DECODER
MEMORY
MATRIX
512 ROWS x 512 x 4
COLUMNS
INPUT
DATA
CONTROL
COLUMN I/O
COLUMN DECODER
A
A
A
A
A
A
A
A
DQ0
A A A A A
E
W
V
CC
V
SS
A
A A A A
DQ3
Order this document
by MCM6728B/D
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
PIN ASSIGNMENT
MCM6728B
WJ PACKAGE
400 MIL SOJ
CASE 810–03
28
27
26
25
24
23
22
21
20
19
18
17
A
A
A
A
E
A
W
A
A
A
V
CC
2
3
1
5
6
4
7
9
10
8
12
13
11
14
A
A
A
A
DQ2
A
A
DQ3
A
A
A
A
16
15
V
SS
V
CC
V
SS
DQ0
DQ1
A0 – A17 Address Input. . . . . . . . . . . . .
E
Chip Enable. . . . . . . . . . . . . . . . . . . . . .
W
Write Enable. . . . . . . . . . . . . . . . . . . .
DQ0 – DQ3 Data Input/Output. . . . . . . .
V
CC
+ 5 V Power Supply. . . . . . . . . . . .
V
SS
Ground. . . . . . . . . . . . . . . . . . . . . . .
NC No Connection. . . . . . . . . . . . . . . . .
PIN NAMES
REV 2
5/95
Motorola, Inc. 1995
Page 2
MCM6728B
2
MOTOROLA FAST SRAM
TRUTH TABLE (X = Don’t Care)
E
W Mode VCC Current Output Cycle
H X Not Selected I
SB1
, I
SB2
High–Z —
L H Read I
CCA
D
out
Read Cycle
L L Write I
CCA
High–Z Write Cycle
ABSOLUTE MAXIMUM RATINGS (See Note)
Rating
Symbol Value Unit
Power Supply Voltage V
CC
– 0.5 to + 7.0 V
Voltage Relative to VSS for Any Pin Except
V
CC
Vin, V
out
– 0.5 to VCC + 0.5 V
Output Current I
out
± 30 mA
Power Dissipation P
D
1.0 W
Temperature Under Bias T
bias
– 10 to + 85 °C
Operating Temperature T
A
0 to + 70 °C
Storage Temperature—Plastic T
stg
– 55 to + 125 °C
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for
extended periods of time could affect device reliability.
DC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V ± 10%, TA = 0 to 70°C, Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS
Parameter Symbol Min Typ Max Unit
Supply Voltage (Operating Voltage Range) V
CC
4.5 5.0 5.5 V
Input High Voltage V
IH
2.2 —
VCC + 0.3**
V
Input Low Voltage V
IL
– 0.5*
— 0.8 V
*VIL (min) = – 0.5 V dc; VIL (min) = – 2.0 V ac (pulse width ≤ 2.0 ns) for I ≤ 20.0 mA.
**VIH (max) = VCC + 0.3 V dc; VIH (max) = VCC + 2 V ac (pulse width ≤ 2.0 ns) for I ≤ 20.0 mA.
DC CHARACTERISTICS
Parameter Symbol Min Max Unit
Input Leakage Current (All Inputs, Vin = 0 to VCC) I
lkg(I)
— ± 1.0 µA
Output Leakage Current (E = VIH, V
out
= 0 to VCC) I
lkg(O)
— ± 1.0 µA
Output Low Voltage (IOL = + 8.0 mA) V
OL
— 0.4 V
Output High Voltage (IOH = – 4.0 mA) V
OH
2.4 — V
POWER SUPPLY CURRENTS
Parameter Symbol 6728B–8 6728B–10 6728B–12 Unit Notes
AC Active Supply Current (I
out
= 0 mA) (VCC = max, f = f
max
) I
CCA
195 165 155 mA 1, 2, 3
Active Quiescent Current (E = VIL, VCC = max, f = 0 MHz) I
CC2
90 90 90 mA
AC Standby Current (E = VIH, VCC = max, f = f
max
) I
SB1
60 60 60 mA 1, 2, 3
CMOS Standby Current (VCC = max, f = 0 MHz, E ≥ VCC – 0.2 V,
Vin ≤ VSS + 0.2 V, or ≥ VCC – 0.2 V)
I
SB2
20 20 20 mA
NOTES:
1. Reference AC Operating Conditions and Characteristics for input and timing (VIH/VIL, tr/tf, pulse level 0 to 3.0 V, VIH = 3.0 V).
2. All addresses transition simultaneously low (LSB) and then high (MSB).
3. Data states are all zero.
ages or electric fields; however, it is advised
that normal precautions be taken to avoid application of any voltage higher than maximum
rated voltages to these high–impedance circuits.
This BiCMOS memory circuit has been designed to meet the dc and ac specifications
shown in the tables, after thermal equilibrium
has been established. The circuit is in a test
socket or mounted on a printed circuit board
and transverse air flow of at least 500 linear feet
per minute is maintained.
This device contains circuitry to protect the
inputs against damage due to high static volt
Page 3
MCM6728B
3
MOTOROLA FAST SRAM
CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, T
A
= 25°C, Periodically Sampled Rather Than 100% Tested)
Parameter
Symbol Typ Max Unit
Address Input Capacitance C
in
— 6 pF
Control Pin Input Capacitance C
in
— 6 pF
Input/Output Capacitance C
I/O
— 8 pF
AC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V ± 10%, TA = 0 to + 70°C, Unless Otherwise Noted)
Input Timing Measurement Reference Level 1.5 V. . . . . . . . . . . . . . .
Input Pulse Levels 0 to 3.0 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Rise/Fall Time 2 ns. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Timing Measurement Reference Level 1.5 V. . . . . . . . . . . . .
Output Load See Figure 1A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
READ CYCLE TIMING (See Notes 1 and 2)
6728B–8 6728B–10 6728B–12
Parameter Symbol Min Max Min Max Min Max Unit Notes
Read Cycle Time t
AVAV
8 — 10 — 12 — ns 3
Address Access Time t
AVQV
— 8 — 10 — 12 ns
Enable Access Time t
ELQV
— 8 — 10 — 12 ns
Output Hold from Address Change t
AXQX
3 — 3 — 3 — ns
Enable Low to Output Active t
ELQX
3 — 3 — 3 — ns 4,5,6
Enable High to Output High–Z t
EHQZ
0 4 0 5 0 6 ns 4,5,6
NOTES:
1. W
is high for read cycle.
2. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycles.
3. All read cycle timings are referenced from the last valid address to the first transitioning address.
4. At any given voltage and temperature, t
EHQZ
max < t
ELQX
min, for a given device.
5. Transition is measured 200 mV from steady–state voltage with load of Figure 1B.
6. This parameter is sampled and not 100% tested.
7. Device is continuously selected (E
= VIL).
8. Addresses valid prior to or coincident with E
going low.
AC TEST LOADS
OUTPUT
Z0 = 50
Ω
RL = 50
Ω
VL = 1.5 V
Figure 1A Figure 1B
5 pF
+5 V
OUTPUT
255
Ω
480
Ω
The table of timing values shows either a
minimum or a maximum limit for each parameter. Input requirements are specified from
the external system point of view. Thus, address setup time is shown as a minimum
since the system must supply at least that
much time (even though most devices do not
require it). On the other hand, responses from
the memory are specified from the device
point of view. Thus, the access time is shown
as a maximum since the device never provides data later than that time.
TIMING LIMITS
Page 4
MCM6728B
4
MOTOROLA FAST SRAM
READ CYCLE 1 (See Note 7)
Q (DATA OUT)
A (ADDRESS)
DATA VALIDPREVIOUS DATA VALID
t
AVAV
t
AXQX
t
AVQV
READ CYCLE 2 (See Note 8)
t
EHQZ
DATA VALID
t
AVAV
t
ELQX
t
ELQV
E (CHIP ENABLE)
Q (DATA OUT)
A (ADDRESS)
t
AVQV
Page 5
MCM6728B
5
MOTOROLA FAST SRAM
WRITE CYCLE 1 (W Controlled, See Notes 1 and 2)
6728B–8 6728B–10 6728B–12
Parameter Symbol Min Max Min Max Min Max Unit Notes
Write Cycle Time t
AVAV
8 — 10 — 12 — ns 3
Address Setup Time t
AVWL
0 — 0 — 0 — ns
Address Valid to End of Write t
AVWH
8 — 9 — 10 — ns
Write Pulse Width t
WLWH
,
t
WLEH
8 — 9 — 10 — ns
Data Valid to End of Write t
DVWH
4 — 5 — 6 — ns
Data Hold Time t
WHDX
0 — 0 — 0 — ns
Write Low to Data High–Z t
WLQZ
0 4 0 5 0 6 ns 4,5,6
Write High to Output Active t
WHQX
3 — 3 — 3 — ns 4,5,6
Write Recovery Time t
WHAX
0 — 0 — 0 — ns
NOTES:
1. A write occurs during the overlap of E
low and W low.
2. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycles.
3. All write cycle timings are referenced from the last valid address to the first transitioning address.
4. Transition is measured 200 mV from steady–state voltage with load of Figure 1B.
5. This parameter is sampled and not 100% tested.
6. At any given voltage and temperature, t
WLQZ
max < t
WHQX
min both for a given device and from device to device.
WRITE CYCLE 1
HIGH–Z
DATA VALID
t
DVWH
t
AVWL
t
AVWH
t
AVAV
t
WHAX
t
WLEH
t
WHDX
t
WLQZ
t
WHQX
HIGH–Z
A (ADDRESS)
W
(WRITE ENABLE)
E (CHIP ENABLE)
Q (DATA OUT)
D (DATA IN)
t
WLWH
Page 6
MCM6728B
6
MOTOROLA FAST SRAM
WRITE CYCLE 2 (E Controlled, See Notes 1 and 2)
6728B–8 6728B–10 6728B–12
Parameter Symbol Min Max Min Max Min Max Unit Notes
Write Cycle Time t
AVAV
8 — 10 — 12 — ns 3
Address Setup Time t
AVEL
0 — 0 — 0 — ns
Address Valid to End of Write t
AVEH
7 — 8 — 9 — ns
Enable to End of Write t
ELEH
,
t
ELWH
7 — 8 — 9 — ns 4,5
Data Valid to End of Write t
DVEH
4 — 5 — 6 — ns
Data Hold Time t
EHDX
0 — 0 — 0 — ns
Write Recovery Time t
EHAX
0 — 0 — 0 — ns
NOTES:
1. A write occurs during the overlap of E
low and W low.
2. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycles.
3. All write cycle timings are referenced from the last valid address to the first transitioning address.
4. If E
goes low coincident with or after W goes low, the output will remain in a high impedance condition.
5. If E
goes high coincident with or before W goes high, the output will remain in a high impedance condition.
WRITE CYCLE 2
DATA VALID
t
AVAV
HIGH–Z
A (ADDRESS)
W
(WRITE ENABLE)
E
(CHIP ENABLE)
Q (DATA OUT)
D (DATA IN)
t
AVEL
t
AVEH
t
ELEH
t
ELWH
t
DVEH
t
EHDX
t
EHAX
Page 7
MCM6728B
7
MOTOROLA FAST SRAM
PACKAGE DIMENSIONS
28-LEAD
400 MIL SOJ
CASE 810-03
MIN MINMAX MAX
MILLIMETERS INCHES
DIM
A
B
C
D
E
F
G
H
K
L
M
N
P
R
S
0
°5°
1.27 BSC
0.64 BSC
0.050 BSC
0.025 BSC
0°5
°
18.29
10.04
3.26
0.39
2.24
0.67
—
0.89
0.76
11.05
9.15
0.77
18.54
10.28
3.75
0.50
2.48
0.81
0.50
1.14
1.14
11.30
9.65
1.01
0.720
0.395
0.128
0.015
0.088
0.026
—
0.035
0.030
0.435
0.360
0.030
0.730
0.405
0.148
0.020
0.098
0.032
0.020
0.045
0.045
0.445
0.380
0.040
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. DIMENSION A & B DO NOT INCLUDE MOLD
PROTRUSION. MOLD PROTRUSION SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
3. CONTROLLING DIMENSION: INCH.
4. DIM R TO BE DETERMINED AT DATUM -T-.
5. 810-01 AND -02 OBSOLETE, NEW STANDARD
810-03.
1
14
1528
H BRK
-A-
M
K
G
L
N
F
P
-B-
M
R
E
C
S RAD
0.10 (0.004)
SEATING
PLANE
-T-
0.25 (0.010) TSB
S
S
0.18 (0.007)MT A
S
0.18 (0.007) T B
S
D
28 PL
DETAIL Z
DETAIL Z
ORDERING INFORMATION
(Order by Full Part Number)
Motorola Memory Prefix
Part Number
Package (WJ = 400 mil SOJ)
Full Part Numbers — MCM6728BWJ8 MCM6728BWJ10 MCM6728BWJ12
MCM6728BWJ8R MCM6728BWJ10R MCM6728BWJ12R
Shipping Method (R = Tape and Reel, Blank = Rails)
Speed (8 = 8 ns, 10 = 10 ns, 12 = 12 ns)
MCM 6728B WJ XX X
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty , representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “T ypical” parameters can and do vary in different
applications. All operating parameters, including “T ypicals” must be validated for each customer application by customer’s technical experts. Motorola does
not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in
systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of
the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such
unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless
against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part.
Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
Page 8
MCM6728B
8
MOTOROLA FAST SRAM
Literature Distribution Centers:
USA: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036.
EUROPE: Motorola Ltd.; European Literature Centre; 88 T anners Drive, Blakelands, Milton Keynes, MK14 5BP, England.
JAPAN: Nippon Motorola Ltd.; 4–32–1, Nishi–Gotanda, Shinagawa–ku, Tokyo 141, Japan.
ASIA PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Center, No. 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong.
MCM6728B/D
*MCM6728B/D*
◊
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