Datasheet MCM6709BJ12R, MCM6709BJ8, MCM6709BJ10R, MCM6709BJ12, MCM6709BJ10 Datasheet (Motorola)
Page 1
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Product Preview
64K x 4 Bit Static RAM
The MCM6709B is a 262,144 bit static random access memory organized as
65,536 words of 4 bit. Static design eliminates the need for external clocks or timing strobes.
Output enable (G
creased system flexibility and eliminates bus contention problems.
The MCM6709B is available in a 300 mil, 28 lead plastic surface–mount SOJ
package.
• Single 5 V ± 10% Power Supply
• Fully Static — No Clock or Timing Strobes Necessary
• All Inputs and Outputs are TTL Compatible
• Three State Outputs
• Fast Access Times: MCM6709B–8 = 8 ns
A
A
A
A
A
A
A
A
), a special control feature of the MCM6709B, provides in-
MCM6709B–10 = 10 ns
MCM6709B–12 = 12 ns
BLOCK DIAGRAM
MEMORY MATRIX
ROW
DECODER
•
•
256 ROWS x 256 x 4
•
COLUMNS
Order this document
by MCM6709B/D
MCM6709B
J PACKAGE
300 MIL SOJ
CASE 810B–03
PIN ASSIGNMENT
NC
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
A
10
A
11
E
12
G
13
V
14
SS
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
A
A
A
A
A
A
NC
NC
DQ
DQ
DQ
DQ
W
CC
DQ
•
•
•
DQ
E
W
G
This document contains informantion on a new product under development. Motorola reserves the right to change or discontinue this product without notice.
REV 1
10/9/96
Motorola, Inc. 1996
MOTOROLA FAST SRAM
•
•
•
INPUT
DATA
CONTROL
AAAAAAAA
COLUMN I/O
COLUMN DECODER
•
•
•
A Address Inputs. . . . . . . . . . . . . . . . . .
W
G
E
DQ Data Input/Output. . . . . . . . . . . . .
V
CC
V
SS
NC No Connection. . . . . . . . . . . . . . . .
PIN NAMES
Write Enable. . . . . . . . . . . . . . . . . . .
Output Enable. . . . . . . . . . . . . . . . .
Chip Enable. . . . . . . . . . . . . . . . . . . .
+ 5 V Power Supply. . . . . . . . . .
Ground. . . . . . . . . . . . . . . . . . . . .
MCM6709B
1
Page 2
TRUTH TABLE (X = Don’t Care)
E
H X X Not Selected High–Z —
L H H Read High–Z —
L L H Read D
L X L Write D
G W Mode Output Cycle
out
in
Read Cycle
Write Cycle
ABSOLUTE MAXIMUM RATINGS (See Note)
Rating
Power Supply Voltage V
Voltage Relative to VSS for Any Pin
Except V
Output Current (per I/O) I
Power Dissipation P
Temperature Under Bias T
Operating Temperature T
Storage Temperature — Plastic T
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
CC
exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for
extended periods of time could affect device reliability.
Symbol Value Unit
CC
Vin, V
out
bias
stg
out
D
A
– 0.5 to + 7.0 V
– 0.5 to VCC + 0.5 V
± 30 mA
2.0 W
– 10 to + 85 °C
0 to + 70 °C
– 55 to + 125 °C
This device contains circuitry to protect the
inputs against damage due to high static voltages or electric fields; however, it is advised
that normal precautions be taken to avoid application of any voltage higher than maximum
rated voltages to this high–impedance circuit.
This BiCMOS memory circuit has been designed to meet the dc and ac specifications
shown in the tables, after thermal equilibrium
has been established. The circuit is in a test
socket or mounted on a printed circuit board
and transverse air flow of at least 500 linear feet
per minute is maintained.
DC OPERA TING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V ± 10%, TA = 0 to 70°C, Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS
Parameter Symbol Min Typ Max Unit
Supply Voltage (Operating Voltage Range) V
Input High Voltage V
Input Low Voltage V
*VIH (max) = VCC + 0.3 V dc; VIH (max) = VCC + 2.0 V ac (pulse width ≤ 2.0 ns) or I ≤ 30.0 mA.
** VIL (min) = – 0.5 V dc @ 30.0 mA; VIL (min) = – 2.0 V ac (pulse width ≤ 2.0 ns) or I ≤ 30.0 mA.
CC
IH
IL
DC CHARACTERISTICS
Parameter Symbol Min Max Unit
Input Leakage Current (All Inputs, Vin = 0 to VCC) I
Output Leakage Current (E = VIH, V
Output High Voltage (IOH = – 4.0 mA) V
Output Low Voltage (IOL = 8.0 mA) V
= 0 to VCC) I
out
POWER SUPPLY CURRENTS
Parameter Symbol MCM6709B–8 MCM6709B–10 MCM6709B–12 Unit Notes
AC Active Supply Current
(I
= 0 mA, VCC = max, f = f
out
AC Standby Current (E = VIH, VCC = max, f = f
CMOS Standby Current (VCC = max, f = 0 MHz,
E
≥ VCC – 0.2 V, Vin ≤ VSS, or ≥ VCC – 0.2 V)
NOTES:
1. Reference AC Operating Conditions and Characteristics for input and timing (VIH/VIL, tr/tf, pulse level 0 to 3.0 V, VIH = 3.0 V).
2. All addresses transition simultaneously low (LSB) and then high (MSB).
3. Data states are all zero.
max
)
max
) I
I
CCA
SB1
I
SB2
185 175 165 mA 1, 2, 3
120 110 105 mA 1, 2, 3
20 20 20 mA
4.5 5.0 5.5 V
2.2 — VCC + 0.3* V
– 0.5** — 0.8 V
lkg(I)
lkg(O)
OH
OL
— ± 1.0 µA
— ± 1.0 µA
2.4 — V
— 0.4 V
MCM6709B
2
MOTOROLA FAST SRAM
Page 3
CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, T
Address Input Capacitance C
Control Pin Input Capacitance (E, G, W) C
Input/Output Capacitance C
= 25°C, Periodically Sampled Rather Than 100% Tested)
A
Parameter
Symbol Max Unit
in
in
I/O
5 pF
5 pF
6 pF
AC OPERA TING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V ± 10%, TA = 0 to + 70°C, Unless Otherwise Noted)
Input Timing Measurement Reference Level 1.5 V. . . . . . . . . . . . . . .
Input Pulse Levels 0 to 3.0 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Rise/Fall Time 2 ns. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
READ CYCLES 1 AND 2 (See Notes 1 and 2)
Parameter Symbol Min Max Min Max Min Max Unit Notes
Read Cycle Time t
Address Access Time t
Chip Enable Access Time t
Output Enable Access Time t
Output Hold from Address Change t
Chip Enable Low to Output Active t
Output Enable Low to Output Active t
Chip Enable High to Output High–Z t
Output Enable High to Output High–Z t
NOTES:
1. W
is high for read cycle.
2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus
contention conditions during read and write cycles.
3. All read cycle timings are referenced from the last valid address to the first transitioning address.
4. At any given voltage and temperature, t
and from device to device.
5. Transition is measured 200 mV from steady–state voltage with load of Figure 1b.
6. This parameter is sampled and not 100% tested.
EHQZ
AVAV
AVQV
ELQV
GLQV
AXQX
ELQX
GLQX
EHQZ
GHQZ
max is less than t
Output Timing Measurement Reference Level 1.5 V. . . . . . . . . . . . .
Output Load See Figure 1a. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MCM6709B–8 MCM6709B–10 MCM6709B–12
8 — 10 — 12 — ns 3
— 8 — 10 — 12 ns
— 8 — 10 — 12 ns
— 4 — 5 — 6 ns
3 — 3 — 3 — ns
1 — 1 — 1 — ns 4, 5, 6
0 — 0 — 0 — ns 4, 5, 6
— 4.5 — 5 — 6 ns 4, 5, 6
— 4 — 5 — 6 ns 4, 5, 6
ELQX
min, and t
max is less than t
GHQZ
min, both for a given device
GLQX
OUTPUT
Z0 = 50
Ω
(a) (b)
MOTOROLA FAST SRAM
RL = 50
VL = 1.5 V
Ω
+5 V
OUTPUT
255
Ω
Figure 1. AC Test Loads
480
5 pF
TIMING LIMITS
The table of timing values shows either a
Ω
minimum or a maximum limit for each parameter. Input requirements are specified from
the external system point of view. Thus, address setup time is shown as a minimum
since the system must supply at least that
much time. On the other hand, responses
from the memory are specified from the device point of view. Thus, the access time is
shown as a maximum since the device never
provides data later than that time.
MCM6709B
3
Page 4
A (ADDRESS)
READ CYCLE 1 (See Note)
t
AXQX
t
AVAV
Q (DATA OUT)
NOTE: Device is continuously selected (E = VIL, G = VIL).
A (ADDRESS)
E
(CHIP ENABLE)
(OUTPUT ENABLE)
G
Q (DATA OUT)
t
AVQV
READ CYCLE 2 (See Note)
t
AVAV
t
ELQV
t
ELQX
t
GLQV
t
AVQV
t
GLQX
DATA VALID
DATA VALIDPREVIOUS DATA VALID
t
EHQZ
t
GHQZ
NOTE: Addresses valid prior to or coincident with E going low.
MCM6709B
4
MOTOROLA FAST SRAM
Page 5
WRITE CYCLE 1 (W Controlled, See Notes 1 and 2)
MCM6709B–8 MCM6709B–10 MCM6709B–12
Parameter Symbol Min Max Min Max Min Max Unit Notes
Write Cycle Time t
Address Setup Time t
Address Valid to End of W rite t
Write Pulse Width t
Data Valid to End of W rite t
Data Hold Time t
Write Low to Data High–Z t
Write High to Output Active t
Write Recovery Time t
NOTES:
1. A write occurs during the overlap of E
2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus
contention conditions during read and write cycles.
3. All write cycle timing is referenced from the last valid address to the first transitioning address.
4. Transition is measured 200 mV from steady state voltage with load of Figure 1b.
5. This parameter is sampled and not 100% tested.
6. At any given voltage and temperature, t
low and W low.
WLQZ
AVAV
AVWL
AVWH
WLWH
t
WLEH
DVWH
WHDX
WLQZ
WHQX
WHAX
max is less than t
8 — 10 — 12 — ns 3
0 — 0 — 0 — ns
8 — 9 — 10 — ns
8 — 9 — 10 — ns
4 — 5 — 6 — ns
0 — 0 — 0 — ns
— 4 — 5 — 6 ns 4, 5, 6
3 — 3 — 3 — ns 4, 5, 6
0 — 0 — 0 — ns
min both for a given device and from device to device.
WHQX
A (ADDRESS)
E
(CHIP ENABLE)
W
(WRITE ENABLE)
D (DATA IN)
Q (DATA OUT)
HIGH–Z
t
AVWL
WRITE CYCLE 1
t
WLQZ
t
AVAV
t
AVWH
t
WLWH
t
WLEH
HIGH–Z
t
DVWH
DATA VALID
t
WHAX
t
WHDX
t
WHQX
MOTOROLA FAST SRAM
MCM6709B
5
Page 6
WRITE CYCLE 2 (E Controlled, See Notes 1 and 2)
MCM6709B–8 MCM6709B–10 MCM6709B–12
Parameter Symbol Min Max Min Max Min Max Unit Notes
Write Cycle Time t
Address Setup Time t
Address Valid to End of W rite t
Chip Enable to End of Write t
Data Valid to End of W rite t
Data Hold Time t
Write Recovery Time t
NOTES:
1. A write occurs during the overlap of E
2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus
contention conditions during read and write cycles.
3. All write cycle timing is referenced from the last valid address to the first transitioning address.
4. If E
goes low coincident with or after W goes low, the output will remain in a high impedance condition.
5. If E
goes high coincident with or before W goes high, the output will remain in a high impedance condition.
low and W low.
AVAV
AVEL
AVEH
ELEH
t
ELWH
DVEH
EHDX
EHAX
8 — 10 — 12 — ns 3
0 — 0 — 0 — ns
8 — 9 — 10 — ns
,
7 — 8 — 9 — ns 4, 5
4 — 5 — 6 — ns
0 — 0 — 0 — ns
0 — 0 — 0 — ns
WRITE CYCLE 2
t
AVAV
A (ADDRESS)
(CHIP ENABLE)
E
W
(WRITE ENABLE)
D (DATA IN)
Q (DATA OUT)
Motorola Memory Prefix
Part Number
t
AVEL
ORDERING INFORMATION
(Order by Full Part Number)
MCM 6709B X XX X
t
AVEH
HIGH–Z
t
ELEH
t
ELWH
t
DVEH
DATA VALID
Shipping Method (R = Tape and Reel, Blank = Rails)
Speed (8 = 8 ns, 10 = 10 ns, 12 = 12 ns)
t
EHAX
t
EHDX
MCM6709B
6
Package (J = 300 mil SOJ)
Full Part Numbers — MCM6709BJ8 MCM6709BJ8R
MCM6709BJ10 MCM6709BJ10R
MCM6709BJ12 MCM6709BJ12R
MOTOROLA FAST SRAM
Page 7
P ACKAGE DIMENSIONS
J PACKAGE
300 MIL SOJ
CASE 810B-03
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
F
DETAIL Z
28
1
15
14
N
24 PL
D
0.18 (0.007)MTSA
P
-B-
S
C
E
-A-
H BRK
0.18 (0.007) TSB
L
M
G
M
0.10 (0.004)
K
DETAIL Z
SEATING PLANE
-TR
0.25 (0.010) TSB
S
S RAD
Y14.5M, 1982.
2. DIMENSION A & B DO NOT INCLUDE MOLD
PROTRUSION. MOLD PROTRUSION SHALL
NOT EXCEED 0.15 (0.006) PER SIDE.
3. CONTROLLING DIMENSION: INCH.
4. DIM R TO BE DETERMINED AT DATUM -T-.
5. 810B-01 AND -02 OBSOLETE, NEW STANDARD
810B-03.
MILLIMETERS INCHES
MIN MINMAX MAX
DIM
A
B
C
D
E
F
G
H
K
L
M
N
P
R
S
18.29
7.50
3.26
0.39
2.24
0.67
1.27 BSC
—
0.89
0.64 BSC
0
°
0.76
8.38
6.60
0.77
18.54
7.74
3.75
0.50
2.48
0.81
0.50
1.14
10
1.14
8.64
6.86
1.01
°
0.720
0.295
0.128
0.015
0.088
0.026
0.050 BSC
—
0.035
0.025 BSC
0
°
0.030
0.330
0.260
0.030
0.730
0.305
0.148
0.020
0.098
0.032
0.020
0.045
10
0.045
0.340
0.270
0.040
°
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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. “T ypical” parameters which may be provided in Motorola
data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”
must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of
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applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury
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arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
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Opportunity/Affirmative Action Employer.
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MOTOROLA FAST SRAM
◊
MCM6709B/D
MCM6709B
7
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