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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Product Preview
32K x 8 Bit Static Random
Order this document
by MCM6706CR/D
MCM6706CR
Access Memory
The MCM6706CR is a 262,144 bit static random access memory organized
as 32,768 words of 8 bits. Static design eliminates the need for external clocks
or timing strobes.
Output enable (G
flexibility and eliminates bus contention problems.
The MCM6706CR meets JEDEC standards and is available in a revolutionary
pinout 300 mil, 32–lead surface–mount SOJ package.
• Single 5.0 V ± 10% Power Supply
• Fully Static — No Clock or Timing Strobes Necessary
• All Inputs and Outputs Are TTL Compatible
• Three State Outputs
• Fast Access Times: MCM6706CR–5 = 5 ns
• Center Power and I/O Pins for Reduced Noise
A
A
A
A
A
A
A
A
A
) is a special control feature that provides increased system
MCM6706CR–5.5 = 5.5 ns
BLOCK DIAGRAM
V
CC
V
SS
ROW
DECODER
MEMORY
MATRIX
512 ROWS x 64 x 8
COLUMNS
J PACKAGE
300 MIL SOJ
CASE 857–02
PIN ASSIGNMENT
ANC
V
V
DQ
DQ
CC
SS
DQ
DQ
W
1
A
2
A
3
A
4
E
5
6
7
8
9
10
11
12
A
13
A
14
A
15
A
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A
A
A
G
DQ
DQ
V
V
DQ
DQ
A
A
A
A
NC
SS
CC
DQ0
INPUT
DATA
CONTROL
DQ7
E
W
G
This document contains information on a new product under development. Motorola reserves the right to change or discontinue this product without notice.
REV 1
10/9/96
Motorola, Inc. 1996
MOTOROLA FAST SRAM
COLUMN I/O
COLUMN DECODER
AA A
A A A
A Address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
W
E
G
DQ Data Input/Output. . . . . . . . . . . . . . . . . . .
V
CC
V
SS
NC No Connection. . . . . . . . . . . . . . . . . . . . . .
PIN NAMES
Write Enable. . . . . . . . . . . . . . . . . . . . . . . . .
Chip Enable. . . . . . . . . . . . . . . . . . . . . . . . . .
Output Enable. . . . . . . . . . . . . . . . . . . . . . .
+ 5 V Power Supply. . . . . . . . . . . . . . . .
MCM6706CR
Ground. . . . . . . . . . . . . . . . . . . . . . . . . . .
1
Page 2
TRUTH TABLE
E G W Mode I/O Pin Cycle
H X X Not Selected High–Z —
L H H Read High–Z —
L L H Read D
L X L Write D
out
in
Read Cycle
Write Cycle
ABSOLUTE MAXIMUM RATINGS (See Note)
Rating
Power Supply Voltage V
Voltage Relative to VSS for Any Pin
Except V
Output Current I
Power Dissipation P
Temperature Under Bias T
Operating Temperature T
Storage Temperature — Plastic T
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
CC
exceeded. Functional operation should be restricted to RECOMMENDED
OPERATING CONDITIONS. Exposure to higher than recommended voltages for
extended periods of time could affect device reliability .
Symbol Value Unit
CC
Vin, V
out
bias
stg
out
D
A
– 0.5 to + 7.0 V
– 0.5 to VCC + 0.5 V
± 30 mA
2.0 W
– 10 to + 85 °C
0 to + 70 °C
– 55 to + 125 °C
DC OPERA TING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V ± 10%, TA = 0 to 70°C, Unless Otherwise Noted)
This device contains circuitry to protect the
inputs against damage due to high static voltages or electric fields; however, it is advised
that normal precautions be taken to avoid application of any voltage higher than maximum
rated voltages to this high–impedance circuit.
This BiCMOS memory circuit has been designed to meet the dc and ac specifications
shown in the tables, after thermal equilibrium
has been established. The circuit is in a test
socket or mounted on a printed circuit board
and transverse air flow of at least 500 linear feet
per minute is maintained.
RECOMMENDED OPERATING CONDITIONS
Parameter Symbol Min Typ Max Unit
Supply Voltage (Operating Voltage Range) V
Input High Voltage V
Input Low Voltage V
*VIH (max) = VCC + 0.3 V dc; VIH (max) = VCC + 2.0 V ac (pulse width ≤ 2.0 ns) or I ≤ 30.0 mA.
** VIL (min) = – 0.5 V dc @ 30.0 mA; VIL (min) = – 2.0 V ac (pulse width ≤ 2.0 ns) or I ≤ 30.0 mA.
CC
IH
IL
4.5 5.0 5.5 V
2.2 —
– 0.5**
— 0.8 V
VCC + 0.3*
DC CHARACTERISTICS
Parameter Symbol Min Max Unit
Input Leakage Current (All Inputs, Vin = 0 to VCC) I
Output Leakage Current (E = VIH or G = VIH, V
Output High Voltage (IOH = – 4.0 mA) V
Output Low Voltage (IOL = + 8.0 mA) V
= 0 to VCC) I
out
lkg(I)
lkg(O)
OH
OL
— ± 1.0 µA
— ± 1.0 µA
2.4 — V
— 0.4 V
POWER SUPPLY CURRENTS
Parameter Symbol MCM6706CR–5 MCM6706CR–5.5 Unit Notes
AC Active Supply Current
(I
= 0 mA, VCC = max, f = f
out
AC Standby Current (E = VIH, VCC = max, f = f
CMOS Standby Current (VCC = max, f = 0 MHz,
E
≥ VCC – 0.2 V, Vin ≤ VSS, or ≥ VCC – 0.2 V)
NOTES:
1. Reference AC Operating Conditions and Characteristics for input and timing (VIH/VIL, tr/tf, pulse level 0 to 3.0 V, VIH = 3.0 V).
2. All addresses transition simultaneously low (LSB) and then high (MSB).
3. Data states are all zero.
max
)
) I
max
I
CCA
SB1
I
SB2
240 235 mA 1, 2, 3
120 115 mA 1, 2, 3
30 30 mA
V
MCM6706CR
2
MOTOROLA FAST SRAM
Page 3
CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, T
Address Input Capacitance C
Control Pin Input Capacitance (E, G, W) C
I/O Capacitance C
= 25°C, Periodically Sampled Rather Than 100% Tested)
A
Parameter
Symbol Max Unit
in
in
out
5 pF
6 pF
6 pF
AC OPERA TING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V ± 10%, TA = 0 to + 70°C, Unless Otherwise Noted)
Input Timing Measurement Reference Level 1.5 V. . . . . . . . . . . . . . .
Input Pulse Levels 0 to 3.0 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Rise/Fall Time 2 ns. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
READ CYCLE (See Notes 1 and 2)
Parameter Symbol Min Max Min Max Unit Notes
Read Cycle Time t
Address Access Time t
Chip Enable Access Time t
Output Enable Access Time t
Output Hold from Address Change t
Chip Enable Low to Output Active t
Chip Enable High to Output High–Z t
Output Enable Low to Output Active t
Output Enable High to Output High–Z t
NOTES:
1. W
is high for read cycle.
2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus
contention conditions during read and write cycles.
3. All read cycle timing is referenced from the last valid address to the first transitioning address.
4. At any given voltage and temperature, t
device to device.
5. Transition is measured 200 mV from steady–state voltage with load of Figure 1b.
6. This parameter is sampled and not 100% tested.
7. Device is continuously selected (E
8. Addresses valid prior to or coincident with E
= VIL, G = VIL).
AVAV
AVQV
ELQV
GLQV
AXQX
ELQX
EHQZ
GLQX
GHQZ
EHQZ
going low.
max < t
ELQX
Output Timing Measurement Reference Level 1.5 V. . . . . . . . . . . . .
Output Load See Figure 1a. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MCM6706CR–5 MCM6706CR–5.5
5 — 5.5 — ns 3
— 5 — 5.5 ns
— 5 — 5.5 ns
— 4 — 4 ns
2.0 — 2.0 — ns
3 — 3 — ns 4 ,5, 6
— 3 — 3 ns 4, 5, 6
0 — 0 — ns 4, 5, 6
— 3 — 3 ns 4, 5, 6
min, and t
GHQZ
max < t
min, both for a given device and from
GLQX
OUTPUT
Z0 = 50
Ω
(a) (b)
MOTOROLA FAST SRAM
RL = 50
VL = 1.5 V
TIMING LIMITS
+5 V
480
Ω
OUTPUT
Ω
255
Ω
5 pF
The table of timing values shows either a
minimum or a maximum limit for each parameter. Input requirements are specified from
the external system point of view. Thus, address setup time is shown as a minimum
since the system must supply at least that
much time. On the other hand, responses
from the memory are specified from the device point of view. Thus, the access time is
shown as a maximum since the device never
provides data later than that time.
Figure 1. AC Test Loads
MCM6706CR
3
Page 4
A (ADDRESS)
Q (DATA OUT)
A (ADDRESS)
E (CHIP ENABLE)
G (OUTPUT ENABLE)
Q (DATA OUT)
READ CYCLE 1 (See Note 7)
t
AXQX
PREVIOUS DATA VALID
READ CYCLE 2 (See Note 8)
t
GLQX
t
AVQV
t
AVAV
t
ELQV
t
AVQV
t
ELQX
t
GLQV
t
AVAV
DATA VALID
DATA VALID
t
EHQZ
t
GHQZ
MCM6706CR
4
MOTOROLA FAST SRAM
Page 5
WRITE CYCLE 1 (W Controlled, See Notes 1 and 2)
MCM6706CR–5 MCM6706CR–5.5
Parameter Symbol Min Max Min Max Unit Notes
Write Cycle Time t
Address Setup Time t
Address Valid to End of W rite t
Write Pulse Width t
Data Valid to End of W rite t
Data Hold Time t
Write Low to Data High–Z t
Write High to Output Active t
Write Recovery Time t
NOTES:
1. A write occurs during the overlap of E
2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus
contention conditions during read and write cycles.
3. All write cycle timings are referenced from the last valid address to the first transitioning address.
4. Transition is measured 200 mV from steady–state voltage with load of Figure 1b.
5. Parameter is sampled and not 100% tested.
6. At any given voltage and temperature, t
low and W low.
WLQZ
AVAV
AVWL
AVWH
WLWH
t
WLEH
DVWH
WHDX
WLQZ
WHQX
WHAX
max is < t
,
WHQX
5 — 5.5 — ns 3
0 — 0 — ns
6 — 6 — ns
6 — 6 — ns
3.5 — 3 — ns
0 — 0 — ns
— 3.5 — 3.5 ns 4, 5, 6
3 — 3 — ns 4, 5, 6
0 — 0 — ns
min both for a given device and from device to device.
A (ADDRESS)
E
(CHIP ENABLE)
(WRITE ENABLE)
W
D (DATA IN)
Q (DATA OUT)
HIGH–Z
t
AVWL
t
WLQZ
WRITE CYCLE 1
t
AVAV
t
AVWH
t
t
WLWH
WLEH
HIGH–Z
t
DVWH
DATA VALID
t
WHAX
t
WHDX
t
WHQX
MOTOROLA FAST SRAM
MCM6706CR
5
Page 6
WRITE CYCLE 2 (E Controlled, See Notes 1 and 2)
MCM6706CR–5 MCM6706CR–5.5
Parameter Symbol Min Max Min Max Unit Notes
Write Cycle Time t
Address Setup Time t
Address Valid to End of W rite t
Chip Enable to End of Write t
Data Valid to End of W rite t
Data Hold Time t
Write Recovery Time t
NOTES:
1. A write occurs during the overlap of E
2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus
contention conditions during read and write cycles.
3. All write cycle timing is referenced from the last valid address to the first transitioning address.
4. If E
goes low coincident with or after W goes low, the output will remain in a high impedance condition.
5. If E
goes high coincident with or before W goes high, the output will remain in a high impedance condition.
low and W low.
AVAV
AVEL
AVEH
ELWH
t
ELEH
DVEH
EHDX
EHAX
,
5 — 5.5 — ns 3
0 — 0 — ns
5 — 5.5 — ns
5 — 5.5 — ns 4,5
3 — 3 — ns
0 — 0 — ns
0 — 0 — ns
WRITE CYCLE 2
t
AVAV
A (ADDRESS)
(CHIP ENABLE)
E
W (WRITE ENABLE)
D (DATA IN)
Q (DATA OUT)
Motorola Memory Prefix
Part Number
t
AVEH
t
AVEL
ORDERING INFORMATION
(Order by Full Part Number)
MCM 6706CR X X X
HIGH–Z
t
ELEH
t
ELWH
t
DVEH
DATA VALID
Shipping Method (R = Tape and Reel, Blank = Rails)
Speed (5 = 5 ns, 5.5 = 5.5 ns)
t
EHAX
t
EHDX
MCM6706CR
6
Package (J = 300 mil SOJ)
Full Part Numbers — MCM6706CRJ5 MCM6706CRJ5R
MCM6706CRJ5.5 MCM6706CRJ5.5R
MOTOROLA FAST SRAM
Page 7
P ACKAGE DIMENSIONS
32–LEAD
300 MIL SOJ
CASE 857–02
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DATUM PLANE -X- LOCATED AT TOP OF MOLD
32 PL
F
0.17(0.007) A
1732
1
16
M
-AL
G
-X-
NOTE 3
K
DETAIL Z
0.10 (0.004)
SEATING
-T-
PLANE
NOTE 4
32 PL
D
0.17(0.007) A
P
0.17(0.007) B
-B-
R S
0.25 (0.010) B
SS
NOTE 5
SS
SS
C
E
RADIUS
SS
NOTE 5
PARTING LINE AND COINCIDENT WITH TOP OF
LEAD, WHERE LEAD EXITS BODY.
4. TO BE DETERMINED AT PLANE -X-.
5. TO BE DETERMINED AT PLANE -T-.
6. DIMENSION A & B DO NOT INCLUDE MOLD
PROTRUSION. MOLD PROTRUSION SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
7. 857-01 IS OBSOLETE, NEW STANDARD 857-02.
MILLIMETERS INCHES
MIN MINMAX MAX
DIM
20.83
A
B
C
D
E
F
G
K
L
N
P
R
S
7.50
3.26
0.41
2.24
0.67
1.27 BSC
0.89
0.64 BSC
0.76
8.38
6.60
0.77
21.08
7.74
3.75
0.50
2.48
0.81
1.14
1.14
8.64
6.86
1.01
0.820
0.295
0.128
0.016
0.088
0.026
0.050 BSC
0.035
0.025 BSC
0.030
0.330
0.260
0.030
0.830
0.305
0.148
0.020
0.098
0.032
0.045
0.045
0.340
0.270
0.040
MOTOROLA FAST SRAM
MCM6706CR
7
Page 8
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty , representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. “T ypical” parameters which may be provided in Motorola
data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”
must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of
others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other
applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury
or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal
Opportunity/Affirmative Action Employer.
How to reach us:
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INTERNET: http://Design–NET.com 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298
MCM6706CR
8
◊
MOTOROLA FAST SRAM
MCM6706CR/D
*MCM6706CR/D*
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