Datasheet MCM6706BJ12R, MCM6706BJ8, MCM6706BJ8R, MCM6706BJ10R, MCM6706BJ12 Datasheet (Motorola)

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Product Preview

32K x 8 Bit Static Random
Access Memory

The MCM6706B is a 262,144 bit static random access memory organized as
32,768 words of 8 bits. Static design eliminates the need for external clocks or
timing strobes.

Output enable (G
flexibility and eliminates bus contention problems.

The MCM6706B is available in a 300 mil, 28–lead surface–mount SOJ
package.

• Single 5.0 V ± 10% Power Supply

• Fully Static — No Clock or Timing Strobes Necessary

• All Inputs and Outputs Are TTL Compatible

• Three State Outputs

• Fast Access Times: MCM6706B–8 = 8 ns

A
A
A

A
A
A
A
A

DQ

DQ

) is a special control feature that provides increased system

MCM6706B–10 = 10 ns
MCM6706B–12 = 12 ns

BLOCK DIAGRAM

ROW

DECODER

INPUT

DATA

CONTROL

MEMORY MATRIX

(256 ROWS

128 x 8 COLUMNS)

COLUMN I/O

COLUMN DECODER

AAAAAAA

Order this document

by MCM6706B/D

MCM6706B

28

1

PIN ASSIGNMENT

A

1

A

2

A

3

A

4

A

5

A

6

A

7

AA

8

A

9

A

10

DQ

11

DQ

12

DQ

13

V

SS

14

PIN NAMES

A Address Input. . . . . . . . . . . . . . . . . . . .

W Write Enable. . . . . . . . . . . . . . . . . . . .

E Chip Enable. . . . . . . . . . . . . . . . . . . . . .

G

DQ Data Input/Output. . . . . . . . . . . . . . .

V

CC

V

SS

J PACKAGE

300 MIL SOJ

CASE 810B–03

28
27
26
25
24

23
22
21
20
19
18
17
16
15

+ 5.0 V Power Supply. . . . . . . . . .

V

CC

W
A
A
A
A
G

E
DQ
DQ

DQ
DQ
DQ

Output Enable. . . . . . . . . . . . . . . . . . .

Ground. . . . . . . . . . . . . . . . . . . . . . .

E

W

G

This document contains information on a new product under development. Motorola reserves the right to change or discontinue this product without notice.

REV 1
10/9/96

 Motorola, Inc. 1996

MOTOROLA FAST SRAM

MCM6706B

1

TRUTH TABLE (X = Don’t Care)

E

H X X Not Selected High–Z —
L H H Read High–Z —
L L H Read D
L X L Write D

G W Mode I/O Pin Cycle

out

in

Read Cycle
Write Cycle

ABSOLUTE MAXIMUM RATINGS (See Note)

Rating

Power Supply Voltage V
Voltage Relative to VSS for Any Pin

Except V
Output Current I
Power Dissipation P
Temperature Under Bias T
Operating Temperature T
Storage Temperature — Plastic T

NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are

CC

exceeded. Functional operation should be restricted to RECOMMENDED OPER­ATING CONDITIONS. Exposure to higher than recommended voltages for
extended periods of time could affect device reliability.

Symbol Value Unit

– 0.5 to + 7.0 V

– 0.5 to VCC + 0.5 V

± 30 mA

2.0 W

– 10 to + 85 °C

0 to + 70 °C

– 55 to + 125 °C

Vin, V

out

bias

CC

out

D

A

stg

DC OPERA TING CONDITIONS AND CHARACTERISTICS

(VCC = 5.0 V ± 10%, TA = 0 to 70°C, Unless Otherwise Noted)

This device contains circuitry to protect the
inputs against damage due to high static volt­ages or electric fields; however, it is advised
that normal precautions be taken to avoid appli­cation of any voltage higher than maximum
rated voltages to this high–impedance circuit.

This BiCMOS memory circuit has been de­signed to meet the dc and ac specifications
shown in the tables, after thermal equilibrium
has been established. The circuit is in a test
socket or mounted on a printed circuit board
and transverse air flow of at least 500 linear feet
per minute is maintained.

RECOMMENDED OPERATING CONDITIONS

Parameter Symbol Min Typ Max Unit

Supply Voltage (Operating Voltage Range) V
Input High Voltage V
Input Low Voltage V
*VIH (max) = VCC + 0.3 V dc; VIH (max) = VCC + 2.0 V ac (pulse width ≤ 2.0 ns) or I ≤ 30.0 mA.

** VIL (min) = – 0.5 V dc @ 30.0 mA; VIL (min) = – 2.0 V ac (pulse width ≤ 2.0 ns) or I ≤ 30.0 mA.

CC

IH

IL

4.5 5.0 5.5 V

2.2 —

– 0.5**

— 0.8 V

DC CHARACTERISTICS

Parameter Symbol Min Max Unit

Input Leakage Current (All Inputs, Vin = 0 to VCC) I
Output Leakage Current (E = VIH or G = VIH, V
Output High Voltage (IOH = – 4.0 mA) V
Output Low Voltage (IOL = + 8.0 mA) V

= 0 to VCC) I

out

lkg(I)

lkg(O)

OH

OL

— ± 1.0 µA
— ± 1.0 µA

2.4 — V
— 0.4 V

POWER SUPPLY CURRENTS

Parameter Symbol 6706B–8 6706B–10 6706B–12 Unit Notes

AC Active Supply Current

(I

= 0 mA, VCC = max, f = f

out

AC Standby Current (E = VIH, VCC = max, f = f
CMOS Standby Current (VCC = max, f = 0 MHz,

E

≥ VCC – 0.2 V, Vin ≤ VSS, or ≥ VCC – 0.2 V)

NOTES:

1. Reference AC Operating Conditions and Characteristics for input and timing (VIH/VIL, tr/tf, pulse level 0 to 3 V, VIH = 3 V).

2. All addresses transition simultaneously low (LSB) and then high (MSB).

3. Data states are all zero.

max

)

) I

max

I

CCA

SB1

I

SB2

195 185 175 mA 1, 2, 3

75 70 65 mA 1, 2, 3
20 20 20 mA

VCC + 0.3*

V

MCM6706B
2

MOTOROLA FAST SRAM

CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, T

Address Input Capacitance C
Control Pin Input Capacitance (E, G, W) C
I/O Capacitance C

= 25°C, Periodically Sampled Rather Than 100% Tested)

A

Parameter

Symbol Max Unit

in
in

out

5 pF
6 pF
6 pF

AC OPERA TING CONDITIONS AND CHARACTERISTICS

(VCC = 5.0 V ± 10%, TA = 0 to + 70°C, Unless Otherwise Noted)

Input Timing Measurement Reference Level 1.5 V. . . . . . . . . . . . . . .

Input Pulse Levels 0 to 3.0 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input Rise/Fall Time 2 ns. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

READ CYCLE (See Notes 1 and 2)

Parameter Symbol Min Max Min Max Min Max Unit Notes

Read Cycle Time t
Address Access Time t
Chip Enable Access Time t
Output Enable Access Time t
Output Hold from Address Change t
Chip Enable Low to Output Active t
Chip Enable High to Output High–Z t
Output Enable Low to Output Active t
Output Enable High to Output High–Z t

NOTES:

1. W

is high for read cycle.

2. Product sensitivites to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus
contention conditions during read and write cycles.

3. All read cycle timing is referenced from the last valid address to the first transitioning address.

4. At any given voltage and temperature, t
device to device.

5. Transition is measured 200 mV from steady–state voltage with load of Figure 1b.

6. This parameter is sampled and not 100% tested.

7. Device is continuously selected (E

8. Addresses valid prior to or coincident with E

EHQZ

= VIL, G = VIL).

going low.

AVAV
AVQV
ELQV
GLQV
AXQX
ELQX
EHQZ
GLQX

GHQZ

max < t

ELQX

Output Timing Measurement Reference Level 1.5 V. . . . . . . . . . . . .

Output Load See Figure 1a. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MCM6706B–8 MCM6706B–10 MCM6706B–12

8 — 10 — 12 — ns 3
— 8 — 10 — 12 ns
— 8 — 10 — 12 ns
— 4 — 5 — 6 ns

3 — 3 — 3 — ns

1 — 1 — 1 — ns 4 ,5, 6
— 4.5 — 5 — 6 ns 4, 5, 6

0 — 0 — 0 — ns 4, 5, 6
— 4 — 5 — 6 ns 4, 5, 6

min, and t

GHQZ

max < t

min, both for a given device and from

GLQX

OUTPUT

Z0 = 50

Ω

(a) (b)

MOTOROLA FAST SRAM

RL = 50

VL = 1.5 V

Ω

+5 V

OUTPUT

255

Ω

Figure 1. AC Test Loads

480

5 pF

TIMING LIMITS

The table of timing values shows either a

Ω

minimum or a maximum limit for each param­eter. Input requirements are specified from
the external system point of view. Thus, ad­dress setup time is shown as a minimum
since the system must supply at least that
much time. On the other hand, responses
from the memory are specified from the de­vice point of view. Thus, the access time is
shown as a maximum since the device never
provides data later than that time.

MCM6706B

3

A (ADDRESS)

Q (DATA OUT)

A (ADDRESS)

E (CHIP ENABLE)

G (OUTPUT ENABLE)

Q (DATA OUT)

READ CYCLE 1 (See Note 7)

t

AXQX

PREVIOUS DATA VALID

READ CYCLE 2 (See Note 8)

t

GLQX

t

AVQV

t

AVAV

t

ELQV

t

AVQV

t

ELQX

t

GLQV

t

AVAV

DATA VALID

DATA VALID

t

EHQZ

t

GHQZ

MCM6706B
4

MOTOROLA FAST SRAM

WRITE CYCLE 1 (W Controlled, See Notes 1 and 2)

MCM6706B–8 MCM6706B–10 MCM6706B–12

Parameter Symbol Min Max Min Max Min Max Unit Notes

Write Cycle Time t
Address Setup Time t
Address Valid to End of W rite t
Write Pulse Width t

Data Valid to End of W rite t
Data Hold Time t
Write Low to Data High–Z t
Wirte High to Output Active t
Write Recovery Time t

NOTES:

1. A write occurs during the overlap of E

2. Product sensitivites to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus
contention conditions during read and write cycles.

3. All write cycle timings are referenced from the last valid address to the first transitioning address.

4. Transition is measured 200 mV from steady–state voltage with load of Figure 1b.

5. Parameter is sampled and not 100% tested.

6. At any given voltage and temperature, t

low and W low.

WLQZ

AVAV
AVWL
AVWH

WLWH
t

WLEH

DVWH
WHDX

WLQZ

WHQX
WHAX

max is < t

WHQX

8 — 10 — 12 — ns 3
0 — 0 — 0 — ns
8 — 9 — 10 — ns

,

8 — 9 — 10 — ns

4 — 5 — 6 — ns
0 — 0 — 0 — ns

— 4 — 5 — 6 ns 4, 5, 6

3 — 3 — 3 — ns 4, 5, 6
0 — 0 — 0 — ns

min both for a given device and from device to device.

A (ADDRESS)

E

(CHIP ENABLE)

(WRITE ENABLE)

W

D (DATA IN)

Q (DATA OUT)

HIGH–Z

t

AVWL

t

WLQZ

WRITE CYCLE 1

t

AVAV

t

AVWH

t

t

WLWH

WLEH

HIGH–Z

t

DVWH

DATA VALID

t

WHAX

t

WHDX

t

WHQX

MOTOROLA FAST SRAM

MCM6706B

5

WRITE CYCLE 2 (E Controlled, See Notes 1 and 2)

MCM6706B–8 MCM6706B–10 MCM6706B–12

Parameter Symbol Min Max Min Max Min Max Unit Notes

Write Cycle Time t
Address Setup Time t
Address Valid to End of W rite t
Chip Enable to End of Write t

Data Valid to End of W rite t
Data Hold Time t
Write Recovery Time t

NOTES:

1. A write occurs during the overlap of E

2. Product sensitivites to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus
contention conditions during read and write cycles.

3. All write cycle timing is referenced from the last valid address to the first transitioning address.

4. If E

goes low coincident with or after W goes low, the output will remain in a high impedance condition.

5. If E

goes high coincident with or before W goes high, the output will remain in a high impedance condition.

low and W low.

AVAV
AVEL
AVEH

ELWH

t

ELEH
DVEH
EHDX

EHAX

8 — 10 — 12 — ns 3
0 — 0 — 0 — ns
8 — 9 — 10 — ns

,

7 — 8 — 9 — ns 4,5

4 — 5 — 6 — ns
0 — 0 — 0 — ns
0 — 0 — 0 — ns

WRITE CYCLE 2

t

AVAV

A (ADDRESS)

(CHIP ENABLE)

E

W (WRITE ENABLE)

D (DATA IN)

Q (DATA OUT)

t

AVEL

t

AVEH

HIGH–Z

t

ELEH

t

ELWH

t

DVEH

DATA VALID

t

EHAX

t

EHDX

MCM6706B
6

MOTOROLA FAST SRAM

P ACKAGE DIMENSIONS

J PACKAGE

300 MIL SOJ

CASE 810B–03

F

DETAIL Z

28

1

15

14

N

24 PL

D

0.18 (0.007)MTSA

-A-

H BRK

0.18 (0.007) TSB

L

M

G

M

S

P

-B-

E

0.10 (0.004)

K

DETAIL Z

SEATING PLANE

-T­R

0.25 (0.010) TSB

S

S RAD

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. DIMENSION A & B DO NOT INCLUDE MOLD
PROTRUSION. MOLD PROTRUSION SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.

3. CONTROLLING DIMENSION: INCH.

4. DIM R TO BE DETERMINED AT DATUM -T-.

MILLIMETERS INCHES

MIN MINMAX MAX

DIM

18.29

7.50

3.26

0.39

2.24

0.67

1.27 BSC

—

0.89

0.64 BSC

0

°

0.76

8.38

6.60

0.77

18.54

7.74

3.75

0.50

2.48

0.81

0.50

1.14
10

1.14

8.64

6.86

1.01

°

A
B
C
D
E
F
G

C

H
K
L
M
N
P
R
S

0.720

0.295

0.128

0.015

0.088

0.026

0.050 BSC
—

0.035

0.025 BSC

0

°

0.030

0.330

0.260

0.030

0.730

0.305

0.148

0.020

0.098

0.032

0.020

0.045

10

0.045

0.340

0.270

0.040

°

ORDERING INFORMATION

(Order by Full Part Number)

MCM 6706B X XX X

Motorola Memory Prefix
Part Number

Full Part Numbers — MCM6706BJ8 MCM6706BJ8R

MCM6706BJ10 MCM6706BJ10R
MCM6706BJ12 MCM6706BJ12R

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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. “T ypical” parameters which may be provided in Motorola
data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”
must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of
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arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
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Opportunity/Affirmative Action Employer.

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Speed (8 = 8 ns, 10 = 10 ns, 12 = 12 ns)
Package (J = 300 mil SOJ)

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MOTOROLA FAST SRAM

◊

MCM6706B/D

MCM6706B

7