Datasheet MCM64PC32SG66, MCM64PC64SG66 Datasheet (Motorola)

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Page 1

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Advance Information

256K/512K Pipelined BurstRAM

Order this document

by MCM64PC32/D

MCM64PC32 MCM64PC64

Secondary Cache Module for Pentium

The MCM64PC32 (256K) and MCM64PC64 (512K) are designed to provide a burstable, high performance, L2 cache for the Pentium microprocessor in conjunction with Intel’s Triton II chip set. The MCM64PC32 is configured as 32K x 64 bits and the MCM64PC64 is configured as 64K x 64 bits. Both are packaged in a 160 pin card edge memory module. Each module uses Motorola’s 3.3 V 32K x 32 BurstRAMs and one Motorola 3.3 V 32K x 8 FSRAM for the tag RAM.

Bursts can be initiated with either address status processor (ADSP address status (CADS the BurstRAM by the cache burst advance (CADV

Write cycles are internally self timed and are initiated by the rising edge of the clock (CLK0) input. Eight write enables are provided for byte write control.

PD0 – PD3 map into the Triton II chip set for auto–configuration of the cache control.

• Pentium–Style Burst Counter on Chip

• Pipelined Data Out

• 160 Pin Card Edge Module

• Address Pipeline Supported by ADSP

• All Cache Data and Tag I/Os are TTL Compatible

• Three State Outputs

• Byte Write Capability

• Fast Module Clock Rate: 66 MHz

• Fast SRAM Access Times:15 ns for Tag RAM

• One–Cycle Deselect Data RAMs

• Decoupling Capacitors for Each Fast Static RAM

• High Quality Multi–Layer FR4 PWB with Separate Power and Ground

Planes

• Single 3.3 V +10%, – 5% Power Supply

• Burndy Connector, Part Number: CELP2X80SC3Z48

• Intel COAST 3.0 Option III Compliant

• Burst Order Select (BOSEL) Option

). Subsequent burst addresses are generated internal to

) input pin.

Disabled with Ex

8 ns for Data RAMs

) or cache

160–LEAD CARD EDGE

CASE TBD, TOP VIEW

42 43

BurstRAM is a trademark of Motorola. Pentium is a trademark of Intel Corp.

This document contains information on a new product. Motorola reserves the right to change or discontinue this product without notice.

5/20/96

 Motorola, Inc. 1996

MOTOROLA FAST SRAM

MCM64PC32•MCM64PC64

Page 2

TIO0 – TIO7

TWE

A3 – A18

MCM64PC32 BLOCK DIAGRAM

32K x 8

DQ0 – DQ7

W A0 – A12

A13 A14 G

ECS2

ECS1

ADSP CADS CADV

CLK0

BWE

GWE

CWE0 – CWE3

CWE4 – CWE7

32K x 32

SA0 – SA14 ADSP

ADSC ADV

K G

SW SGW

SBa – SBd

DQ0 – DQ31

32K x 32

SA0 – SA14 ADSP

ADSC ADV

K G

SW SGW

SBa – SBd

DQ0 – DQ31

SE1 SE2

SE3

LBO

SE1 SE2

SE3

LBO

4.7 k

CCS V

Ω

BOSEL

DQ0 – DQ31

DQ32 – DQ63

MCM64PC32•MCM64PC64 2

MOTOROLA FAST SRAM

Page 3

TIO0 – TIO7

TWE

A3 – A17

A18

CCS

MCM64PC64 BLOCK DIAGRAM

32K x 8

DQ0 – DQ7

W A0 – A12

A13 A14 G

ADSP CADS CADV

CLK0

BWE

GWE

CWE0 –

CWE3

CLK1

CWE4 – CWE7

32K x 32

SA0 – SA14 ADSP

ADSC ADV

K G

SW SGW

SBa – SBd

DQ0 – DQ31

32K x 32

SA0 – SA14 ADSP

ADSC ADV

K G

SW SGW

SBa – SBd

DQ0 – DQ31

SE1 SE2

SE3

LBO

SE1 SE2

SE3

LBO

32K x 32

SA0 – SA14 ADSP

ADSC ADV

K G

SW SGW

SBa – SBd

DQ0 – DQ31

32K x 32

SA0 – SA14 ADSP

ADSC ADV

K G

SW SGW

SBa – SBd

DQ0 – DQ31

SE1 SE2

SE3

LBO

SE1 SE2

SE3

LBO

DQ0 – DQ31

4.7 k

BOSEL

DQ32 – DQ63

Ω

MOTOROLA FAST SRAM

MCM64PC32•MCM64PC64

Page 4

PIN ASSIGNMENT 160–LEAD CARD EDGE MODULE (DIMM)

Pin Name Pin Name Pin Name Pin Name Pin Name

1 V 2 TIO0 34 PD3 66 DQ20 98 NC 130 DQ45 3 TIO2 35 V 4 TIO6 36 CLK1 68 VDD3 100 RSVD 132 VDD5 5 TIO4 37 V 6 NC 38 DQ62 70 DQ14 102 A6 134 DQ39 7 VDD3 39 VDD3 71 DQ12 103 A8 135 DQ37 8 TWE 40 DQ60 72 V

9 CADS 41 DQ58 73 DQ10 105 VDD5 137 DQ35 10 V 11 CWE4 43 V 12 CWE6 44 DQ54 76 VDD3 108 A9 140 VDD5 13 CWE0 45 DQ52 77 DQ4 109 A14 141 DQ29 14 CWE2 46 DQ50 78 DQ2 110 A15 142 DQ27 15 VDD3 47 DQ48 79 DQ0 111 RSVD 143 DQ25 16 CCS 48 V 17 GWE 49 DQ46 81 V 18 BWE 50 DQ44 82 TIO1 114 BOSEL 146 DQ21 19 V 20 A3 52 VDD3 84 TIO5 116 CLK0 148 VDD5 21 A7 53 DQ40 85 TIO3 117 V 22 A5 54 DQ38 86 NC 118 DQ63 150 DQ15 23 A11 55 DQ36 87 VDD5 119 VDD5 151 DQ13 24 A16 56 V 25 VDD3 57 DQ34 89 CADV 121 DQ59 153 DQ11 26 A18 58 DQ32 90 V 27 V 28 A12 60 VDD3 92 CWE5 124 DQ55 156 VDD5 29 A13 61 DQ28 93 CWE7 125 DQ53 157 DQ5 30 ADSP 62 DQ26 94 CWE1 126 DQ51 158 DQ3 31 ECS1 63 DQ24 95 VDD5 127 DQ49 159 DQ1 32 ECS2 64 V

33 PD1 65 DQ22 97 NC 129 DQ47

42 DQ56 74 DQ8 106 A17 138 DQ33

51 DQ42 83 TIO7 115 V

59 DQ30 91 CG 123 V

67 DQ18 99 V

69 DQ16 101 A4 133 DQ41

75 DQ6 107 V

80 V

88 NC 120 DQ61 152 V

96 CWE3 128 V

SS SS

104 A10 136 V

112 PD0 144 V 113 PD2 145 DQ23

122 DQ57 154 DQ9

131 DQ43

139 DQ31

147 DQ19

149 DQ17

155 DQ7

160 V

TOP VIEW – CASE TBD

122

123

160

MCM64PC32•MCM64PC64 4

PRESENCE DETECT TABLE

Cache Size and

Functionality

256K Pipe Burst NC NC V 512K Pipe Burst V

PD0 PD1 PD2 PD3

MOTOROLA FAST SRAM

NC V

Page 5

PIN DESCRIPTIONS

160–Lead Card Edge Pin Locations Symbol

20, 21, 22, 23, 24, 26, 28, 29,

101, 102, 103, 104, 106, 108, 109, 110

36, 116 CLK0,

11, 12, 13, 14, 92, 93, 94, 96 CWE0 –

8 TWE Input Tag Write Enable: Active low write signal for tag RAMs. 18 BWE Input Byte Write Enable: To be used in future modules. 17 GWE Input Global Write Enable: To be used in future modules. 16 CCS Input Chip Select: Active low chip enable for data RAMs.

31, 32 ECS1,

30 ADSP Input Address Status Processor: Initiates READ, WRITE, or chip deselect

9 CADS Input Cache Address Status: Initiates READ, WRITE, or chip deselect cycle. 89 CADV Input Cache Burst Advance: Increments address count in accordance with

91 CG Input Cache Output Enable: Active low asynchronous input.

114 BOSEL Input Burst Order Select: NC for interleaved burst counter. T ie to ground for

38, 40, 41, 42, 44, 45, 46, 47, 49, 50, 51, 53, 54, 55, 57, 58, 59, 61, 62, 63, 65, 66,

67, 69, 70, 71, 73, 74, 75, 77, 78, 79, 118, 120, 121, 122, 124, 125, 126, 127, 129, 130, 131, 133, 134, 135, 137, 138, 139, 141, 142, 143, 145, 146, 147, 149,

150, 151, 153, 154, 155, 157, 158, 159

2, 3, 4, 5, 82, 83, 84, 85 TIO0 –

33, 34, 112, 113 PD0 –

7, 15, 25, 39, 52, 60, 68, 76 VDD3 Supply Power Supply: 3.3 V + 10%, – 5%.

87, 95, 105, 119, 132, 140, 148, 156 VDD5 Supply Power Supply: 5.0 V ± 5%.

1, 10, 19, 27, 35, 37, 43, 48, 56, 64, 72, 80, 81, 90, 99, 107, 115, 117, 123, 128,

136, 144, 152, 160

6, 86, 88, 97, 98 NC — No Connection: There is no connection to the module.

100, 111 RSVD — No Connection: Reserved for future use.

A3 – A18 Input Address Inputs: These inputs are registered into data RAMs and must

CLK1

CWE7

ECS2

DQ0 –

DQ63

TIO7

PD3

Type Description

meet setup and hold times. The tag RAM addresses are not registered.

Input Clock: This signal registers the address, data in, and all control signals

Input Cache Data Byte Write Enable: Active low write signal for data RAMs.

Input Expansion Chip Select

Supply Ground

except CG

cycle (Exception–chip deselect does not occur when ADSP and CCS

interleaved count style.

Low–enables output buffers (DQ pins) High–DQx pins are high impedance.

linear burst counter.

I/O Synchronous Data I/O:

Drives data out of data RAMs during READ cycles. Stores data to data RAMs during WRITE cycles.

I/O Tag RAM I/O:

Drives data out during tag compare cycles. Stores data to tag RAM during tag WRITE cycles.

— Presence Detect: See Presence Detect Table

is high.

is asserted

MOTOROLA FAST SRAM

MCM64PC32•MCM64PC64

Page 6

SYNCHRONOUS TRUTH TABLE (See Notes 1, 2, and 3)

CCS

H X L X X L–H N/A Deselected

X H H L L L–H Next Address Write Cycle, Continue Burst X H H L H L–H Next Address Read Cycle, Continue Burst X H H H L L–H Current Address Write Cycle, Suspend Burst X H H H H L–H Current Address Read Cycle, Suspend Burst H X H L L L–H Next Address Write Cycle, Continue Burst H X H L H L–H Next Address Read Cycle, Continue Burst H X H H L L–H Current Address Write Cycle, Suspend Burst H X H H H L–H Current Address Read Cycle, Suspend Burst

NOTES:

1. X means Don’t Care.

2. All inputs except CG

3. Wait states are inserted by suspending burst.

ADSP CADS CADV CWEx CLK0 Address Used Operation

L L X X X L–H External Address Read Cycle, Begin Burst

L H L X L L–H External Address Write Cycle, Begin Burst

L H L X H L–H External Address Read Cycle, Begin Burst

must meet setup and hold times for the low–to–high transition of clock (CLK0/1).

ASYNCHRONOUS TRUTH TABLE (See Notes 1 and 2)

Operation

Read L Data Out Read H High–Z Write X High–Z — Data In

Deselected X High–Z

NOTES:

1. X means Don’t Care.

2. For a write operation following a read operation, G

required setup time and held high through the input data hold time.

CG I/O Status

must be high before the input data

DC ABSOLUTE MAXIMUM RATINGS (Voltages Referenced to V

Rating

Power Supply Voltage VDD3 – 0.5 to + 4.6 V Voltage Relative to V Output Current (per I/O) I Temperature Under Bias T Operating Temperature T Storage Temperature T

NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are

exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability.

Symbol Value Unit

Vin, V

out

bias

stg

outVSS

– 0.5 to VDD3 + 0.5 V

± 20 mA

– 10 to + 85 °C

20 to +110 °C

– 55 to + 125 °C

= 0 V)

This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high–impedance circuit.

This BiCMOS memory circuit has been designed to meet the dc and ac specifications shown in the tables, after thermal equilibrium has been established.

This device contains circuitry that will ensure the output devices are in High–Z at power up.

MCM64PC32•MCM64PC64 6

MOTOROLA FAST SRAM

Page 7

DC OPERA TING CONDITIONS AND CHARACTERISTICS

(VDD = 3.3 V + 10%, – 5%, TJ = 20 to + 1 10 °C, Unless Otherwise Noted)

RECOMMENDED OPERATING CONDITIONS

Parameter

Supply Voltage (Operating Voltage Range) V Input High Voltage V Input Low Voltage V

NOTES:

1. JEDEC specification 8–1A specifies ± 0.3 V tolerance for VDD.

2. VIH (max) = VDD + 0.3 V dc; VIH (max) = VDD + 1.4 V ac (pulse width ≤ 20 ns) for I ≤ 20.0 mA.

3. VIL (min) = – 0.5 V dc; VIL (min) = – 2.0 V ac (pulse width ≤ 20 ns) for I ≤ 20.0 mA.

(Voltages referenced to VSS = 0 V)

Symbol Min Max Unit Notes

IH IL

DC CHARACTERISTICS

Parameter Symbol Min Max Unit Notes

Input Leakage Current (All Inputs, Vin = 0 to VDD3) I Output Leakage Current (CG = VIH) I TTL Output Low Voltage (IOL = + 8.0 mA) V TTL Output High Voltage (IOH = – 4.0 mA) V

NOTES:

1. Champing diodes exist to VSS and VDD.

lkg(I)

lkg(O)

POWER SUPPLY CURRENTS

Parameter Symbol Max Unit

AC Supply Current (CG = VIH, CCS = VIL, I VIL = 0.0 V and VIH ≥ 3.0 V, Cycle Time ≥ t

AC Standby Current (CG = VIH, CCS = VIL, I VIL = 0.0 V and VIH ≥ 3.0 V, Cycle Time ≥ t

= 0 mA, All Inputs = VIL or VIH, MCM64PC32

out

min) MCM64PC64

KHKH

= 0 mA, All Inputs = VIL or VIH, MCM64PC32

out

min) MCM64PC64

KHKH

3.135 3.6 V 1

2.0 VDD + 0.3 V 2

– 0.5 0.8 V 3

— ± 1.0 µA — ± 1.0 µA — 0.4 V 1

2.4 — V 1

DDA

SB1

635 795

180 405

CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, T

Input Capacitance MCM64PC32

Input/Output Capacitance (DQ0 – DQ63) MCM64PC32

= 20 to 110°C, Periodically Sampled Rather Than 100% Tested)

Parameter

MCM64PC64

Symbol Max Unit

I/O

16 26

MOTOROLA FAST SRAM

MCM64PC32•MCM64PC64

Page 8

DAT A RAMs AC OPERATING CONDITIONS AND CHARACTERISTICS

(VDD = 3.3 V + 10%, – 5% TJ = 20 to + 1 10 °C, Unless Otherwise Noted)

Input Timing Measurement Reference Level 1.5 V. . . . . . . . . . . . . . .

Input Pulse Levels 0 to 3.0 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input Rise/Fall Time 2 ns. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

OUTPUT LOAD

OUTPUT BUFFER

UNLOADED RISE AND FALL TIME MEASUREMENT

INPUT

WA VEFORM

OUTPUT

WA VEFORM

NOTES:

1. Input waveform should have a slew rate of 1 V/ns.

2. Rise time is measure from 0.4 V to 2.4 V unloaded.

3. Fall time is measure from 2.4 V to 0.4 V unloaded.

(UNLOADED OUTPUT)

0.4 0.4

TEST POINT

2.4

Output Timing Reference Level 1.5 V. . . . . . . . . . . . . . . . . . . . . . . . . .

Output Load See Figure 3 Unless Otherwise Noted. . . . . . . . . . . . . .

2.4

Figure 1. Unloaded Rise and Fall Time Characterization

MCM64PC32•MCM64PC64 8

MOTOROLA FAST SRAM

Page 9

DATA RAMs READ/WRITE CYCLE TIMING (See Notes 1, 2, and 3)

MCM64PC32–66

Parameter Symbol Min Max Unit Notes

Cycle Time t Clock Access Time t Output Enable to Output Valid t Clock High to Output Active t Clock High to Output Change t Output Enable to Output Active t Output Disable to Q High–Z t Clock High to Q High–Z t Clock High Pulse Width t Clock Low Pulse Width t Setup Times: Address

Hold Times: Address

NOTES:

1. Write applies to all SBx

2. Chip Enable applies to all SE1

3. All read and write cycle timings are referenced from K or G

4. G

is a don’t care after write cycle begins. To prevent bus contention, G should be negated prior to start of write cycle.

5. Tested per AC Test Load.

6. Measured at

7. This parameter is sampled and is not 100% tested.

± 200 mV from steady state. Tested per High–Z Test Load.

, SW, and SGW signals when the chip is selected and ADSP high.

, SE2 and SE3 signals whenever ADSP or ADSC is asserted.

Address Status

Data In

Write

Address Advance

Chip Enable

Address Status

Data In

Write

Address Advance

Chip Enable

KHKH

KHQV

GLQV KHQX1 KHQX2

GLQX

GHQZ

KHQZ

KHKL KLKH

AVKH

ADSVKH

DVKH t

WVKH

ADVVKH

EVKH t

KHAX

KHADSX

KHDX t

KHWX

KHADVX

KHEX

15 — ns — 8 ns 5 — 6 ns 5

0 — ns 5, 7 2 — ns 5, 7 0 — ns 5, 7

— 8 ns 6, 7

2 8 ns 6, 7 5 — ns 5 — ns

2.5 — ns 4

0.5 — ns 4

MOTOROLA FAST SRAM

MCM64PC32•MCM64PC64

Page 10

PULL–UP

3.6

VOLTAGE (V)

–0.5

1.4

1.65 2

3.135

3.6

NOTES:

1. Driver impedance @ 1.65 V = 15.9 to 44.6 Ω.

2. Meets the temperature and voltage range specified in DC Characteristics tables.

3. This drawing is not to scale. Comparisons should be made to the table in Figure 2a.

I (mA) Min I (mA) Max

– 40 – 40 – 40

– 37 –28

0 0

– 120 – 120 – 120

– 104

– 81 – 20

3.135

2.8

DC DRIVE

POINT

1.65

VOLTAGE (V)VOLTAGE (V)

1.4

AC DRIVE

POINT

–5

0 –40 –120

2a. Pull–Up

VOLTAGE (V)

–0.5

0.5 1

1.65

1.8

3.6 4

PULL–DOWN

I (mA) Min I (mA) Max

– 34

0 17 35 45 46 46 46

– 126

0 47 90

114 120 120 120

1.8

1.65

DC DRIVE

POINT

0.3

AC DRIVE

POINT

TEST POINT

– 80

CURRENT (mA)

TEST POINT

0 46 120

NOTES:

1. Driver impedance @ 1.65 V = 15.9 to 44.6 Ω.

2. Meets the temperature and voltage range specified in DC Characteristics tables.

3. This drawing is not to scale. Comparisons should be made to the table in Figure 2b.

2b. Pull–Down

Figure 2. Output Buffer Characteristics

CURRENT (mA)

MCM64PC32•MCM64PC64 10

MOTOROLA FAST SRAM

Page 11

KHQV

GLQX

BURST WRITE

ESC1 IGNORED

ADSP, Ax

DATA RAMs READ/WRITE CYCLES

KLKH

KHKL

KHKH

BURST WRAPS AROUND

KHQV

Q(B) D(C) D(C+1) D(C+2) D(C+3) Q(D)

Q(B+2) Q(B+3)

Q(B) Q(B+1)

Q(A)

GHQZ

BURST READSINGLE READ

KHQX2

KHQX1

CLK0, CLK1

MOTOROLA FAST SRAM

ADSP

(ADDRESS)

CADS

CADV

CCS

ESC1

Q(n–1)

KHQZ

DQx

DESELECTED SINGLE READ

Note: W low = GWE low and/or BWE and CWEx low.

MCM64PC32•MCM64PC64

Page 12

T AG RAM AC OPERATING CONDITIONS AND CHARACTERISTICS

(VDD = 3.3 V ± 0.3 V, TJ = 20 to + 110°C, Unless Otherwise Noted)

Input Timing Measurement Reference Level 1.5 V. . . . . . . . . . . . . . .

Input Pulse Levels 0 to 3.0 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input Rise/Fall Time 3 ns. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output Timing Measurement Reference Level 1.5 V. . . . . . . . . . . . .

Output Load Figure 3 Unless Otherwise Noted. . . . . . . . . . . . . . . . . .

TAG RAM READ CYCLE (See Note 1 and 5)

Parameter Symbol Min Max Unit Notes

Read Cycle Time t Address Access Time t Output Hold from Address Change t

NOTES:

1. CWE

is high for read cycle.

2. All timings are referenced from the last valid address to the first address transition.

3. Transition is measured ±500 mV from steady–state voltage with load of Figure 3B.

4. This parameter is sampled and not 100% tested.

5. Device is continuously selected (CG

= VIL).

AVAV AVQV AXQX

TAG RAM READ CYCLE (See Note 5)

AVAV

Ax (ADDRESS)

AXQX

–15

15 — ns 2 — 15 ns

4 — ns 3, 4

Q (DATA OUT)

OUTPUT

AVQV

AC TEST LOADS

3.3 V

Z0 = 50

Ω

OUTPUT

Ω

VL = 1.5 V

Figure 3A Figure 3B

351

Ω

317

5 pF

DATA VALIDPREVIOUS DATA VALID

TIMING LIMITS

The table of timing values shows either a

minimum or a maximum limit for each param-

Ω

eter. Input requirements are specified from the external system point of view. Thus, address setup time is shown as a minimum since the system must supply at least that much time (even though most devices do not require it). On the other hand, responses from the memory are specified from the device point of view. Thus, the access time is shown as a maximum since the device never provides data later than that time.

MCM64PC32•MCM64PC64 12

MOTOROLA FAST SRAM

Page 13

TAG RAM WRITE CYCLE (See Notes 1 and 2)

Parameter Symbol Min Max Unit Notes

Write Cycle Time t Address Setup Time t Address Valid to End of W rite t Data Valid to End of W rite t Data Hold Time t Write Low to Output High–Z t Write High to Output Active t Write Recovery Time t

NOTES:

1. A write occurs when CWE

2. If CG

goes low coincident with or after CWE goes low, the output will remain in a high impedance state.

3. All timings are referenced from the last valid address to the first address transition.

4. If CG

≥ VIH, the output will remain in a high impedance state.

5. At any given voltage and temperature, t

6. Transition is measured ±500 mV from steady–state voltage with load of Figure 3B.

7. This parameter is sampled and not 100% tested.

is low.

(max) is less than t

WLQZ

WHQX

AVAV AVWL AVWH

DVWH WHDX

WLQZ

WHQX WHAX

(min), both for a given device and from device to device.

TAG RAM WRITE CYCLE (See Notes 1 and 2)

–15

15 — ns 3

0 — ns

12 — ns

7 — ns 0 — ns 0 7 ns 5,6,7 4 — ns 5,6,7 0 — ns

AX (ADDRESS)

TWE

D (DATA IN)

Q (DATA OUT)

HIGH Z

AVWL

WLQZ

AVAV

AVWH

WLWH

DVWH

DATA VALID

HIGH Z

WHAX

WHDX

WHQX

MOTOROLA FAST SRAM

MCM64PC32•MCM64PC64

Page 14

ORDERING INFORMATION

(Order by Full Part Number)

64PC32

MCM 64PC64 XX XX

Motorola Memory Prefix Part Number

Full Part Number —MCM64PC32SG66 MCM64PC64SG66

Speed (66 = 66 MHz)

Package (SG = Gold Pad SIMM)

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty , representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “T ypical” parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.

MCM64PC32•MCM64PC64

MOTOROLA FAST SRAM

Page 15

P ACKAGE DIMENSIONS

CARD EDGE MODULE

COMPONENT

AREA

80 43 42 1

MIN .285 inches, MAX .305 inches

160–LEAD

CASE TBD

NOTE 4

–Y–

VIEW

–X–

FRONT VIEW

160X

0.004 (0.1) X

156X

H160X

160X

(N)

VIEW AA

160 123 122 81

COMPONENT

AREA

BACK VIEW

NOTE: Case Outline number to be determined.

NOTE 5

–T–

J NOTE 6

0.012 (0.3)

SIDE VIEW

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. CARD THICKNESS APPLIES ACROSS TABS AND INCLUDES PLATING AND/OR METALLIZATION.

4. DIMENSIONS C AND V DEFINE A DOUBLE–SIDED MODULE.

5. DIMENSION AB DEFINES OPTIONAL SINGLE–SIDED MODULE.

6. STRAIGHTNESS CALLOUT APPLIES TO TAB AREA ONLY.

DIM MIN MAX MIN MAX

A 4.330 4.350 109.98 110.49 B 1.120 1.140 28.45 28.96 C ––– 0.454 ––– 11.53 D 0.033 0.037 0.84 0.94 E 2.265 2.275 57.53 57.79 F 0.075 BSC 1.91 BSC G 0.050 BSC 1.27 BSC H ––– 0.030 ––– 0.51 J 0.055 0.069 1.40 1.75 K 0.210 ––– 5.33 ––– L 1.955 1.965 49.66 49.91

M 2.155 2.165 54.74 54.99

N 0.110 REF 2.79 REF P 0.300 ––– 7.62 ––– R 0.492 0.512 7.24 7.75 V 0.300 ––– 7.62 –––

W 0.040 0.060 1.02 1.52 AB ––– 0.262 ––– 6.66 AC 0.072 0.076 1.83 1.93

MILLIMETERSINCHES

MOTOROLA FAST SRAM

MCM64PC32•MCM64PC64

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How to reach us: USA/ EUROPE: Motorola Literature Distribution; JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, Toshikatsu Otsuki,

P.O. Box 20912; Phoenix, Arizona 85036. 1–800–441–2447 6F Seibu–Butsuryu–Center, 3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 03–3521–8315

MFAX: RMF AX0@email.sps.mot.com – T OUCHTONE (602) 244–6609 HONG KONG: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, INTERNET: http://Design–NET.com 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298

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