Datasheet MCM63F733ATQ11, MCM63F733ATQ11R, MCM63F733ATQ10R, MCM63F733ATQ10 Datasheet (Motorola)

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Order this document

by MCM63F733A/D

Advance Information

128K x 32 Bit Flow–Through
BurstRAM Synchronous
Fast Static RAM

The MCM63F733A is a 4M–bit synchronous fast static RAM designed to pro­vide a burstable, high performance, secondary cache for the PowerPC and
other high performance microprocessors. It is organized as 128K words of 32
bits each, fabricated with high performance silicon gate CMOS technology.
This device integrates input registers, a 2–bit address counter , and high speed
SRAM onto a single monolithic circuit for reduced parts count in cache data
RAM applications. Synchronous design allows precise cycle control with the
use of an external clock (K). CMOS circuitry reduces the overall power con­sumption of the integrated functions for greater reliability.

Addresses (SA), data inputs (DQx), and all control signals except output
enable (G
positive–edge–triggered noninverting registers.

Bursts can be initiated with either ADSP
addresses can be generated internally by the MCM63F733A (burst sequence
operates in linear or interleaved mode dependent upon state of LBO
trolled by the burst address advance (ADV

Write cycles are internally self–timed and are initiated by the rising edge of the
clock (K) input. This feature eliminates complex off–chip write pulse generation
and provides increased timing flexibility for incoming signals.

Synchronous byte write (SBx
nous write enable (SW
to all bytes. The four bytes are designated as “a”, “b”, “c”, and “d”. SBa
DQa, SBb
writes SBx
or if all SBx

For read cycles, a flow–through SRAM allows output data to simply flow freely
from the memory array .

The MCM63F733A operates from a 3.3 V core power supply and all outputs
operate on a 2.5 V or 3.3 V power supply. All inputs and outputs are JEDEC
Standard JESD8–5 compatible.

• MCM63F733A–10 = 10 ns Access/13 ns Cycle (75 MHz)

• 3.3 V + 10%/– 5% Core, Power Supply , 2.5 V or 3.3 V I/O Supply

• ADSP

• Selectable Burst Sequencing Order (Linear/Interleaved)

• Internally Self–Timed Write Cycle

• Byte Write and Global Write Control

• Single–Cycle Deselect

• Sleep Mode (ZZ)

• 100–Pin TQFP Package

) and Linear Burst Order (LBO) are clock (K) controlled through

or ADSC input pins. Subsequent burst

) and con-

) input pin.

), synchronous global write (SGW), and synchro-

) are provided to allow writes to either individual bytes or

controls
controls DQb, etc. Individual bytes are written if the selected byte
are asserted with SW. All bytes are written if either SGW is asserted

and SW are asserted.

MCM63F733A–11 = 11 ns Access/15 ns Cycle (66 MHz)

, ADSC, and ADV Burst Control Pins

MCM63F733A

TQ PACKAGE

TQFP

CASE 983A–01

The PowerPC name is a trademark of IBM Corp., used under license therefrom.

This document contains information on a new product. Specifications and information herein are subject to change without notice.

REV 2
3/20/98

 Motorola, Inc. 1998

MOTOROLA FAST SRAM

MCM63F733A

1

LBO

ADV

K
ADSC
ADSP

SA
SA1
SA0

SGW

FUNCTIONAL BLOCK DIAGRAM

K2

ADDRESS

REGISTER

17

BURST

COUNTER

CLR

2

15

2

17

128K x 32 ARRAY

SW

SBa

SBb

SBc

SBd

SE1
SE2

SE3

WRITE

REGISTER

a

WRITE

REGISTER

b

WRITE

REGISTER

c

WRITE

REGISTER

d

K2

ENABLE

REGISTER

4

DATA–IN

REGISTER

K

32

32

G

MCM63F733A
2

DQa – DQd

MOTOROLA FAST SRAM

PIN ASSIGNMENT

V

DDQ

V

DDQ

V

DQd

V

DDQ

DQd
DQd
DQd
DQd

V

DDQ

DQd
DQd

NC
DQc
DQc

V

SS
DQc
DQc

DQc
DQc
V

SS
DQc

DQc

NC
DD

NC

V

SS
DQd

V

SS

V

SS

NC

1
2
3
4
5
6
7

8
9

10
11
12
13
14
15
16
17
18
19
20

21
22
23
24
25
26
27
28
29
30

31 3233

SASASE1

DD

SE2

SBc

SBa

SBb

SBd

94 93979695 89889291 90 86858710099 98 81828384

3738343536 42433940 41 454644

SE3

K

VSSV

SW

SGW

G

ADSP

ADSC

ADV

SA

SA

NC

80
79

DQb

78

DQb
V

77

DDQ

V

76

SS

DQb

75

DQb

74

DQb

73

DQb

72

V

71

SS

V

70

DDQ

DQb

69

DQb

68

V

67

SS

NC

66

V

65

DD

ZZ

64

DQa

63

DQa

62

V

61

DDQ

V

60

SS

DQa

59

DQa

58
57

DQa

56

DQa
V

55

SS

V

54

DDQ

DQa

53

DQa

52

NC

51

50494847

SASASA

LBO

SA

SA1

SA0

NC

NC

V

SS

DD

V

NC

NC

SASASA

SA

SA

SA

SA

MOTOROLA FAST SRAM

MCM63F733A

3

PIN DESCRIPTIONS

Pin Locations Symbol

85 ADSC Input Synchronous Address Status Controller: Active low, interrupts any

84 ADSP Input Synchronous Address Status Processor: Active low, interrupts any

83 ADV Input Synchronous Address Advance: Increments address count in

(a) 51, 52, 53, 56, 57, 58, 59, 62, 63
(b) 68, 69, 72, 73, 74, 75, 78, 79, 80
(c) 1, 2, 3, 6, 7, 8, 9, 12, 13
(d) 18, 19, 22, 23, 24, 25, 28, 29, 30

86 G Input Asynchronous Output Enable Input.
89 K Input Clock: This signal registers the address, data in, and all control signals

31 LBO Input Linear Burst Order Input: This pin may be left floating; it will default as

32, 33, 34, 35, 44, 45, 46,

47, 48, 49, 50, 81, 82, 99, 100

36, 37 SA1, SA0 Input Synchronous Address Inputs: These pins must be wired to the two

93, 94, 95, 96

(a) (b) (c) (d)

98 SE1 Input Synchronous Chip Enable: Active low to enable chip.

97 SE2 Input Synchronous Chip Enable: Active high for depth expansion.
92 SE3 Input Synchronous Chip Enable: Active low for depth expansion.
88 SGW Input Synchronous Global Write: This signal writes all bytes regardless of the

87 SW Input Synchronous Write: This signal writes only those bytes that have been

64 ZZ Input Sleep Mode: This active high asynchronous signal places the RAM into

15, 41, 65, 91 V

4, 11, 20, 27, 54, 61, 70, 77 V

5, 10, 17, 21, 26, 40,

55, 60, 67, 71, 76, 90

14, 16, 38, 39, 42, 43, 66 NC — No Connection: There is no connection to the chip.

Type Description

ongoing burst and latches a new external address. Used to initiate a
READ, WRITE, or chip deselect.

ongoing burst and latches a new external address. Used to initiate a
new READ, WRITE, or chip deselect (exception — chip deselect does
not occur when ADSP

accordance with counter type selected (linear/interleaved).

DQx I/O Synchronous Data I/O: “x” refers to the byte being read or written

SA Input Synchronous Address Inputs: These inputs are registered and must

SBx Input Synchronous Byte Write Inputs: “x” refers to the byte being written

DD

DDQ

V

SS

Supply Core Power Supply.
Supply I/O Power Supply.
Supply Ground.

(byte a, b, c, d).

except G

interleaved.
Low — linear burst counter (68K/PowerPC).
High — interleaved burst counter (486/i960/Pentium).

meet setup and hold times.

LSBs of the address bus for proper burst operation. These inputs are
registered and must meet setup and hold times.

(byte a, b, c, d). SGW

Negated high — blocks ADSP
asserted.

status of the SBx
being used, tie this pin high.

selected using the byte write SBx
are being used, tie this pin low.

the lowest power mode. The ZZ pin disables the RAMs internal clock
when placed in this mode. When ZZ is negated, the RAM remains in
low power mode until it is commanded to READ or WRITE. Data
integrity is maintained upon returning to normal operation.

, LBO, and ZZ.

is asserted and SE1 is high).

overrides SBx.

or deselects chip when ADSC is

and SW signals. If only byte write signals SBx are

pins. If only byte write signals SBx

MCM63F733A
4

MOTOROLA FAST SRAM

TRUTH TABLE (See Notes 1 through 5)

Address

Next Cycle

Deselect None 1 X X X 0 X X High–Z X
Deselect None 0 X 1 0 X X X High–Z X
Deselect None 0 0 X 0 X X X High–Z X
Deselect None X X 1 1 0 X X High–Z X
Deselect None X 0 X 1 0 X X High–Z X
Begin Read External 0 1 0 0 X X X High–Z X
Begin Read External 0 1 0 1 0 X X High–Z READ
Continue Read Next X X X 1 1 0 1 High–Z READ
Continue Read Next X X X 1 1 0 0 DQ READ
Continue Read Next 1 X X X 1 0 1 High–Z READ
Continue Read Next 1 X X X 1 0 0 DQ READ
Suspend Read Current X X X 1 1 1 1 High–Z READ
Suspend Read Current X X X 1 1 1 0 DQ READ
Suspend Read Current 1 X X X 1 1 1 High–Z READ
Suspend Read Current 1 X X X 1 1 0 DQ READ
Begin Write External 0 1 0 1 0 X X High–Z WRITE
Continue Write Next X X X 1 1 0 X High–Z WRITE
Continue Write Next 1 X X X 1 0 X High–Z WRITE
Suspend Write Current X X X 1 1 1 X High–Z WRITE
Suspend Write Current 1 X X X 1 1 X High–Z WRITE

NOTES:

1. X = Don’t Care. 1 = logic high. 0 = logic low.

2. Write is defined as either 1) any SBx

3. G

is an asynchronous signal and is not sampled by the clock K. G drives the bus immediately (t

4. On write cycles that follow read cycles, G
G

must also remain negated at the completion of the write cycle to ensure proper write data hold times.

Used

SE1 SE2 SE3 ADSP ADSC ADV G

and SW low, or 2) SGW is low.

must be negated prior to the start of the write cycle to ensure proper write data setup times.

3

DQx Write 2,

) following G going low.

GLQX

4

ASYNCHRONOUS TRUTH TABLE

Operation ZZ G I/O Status

Read L L Data Out (DQx)
Read L H High–Z
Write L X High–Z

Deselected L X High–Z

Selected H X High–Z

LINEAR BURST ADDRESS TABLE (LBO = V

1st Address (External)

X . . . X00 X . . . X01 X . . . X10 X . . . X11
X . . . X01 X . . . X10 X . . . X11 X . . . X00
X . . . X10 X . . . X11 X . . . X00 X . . . X01
X . . . X11 X . . . X00 X . . . X01 X . . . X10

2nd Address (Internal) 3rd Address (Internal) 4th Address (Internal)

SS

)

MOTOROLA FAST SRAM

MCM63F733A

5

INTERLEAVED BURST ADDRESS TABLE (LBO = V

1st Address (External) 2nd Address (Internal) 3rd Address (Internal) 4th Address (Internal)

X . . . X00 X . . . X01 X . . . X10 X . . . X11
X . . . X01 X . . . X00 X . . . X11 X . . . X10
X . . . X10 X . . . X11 X . . . X00 X . . . X01
X . . . X11 X . . . X10 X . . . X01 X . . . X00

DD

)

WRITE TRUTH TABLE

Cycle Type SGW SW SBa SBb SBc SBd

Read H H X X X X
Read H L H H H H
Write Byte a H L L H H H
Write Byte b H L H L H H
Write Byte c H L H H L H
Write Byte d H L H H H L
Write All Bytes H L L L L L
Write All Bytes L X X X X X

ABSOLUTE MAXIMUM RATINGS (See Note 1)

Rating Symbol Value Unit Notes

Power Supply Voltage V
I/O Supply Voltage V
Input Voltage Relative to VSS for

Any Pin Except V
Input Voltage (Three–State I/O) V
Output Current (per I/O) I
Package Power Dissipation P
Temperature Under Bias T
Storage Temperature T

NOTES:

1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED OPER­ATING CONDITIONS. Exposure to higher than recommended voltages for extended
periods of time could affect device reliability.

2. This is a steady–state DC parameter that is in effect after the power supply has
achieved its nominal operating level. Power sequencing is not necessary.

3. Power dissipation capability is dependent upon package characteristics and use
environment. See Package Thermal Characteristics.

DD

DD

DDQ

Vin, V

out

bias

stg

out

IT

D

– 0.5 to + 4.6 V

VSS – 0.5 to V

– 0.5 to VDD + 0.5 V 2

– 0.5 to V

– 10 to + 85 °C

– 55 to + 125 °C

DD

+ 0.5 V 2

DDQ

± 20 mA

1.2 W 3

V 2

This device contains circuitry to protect the
inputs against damage due to high static volt­ages or electric fields; however, it is advised
that normal precautions be taken to avoid
application of any voltage higher than maxi­mum rated voltages to this high–impedance
circuit.

PACKAGE THERMAL CHARACTERISTICS

Rating Symbol Max Unit Notes

Junction to Ambient (@ 200 lfm) Single–Layer Board

Four–Layer Board
Junction to Board (Bottom) R
Junction to Case (Top) R

NOTES:

1. Junction temperature is a function of on–chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient
temperature, air flow, board population, and board thermal resistance.

2. Per SEMI G38–87.

3. Indicates the average thermal resistance between the die and the printed circuit board.

4. Indicates the average thermal resistance between the die and the case top surface via the cold plate method (MIL SPEC–883
Method 1012.1).

MCM63F733A

R

θJA

θJB
θJC

40
25

17 °C/W 3

9 °C/W 4

°C/W 1, 2

MOTOROLA FAST SRAM

6

DC OPERA TING CONDITIONS AND CHARACTERISTICS

(VDD = 3.3 V + 10%, – 5%, TA = 0 to 70°C, Unless Otherwise Noted)

RECOMMENDED OPERATING CONDITIONS: 2.5 V I/O Supply

Parameter Symbol Min Typ Max Unit

Supply Voltage V
I/O Supply Voltage V
Input Low Voltage V
Input High Voltage V
Input High Voltage (I/O Pins) V
Output Low Voltage (IOL = 2 mA) V
Output High Voltage (IOH = – 2 mA) V

(Voltages Referenced to VSS = 0 V)

DD

DDQ

IL

IH
IH2
OL
OH

3.135 3.3 3.6 V

2.375 2.5 2.9 V
– 0.3 — 0.7 V

1.7 — VDD + 0.3 V

1.7 — V
— — 0.7 V

1.7 — — V

RECOMMENDED OPERATING CONDITIONS: 3.3 V I/O Supply (Voltages Referenced to V

Parameter Symbol Min Typ Max Unit

Supply Voltage V
I/O Supply Voltage V
Input Low Voltage V
Input High Voltage V
Input High Voltage (I/O Pins) V
Output Low Voltage (IOL = 8 mA) V
Output High Voltage (IOH = – 4 mA) V

DD

DDQ

IL

IH
IH2
OL
OH

3.135 3.3 3.6 V

3.135 3.3 V
– 0.5 — 0.8 V

2 — VDD + 0.5 V
2 — V

— — 0.4 V

2.4 — — V

SS

= 0 V)

+ 0.3 V

DDQ

DD

+ 0.5 V

DDQ

V

V

SS

VSS – 1.0 V

V

IH

Figure 1. Undershoot Voltage

20% t

KHKH

(MIN)

MOTOROLA FAST SRAM

MCM63F733A

7

SUPPLY CURRENTS

Parameter Symbol Min Typ Max Unit Notes

Input Leakage Current (0 V ≤ Vin ≤ VDD) I
Output Leakage Current (0 V ≤ Vin ≤ V
AC Supply Current (Device Selected, MCM63F733A–10

All Outputs Open, Freq = Max) MCM63F733A–11
Includes VDD Only

CMOS Standby Supply Current (Device Deselected, Freq = 0,
VDD = Max, All Inputs Static at CMOS Levels)

Sleep Mode Supply Current (Sleep Mode, Freq = Max,
VDD = Max, All Other Inputs Static at CMOS Levels,
ZZ ≥ VDD – 0.2 V)

TTL Standby Supply Current (Device Deselected, Freq = 0,
VDD = Max, All Inputs Static at TTL Levels)

Clock Running (Device Deselected, MCM63F733A–10
Freq = Max, VDD = Max, All Inputs MCM63F733A–11
Toggling at CMOS Levels)

Static Clock Running (Device Deselected, MCM63F733A–10
Freq = Max, VDD = Max, All Inputs MCM63F733A–11
Static at TTL Levels)

NOTES:

1. LBO

pin has an internal pullup and will exhibit leakage currents of ± 5 µA.

2. ZZ pin has an internal pulldown and will exhibit leakage currents of ± 5 µA.

3. Reference AC Operating Conditions and Characteristics for input and timing.

4. All addresses transition simultaneously low (LSB) then high (MSB).

5. Data states are all zero.

6. Device is deselected as defined by the Truth Table.

7. Device in Sleep Mode as defined by the Asynchronous Truth Table.

8. CMOS levels for I/Os are VIT ≤ VSS + 0.2 V or ≥ V

9. TTL levels for I/Os are VIT ≤ VIL or ≥ V

) I

DDQ

DDQ

. TTL levels for other inputs are Vin ≤ VIL or ≥ VIH.

IH2

lkg(O)
I

– 0.2 V. CMOS levels for other inputs are Vin ≤ VSS + 0.2 V or ≥ VDD – 0.2 V.

lkg(I)

DDA

I

SB2

I

ZZ

I

SB3

I

SB4

I

SB5

— — ± 1 µA 1, 2
— — ± 1 µA
— — TBD mA 3, 4, 5

— — TBD mA 6, 8

— — 2 mA 2, 7, 8

— — TBD mA 6, 9

— — TBD mA 3, 4,

5, 6, 8

— — TBD mA 6, 9

CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, T

Parameter Symbol Min Typ Max Unit

Input Capacitance C
Input/Output Capacitance C

= 0 to 70°C, Periodically Sampled Rather Than 100% Tested)

A

I/O

in

— 4 5 pF
— 7 8 pF

MCM63F733A
8

MOTOROLA FAST SRAM

AC OPERA TING CONDITIONS AND CHARACTERISTICS

(VDD = 3.3 V + 10%, – 5%, TA = 0 to 70°C, Unless Otherwise Noted)

Input Timing Measurement Reference Level 1.25 V. . . . . . . . . . . . . .

Input Pulse Levels 0 to 2.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input Rise/Fall Time 1.0 V/ns (20 to 80%). . . . . . . . . . . . . . . . . . . . . .

Output Timing Reference Level 1.25 V. . . . . . . . . . . . . . . . . . . . . . . . .

Output Load See Figure 2 Unless Otherwise Noted. . . . . . . . . . . . . .

READ/WRITE CYCLE TIMING (See Notes 1 through 4)

MCM63F733A–10

75 MHz

Parameter Symbol

Cycle Time t
Clock High Pulse Width t
Clock Low Pulse Width t
Clock Access Time t
Output Enable to Output Valid t
Clock High to Output Active t
Clock High to Output Change t
Output Enable to Output Active t
Output Disable to Q High–Z t
Clock High to Q High–Z t
Setup Times: Address

Hold Times: Address

Sleep Mode Standby t

Sleep Mode Recovery t

Sleep Mode High to Q High–Z t

NOTES:

1. Write is defined as either any SBx
or ADSC is asserted.

2. All read and write cycle timings are referenced from K or G

3. G

is a don’t care after write cycle begins. To prevent bus contention, G should be negated prior to start of write cycle.

4. In order to reduce test correlation issues and to reduce the effects of application specific input edge rate variations on correlation between
data sheet parameters and actual system performance, FSRAM AC parametric specifications are always specified at V
design exercises, it is desirable to evaluate timing using other reference levels. Since the maximum test input edge rate is known and is given
in the AC Test Conditions section of the data sheet as 1 V/ns, one can easily interpolate timing values to other reference levels.

5. This parameter is sampled and not 100% tested.

6. Measured at

± 200 mV from steady state.

ADSP

, ADSC, ADV

Data In

Write

Chip Enable

ADSP

, ADSC, ADV

Data In

Write

Chip Enable

and SW low or SGW is low. Chip Enable is defined as SE1 low , SE2 high, and SE3 low whenever ADSP

KHKH

KHKL

KLKH
KHQV
GLQV

KHQX1
KHQX2

GLQX
GHQZ
KHQZ

t

ADKH

t

ADSKH
t

DVKH

t

WVKH

t

EVKH

t

KHAX

t

KHADSX

t

KHDX

t

KHWX

t

KHEX

ZZS

ZZREC

ZZQZ

.

Min Max Min Max

13 — 15 — ns

5.2 — 6 — ns

5.2 — 6 — ns
— 10 — 11 ns
— 3.8 — 3.8 ns

0 — 0 — ns 5, 6

1.5 — 1.5 — ns 6

0 — 0 — ns 5, 6

— 3.8 — 3.8 ns 5, 6

1.5 3.8 1.5 3.8 ns 5, 6

2 — 2 — ns

0.5 — 0.5 — ns

— 2 x

2 x

t

KHKH

— 15 — 15 ns

t

KHKH

— 2 x

MCM63F733A–1 1

66 MHz

— 2 x

t

KHKH

t

KHKH

Unit Notes

ns

— ns

DDQ

/2. In some

MOTOROLA FAST SRAM

MCM63F733A

9

OUTPUT

OUTPUT

C

L

Z0 = 50

Ω

1.25 V

Figure 2. AC Test Load

2400
2200

2000
1800

1600
1400

1200
1000

800

CLOCK ACCESS TIME DELA Y (ps)

600
400
200

0

RL = 50

Ω

LUMPED CAP ACITANCE, CL (pF)

100806040200

Figure 3. Lumped Capacitive Load and T ypical Derating Curve

MCM63F733A
10

MOTOROLA FAST SRAM

VOLTAGE (V)

– 0.5

0

0.8

1.25

1.5

2.3

2.7

2.9

VOLTAGE (V)

– 0.5

0

1.4

1.65

2.0

3.135

3.6

PULL–UP

I (mA) MIN I (mA) MAX

– 38
– 38
– 38
– 30

– 27

0
0
0

PULL–UP

I (mA) MIN I (mA) MAX

– 40
– 40
– 40
– 37
– 28

0
0

– 105
– 105
– 105

– 83
– 75

– 40
– 15

0

– 120
– 120
– 120
– 108

– 81
– 20

0

(a) Pull–Up for V

(b) Pull–Up: V

2.9

2.5

2.3

1.25

VOLTAGE (V)

0.8

DDQ

3.6

3.135

2.8

1.65

VOLTAGE (V)

1.4

DDQ

0

0 – 40 – 105

CURRENT (mA)

= 2.5 V

0

0

– 40

CURRENT (mA)

= 3.3 V

– 120– 80

PULL–DOWN

VOLTAGE (V)

– 0.5

0

0.4

0.8

1.25

1.6

2.8

3.2

3.4

I (mA) MIN I (mA) MAX

MOTOROLA FAST SRAM

0

0
10
20
31
40
40
40
40

V

DD

0

0
20
40
63
80
80
80
80

1.6

1.25

VOLTAGE (V)

0.3

0

040 80

(c) Pull–Down

Figure 4. T ypical Output Buffer Characteristics

CURRENT (mA)

MCM63F733A

11

CD

READ/WRITE CYCLES

GLQV

t

Q(B) D(C) D(C+1) D(C+2) D(C+3) Q(D)

GLQX

t

SE2, SE3

ADSP, SA

GHQZ

t

BURST WRITE

IGNORED

KLKH

t

KHKL

t

KHKH

t

Q(B+2) Q(B+3)

BURST WRAPS AROUND

KHQX2

Q(B) Q(B+1)

t

KHQV

t

AB

K

SA

ADSP

ADSC

ADV

SE1

E

W

G

Q(A)Q(n)

DQx

KHQX1

t

KHQZ

t

BURST READSINGLE READ

DESELECTED SINGLE READ

W low = SGW low and/or SW and SBx low.

NOTE: E low = SE2 high and SE3 low.

MCM63F733A
12

MOTOROLA FAST SRAM

NORMAL OPERATION

NO READS OR

WRITES ALLOWEDIN SLEEP MODE

SLEEP MODE TIMING

ZZREC

t

ZZ

I

WRITES ALLOWEDNORMAL OPERATION

NO NEW READS OR

K

ADS

ADDR

ADV

ZZ

ZZS

t

I

DD

ZZ

E low = SE1 low, SE2 high, SE3 low.

ADS high = both ADSC, ADSP high.

I (max) specifications will not be met if inputs toggle.

NOTE: ADS low = ADSC low or ADSP low.

ZZQZ

t

E

W

G

DQ

MOTOROLA FAST SRAM

MCM63F733A

13

APPLICATION INFORMATION

SLEEP MODE

A sleep mode feature, the ZZ pin, has been implemented
on the MCM63F733A. It allows the system designer to place
the RAM in the lowest possible power condition by asserting
ZZ. The sleep mode timing diagram shows the different
modes of operation: Normal Operation, No READ/WRITE
Allowed, and Sleep Mode. Each mode has its own set of
constraints and conditions that are allowed.

Normal Operation: All inputs must meet setup and hold
times prior to sleep and t

ZZREC

nanoseconds after re­covering from sleep. Clock (K) must also meet cycle, high,
and low times during these periods. Two cycles prior to sleep,
initiation of either a read or write operation is not allowed.

No READ/WRITE: During the period of time just prior to

sleep and during recovery from sleep, the assertion of either

, ADSP, or any write signal is not allowed. If a write

ADSC
operation occurs during these periods, the memory array
may be corrupted. Validity of data out from the RAM can not
be guaranteed immediately after ZZ is asserted (prior to
being in sleep).

Sleep Mode: The RAM automatically deselects itself. The

RAM disconnects its internal clock buffer . The external clock

K

may continue to run without impacting the RAMs sleep cur­rent (IZZ). All inputs are allowed to toggle — the RAM will not
be selected and perform any reads or writes. However, if
inputs toggle, the IZZ (max) specification will not be met.

NON–BURST SYNCHRONOUS OPERATION

Although this BurstRAM has been designed for PowerPC
— and other high end MPU–based systems, these SRAMs
can be used in other high speed L2 cache or memory
applications that do not require the burst address feature.
Most L2 caches designed with a synchronous interface can
make use of the MCM63F733A. The burst counter feature of
the BurstRAM can be disabled, and the SRAM can be con­figured to act upon a continuous stream of addresses. See
Figure 5.

CONTROL PIN TIE VALUES EXAMPLE

Non–Burst

Sync Non–Burst,
Pipelined SRAM

NOTE: Although X is specified in the table as a don’t care, the pin

must be tied either high or low.

ADSP ADSC ADV SE1 SE2 LBO

H L H L H X

(H ≥ VIH, L ≤ VIL)

ADDR A B CD EFGH

SE3

W

G

DQ

Q(B)Q(A)

Q(D)Q(C) D(E)

D(F)

D(G)

WRITESREADS

D(H)

Figure 5. Example Configuration as Non–Burst Synchronous SRAM

ORDERING INFORMATION

(Order by Full Part Number)

MCM 63F733A XX X X

Motorola Memory Prefix

Blank = Trays, R = Tape and Reel

Part Number

MCM63F733A
14

Speed (10 = 10 ns, 11 = 11 ns)
Package (TQ = TQFP)

Full Part Numbers — MCM63F733ATQ10 MCM63F733ATQ11

MCM63F733ATQ10R MCM63F733ATQ11R

MOTOROLA FAST SRAM

P ACKAGE DIMENSIONS

ÉÉÉ

4X

A–B0.20 (0.008) H

D

80 51

–D–

TQ PACKAGE

100–PIN TQFP

CASE 983A–01

2X 30 TIPS

C D

A–B0.20 (0.008)

e

e/2

–A–

–H–
–C–

SEATING
PLANE

0.05 (0.002)

81

100

S

2X 20 TIPS

A

A2

A1

D1/2

C D

S

R1

VIEW AB

D1

50

E/2

–B–

E1

E

E1/2

31

301

D/2

D

B
B

VIEW Y

BASE

METAL

b1

c

b

0.13 (0.005) D

M

–X–

X=A, B, OR D

PLATING

c1

S

A–B

C

S

SECTION B–B

NOTES:

A–B0.20 (0.008)

q

2

q

3

0.10 (0.004)

C

VIEW AB

q

1

0.25 (0.010)

GAGE PLANE

R2

L2

L

q

L1

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DATUM PLANE –H– IS LOCATED AT BOTTOM OF
LEAD AND IS COINCIDENT WITH THE LEAD
WHERE THE LEAD EXITS THE PLASTIC BODY AT
THE BOTTOM OF THE PARTING LINE.

4. DATUMS –A–, –B– AND –D– TO BE DETERMINED
AT DATUM PLANE –H–.

5. DIMENSIONS D AND E TO BE DETERMINED AT
SEATING PLANE –C–.

6. DIMENSIONS D1 AND E1 DO NOT INCLUDE
MOLD PROTRUSION. ALLOWABLE PROTRUSION
IS 0.25 (0.010) PER SIDE. DIMENSIONS D1 AND
B1 DO INCLUDE MOLD MISMATCH AND ARE
DETERMINED AT DATUM PLANE –H–.

7. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. DAMBAR PROTRUSION SHALL
NOT CAUSE THE b DIMENSION TO EXCEED 0.45
(0.018).

_
_

_

INCHESMILLIMETERS

0.020 REF

_
_
_
_

_
_

_

DIM MIN MAX MIN MAX

A ––– 1.60 ––– 0.063
A1 0.05 0.15 0.002 0.006
A2 1.35 1.45 0.053 0.057

b 0.22 0.38 0.009 0.015

b1 0.22 0.33 0.009 0.013

c 0.09 0.20 0.004 0.008

c1 0.09 0.16 0.004 0.006

D 22.00 BSC 0.866 BSC
D1 20.00 BSC 0.787 BSC

E 16.00 BSC 0.630 BSC

E1 14.00 BSC 0.551 BSC

e 0.65 BSC 0.026 BSC

L 0.45 0.75 0.018 0.030

L1 1.00 REF 0.039 REF
L2 0.50 REF

S 0.20 ––– 0.008 –––
R1 0.08 ––– 0.003 –––
R2 0.08 0.20 0.003 0.008

q

0 7 0 7

_

q

0 ––– 0 –––

1

_

q

11 13 11 13

2

_

q

11 13 11 13

3

_

MOTOROLA FAST SRAM

MCM63F733A

15

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty , representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. “T ypical” parameters which may be provided in Motorola
data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”
must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of
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applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury
or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal
Opportunity/Affirmative Action Employer.

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Mfax is a trademark of Motorola, Inc.

MCM63F733A
16

◊

MOTOROLA FAST SRAM

MCM63F733A/D