Page 1
MCM62486B
1
MOTOROLA FAST SRAM
32K x 9 Bit BurstRAM
Synchronous Static RAM
With Burst Counter and Self–Timed Write
The MCM62486B is a 294,912 bit synchronous static random access
memory designed to provide a burstable, high–performance, secondary cache
for the i486 and Pentium microprocessors. It is organized as 32,768 words of
9 bits, fabricated with Motorola’s high–performance silicon–gate CMOS
technology. The device integrates input registers, a 2–bit counter, high speed
SRAM, and high drive capability outputs onto a single monolithic circuit for reduced parts count implementation of cache data RAM applications. Synchronous design allows precise cycle control with the use of an external clock (K).
CMOS circuitry reduces the overall power consumption of the integrated functions for greater reliability.
Addresses (A0 – A14), data inputs (D0 – D8), and all control signals except
output enable (G
) are clock (K) controlled through positive–edge–triggered
noninverting registers.
Bursts can be initiated with either address status processor (ADSP
) or address
status cache controller (ADSC
) input pins. Subsequent burst addresses can be
generated internally by the MCM62486B (burst sequence imitates that of the
i486 and Pentium) and controlled by the burst address advance (ADV
) input pin.
The following pages provide more detailed information on burst controls.
Write cycles are internally self–timed and are initiated by the rising edge of the
clock (K) input. This feature eliminates complex off–chip write pulse generation
and provides increased flexibility for incoming signals.
The MCM62486B will be available in a 44–pin plastic leaded chip carrier
(PLCC). Multiple power and ground pins have been utilized to minimize effects
induced by output noise. Separate power and ground pins have been employed
for DQ0 – DQ8 to allow user–controlled output levels of 5 volts or 3.3 volts.
• Single 5 V ±
10% Power Supply (± 5% for MCM62486BFN11)
• Choice of 5 V or 3.3 V ± 10% Power Supplies for Output Level
Compatibility
• Fast Access Times:11/12/14/19 ns Max and Cycle Times:15/20/25 ns Min
• Internal Input Registers (Address, Data, Control)
• Internally Self–Timed Write Cycle
• ADSP
, ADSC, and ADV Burst Control Pins
• Asynchronous Output Enable Controlled Three–State Outputs
• Common Data Inputs and Data Outputs
• High Output Drive Capability: 85 pF per I/O
• High Board Density PLCC Package
• Fully TTL–Compatible
• Active High and Low Chip Select Inputs for Easy Depth Expansion
BurstRAM is a trademark of Motorola, Inc.
i486 and Pentium are trademarks of Intel Corp.
Order this document
by MCM62486B/D
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
MCM62486B
PIN NAMES
PIN ASSIGNMENT
A11
A12
A13
A14
DQ7
DQ6
DQ5
DQ4
A2
A3
A4
A5
A6
DQ0
DQ1
DQ2
V
SS
V
SSQ
V
CCQ
V
SS
V
SSQ
V
CCQ
A1
A0
K
VCCA7A8A9
A10
DQ3VSSQ
V
CC
V
SS
W
G
S0
S1
DQ8VSSQ
ADV
ADSP
A0 – A14 Address Inputs. . . . . . . . . . . . . . . .
K Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
W Write Enable. . . . . . . . . . . . . . . . . . . . . . . .
G
Output Enable. . . . . . . . . . . . . . . . . . . . . .
S0, S1
Chip Selects. . . . . . . . . . . . . . . . . . . .
ADV
Burst Address Advance. . . . . . . . . . . .
ADSP
, ADSC Address Status. . . . . . . . . . . .
DQ0 – DQ8 Data Input/Output. . . . . . . . . . .
V
CC
+ 5 V Power Supply. . . . . . . . . . . . . . . .
V
CCQ
Output Buffer Power Supply. . . . . . .
V
SS
Ground. . . . . . . . . . . . . . . . . . . . . . . . . .
V
SSQ
Output Buffer Ground. . . . . . . . . . . .
All power supply and ground pins must be connected for proper operation of the device. VCC ≥
V
CCQ
at all times including power up.
6 5 4 3 2 1 44 43 42 41 40
10
9
8
12
11
15
14
13
17
16
7
32
33
29
30
31
35
36
34
37
38
39
18 19 20 21 22 23 24 25 26 27 28
V
SS
ADSC
REV 2
5/95
Motorola, Inc. 1994
FN PACKAGE
44–LEAD PLCC
CASE 777–01
Page 2
MCM62486B
2
MOTOROLA FAST SRAM
BLOCK DIAGRAM (See Note)
DQ0 – DQ8
S0
K
A0 – A14
W
S1
G
BINARY
COUNTER
CLR
Q0
Q1
A0
A1
ADDRESS
REGISTER
WRITE
REGISTER
ENABLE
REGISTER
DATA–IN
REGISTERS
OUTPUT
BUFFER
32K x 9
MEMORY
ARRAY
ADV
BURST LOGIC
INTERNAL
ADDRESS
A0
′
A1
′
15
9
9
15
2
A2 – A14
A1 – A0
ADSC
ADSP
9
NOTE: All registers are positive–edge triggered. The ADSC or ADSP signals control the duration of the burst and the start of the
next burst. When ADSP
is sampled low, any ongoing burst is interrupted and a read (independent of W and ADSC) is per-
formed using the new external address. When ADSC
is sampled low (and ADSP is sampled high), any ongoing burst is
interrupted and a read or write (dependent on W
) is performed using the new external address. Chip selects (S0, S1) are
sampled only when a new base address is loaded. After the first cycle of the burst, ADV
controls subsequent burst cycles.
When ADV
is sampled low, the internal address is advanced prior to the operation. When ADV is sampled high, the internal
address is not advanced, thus inserting a wait state into the burst sequence accesses. Upon completion of a burst, the
address will wrap around to its initial state. See BURST SEQUENCE TABLE.
BURST SEQUENCE TABLE
(See Note)
External Address A14 – A2
A1 A0
1st Burst Address A14 – A2 A1 A0
2nd Burst Address A14 – A2 A1 A0
3rd Burst Address A14 – A2 A1 A0
NOTE: The burst wraps around to its initial state upon completion.
Page 3
MCM62486B
3
MOTOROLA FAST SRAM
SYNCHRONOUS TRUTH TABLE (See Notes 1, 2, 3, and 4)
S
ADSP ADSC ADV W K Address Used Operation
F L X X X L–H N/A Deselected
F X L X X L–H N/A Deselected
T L X X X L–H External Address Read Cycle, Begin Burst
T H L X L L–H External Address Write Cycle, Begin Burst
T H L X H L–H External Address Read Cycle, Begin Burst
X H H L L L–H Next Address Write Cycle, Continue Burst
X H H L H L–H Next Address Read Cycle, Continue Burst
X H H H L L–H Current Address Write Cycle, Suspend Burst
X H H H H L–H Current Address Read Cycle, Suspend Burst
NOTES:
1. X means Don’t Care.
2. All inputs except G
must meet setup and hold times for the low–to–high transition of clock (K).
3. S represents S0 and S1
. T implies S1 = L and S0 = H; F implies S1 = H or S0 = L.
4. Wait states are inserted by suspending burst.
ASYNCHRONOUS TRUTH TABLE (See Notes 1 and 2)
Operation
G I/O Status
Read L Data Out (DQ0 – DQ8)
Read H High–Z
Write X High–Z — Data In (DQ0 – DQ8)
Deselected X High–Z
NOTES:
1. X means Don’t Care.
2. For a write operation following a read operation, G
must be high before the input data
required setup time and held high through the input data hold time.
ABSOLUTE MAXIMUM RATINGS (Voltages Referenced to V
SS
= 0)
Rating
Symbol Value Unit
Power Supply Voltage V
CC
– 0.5 to 7.0 V
Output Power Supply Voltage V
CCQ
– 0.5 to V
CC
V
Voltage Relative to V
SS
Vin, V
out
– 0.5 to VCC + 0.5 V
Output Current (per I/O) I
out
± 20 mA
Power Dissipation P
D
1.0 W
Temperature Under Bias T
bias
– 10 to + 85 °C
Operating Temperature T
A
0 to + 70 °C
Storage Temperature T
stg
– 55 to + 125 °C
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for
extended periods of time could affect device reliability.
This device contains circuitry to protect the
inputs against damage due to high static
voltages or electric fields; however, it is advised that normal precautions be taken to avoid
application of any voltage higher than maximum rated voltages to this high–impedance
circuit.
This CMOS memory circuit has been designed to meet the dc and ac specifications
shown in the tables, after thermal equilibrium
has been established.
Page 4
MCM62486B
4
MOTOROLA FAST SRAM
DC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC, V
CCQ
= 5.0 V ± 5%, TA = 0 to + 70°C, for device MCM62486B–11)
(VCC = 5.0 V ± 10%, V
CCQ
= 5.0 V or 3.3 V ± 10%, TA = 0 to + 70°C, for all other devices)
RECOMMENDED OPERATING CONDITIONS
(Voltages referenced to VSS = 0 V)
Parameter
Symbol Min Max Unit
Supply Voltage (Operating Voltage Range) V
CC
4.5 5.5 V
Output Buffer Supply Voltage
(5.0 V TTL Compatible)
(3.3 V 50 Ω Compatible)
V
CCQ
4.5
3.0
5.5
3.6
V
Input High Voltage V
IH
2.2 VCC + 0.3 V
Input Low Voltage V
IL
– 0.5*
0.8 V
*VIL (min) = – 3.0 V ac (pulse width ≤ 20 ns)
DC CHARACTERISTICS
Parameter Symbol Min Max Unit
Input Leakage Current (All Inputs, Vin = 0 to VCC) I
lkg(I)
— ± 1.0 µA
Output Leakage Current (G, S1 = VIH, S0 = VIL, V
out
= 0 to V
CCQ
) I
lkg(O)
— ± 1.0 µA
AC Supply Current (G, S1 = VIL, S0 = VIH, All Inputs = VIL = 0.0 V and VIH ≥ 3.0 V,
I
out
= 0 mA, Cycle Time ≥ t
KHKH
min)
I
CCA
— 160 mA
Standby Current (S1 = VIH, S0 = VIL, All Inputs = VIL and VIH, Cycle Time ≥ t
KHKH
min) I
SB1
— 50 mA
Output Low Voltage (IOL = + 8.0 mA) V
OL
— 0.4 V
Output High Voltage (IOH = – 4.0 mA) V
OH
2.4 — V
NOTE: Good decoupling of the local power supply should always be used. DC characteristics are guaranteed for all possible i486 and Pentium
bus cycles.
CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, T
A
= 25°C, Periodically Sampled Rather Than 100% Tested)
Characteristic
Symbol Typ Max Unit
Input Capacitance (All Pins Except DQ0 – DQ8) C
in
2 3 pF
Input/Output Capacitance (DQ0 – DQ8) C
I/O
7 8 pF
Page 5
MCM62486B
5
MOTOROLA FAST SRAM
AC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC, V
CCQ
= 5.0 V ± 5%, TA = 0 to + 70°C, for device MCM62486B–11)
(VCC = 5.0 V ± 10%, V
CCQ
= 5.0 V or 3.3 V ± 10%, TA = 0 to + 70°C, for all other devices)
Input Timing Measurement Reference Level 1.5 V. . . . . . . . . . . . . . .
Input Pulse Levels 0 to 3.0 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Rise/Fall Time 3 ns. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Timing Reference Level 1.5 V. . . . . . . . . . . . . . . . . . . . . . . . . .
Output Load Figure 1A Unless Otherwise Noted. . . . . . . . . . . . . . . .
READ/WRITE CYCLE TIMING (See Notes 1, 2, and 3)
62486B–11 62486B–12 62486B–14 62486B–19
Parameter Symbol Min Max Min Max Min Max Min Max Unit Notes
Cycle Time t
KHKH
15 — 20 — 20 — 25 — ns
Clock Access Time t
KHQV
— 11 — 12 — 14 — 19 ns
Output Enable Access t
GLQV
— 5 — 5 — 6 — 7 ns
Clock High to Output Active t
KHQX1
6 — 6 — 6 — 6 — ns
Clock High to Q Change t
KHQX2
3 — 3 — 4 — 4 — ns
Output Enable to Q Active t
GLQX
0 — 0 — 0 — 0 — ns
Output Disable to Q High–Z t
GHQZ
— 6 — 6 — 6 — 7 ns 4
Clock High to Q High–Z t
KHQZ
— 6 — 6 — 6 — 6 ns
Clock High Pulse Width t
KHKL
5.5 — 7 — 8 — 6 — ns
Clock Low Pulse Width t
KLKH
5.5 — 7 — 8 — 6 — ns
Setup Times: Address
Address Status
Data In
Write
Address Advance
Chip Select
t
AVKH
t
ADSVKH
t
DVKH
t
WVKH
t
ADVVKH
t
S0VKH
t
S1VKH
2 — 2 — 3 — 3 — ns 5
Hold Times: Address
Address Status
Data In
Write
Address Advance
Chip Select
t
KHAX
t
KHADSX
t
KHDX
t
KHWX
t
KHADVX
t
KHS0X
t
KHS1X
2 — 2 — 2 — 2 — ns 5
NOTES:
1. A read cycle is defined by W
high or ADSP low for the setup and hold times. A write cycle is defined by W low and ADSP high for the setup
and hold times.
2. All read and write cycle timings are referenced from K or G
.
3. G
is a don’t care when W is sampled low.
4. Transition is measured
± 500 mV from steady–state voltage with load of Figure 1B. This parameter is sampled and not 100% tested. At any
given voltage and temperature, t
KHQZ
max is less than t
KHQX1
min for a given device and from device to device.
5. This is a synchronous device. All addresses must meet the specified setup and hold times for
ALL
rising edges of clock (K) whenever ADSP
and ADSC are low and the chip is selected. All other synchronous inputs must meet the specified setup and hold times for
ALL
rising edges
of K when the chip is selected.Chip select must be true (S1
low and S0 high) at each rising edge of clock for the device (when ADSP or ADSC
is low) to remain enabled. Timings for S1 and S0 are similar.
AC TEST LOADS
Figure 1B
5 pF
+ 5 V
OUTPUT
255
Ω
480
Ω
Figure 1A
OUTPUT
Z0 = 50
Ω
RL = 50
Ω
VL = 1.5 V
Page 6
MCM62486B
6
MOTOROLA FAST SRAM
Q(A2+2)Q(A2+1)Q(A2)Q(A2+3)Q(A2+2)Q(A2+1)Q(A2)Q(A1)
BURST READ
(ADV SUSPENDS BURST)
(BURST WRAPS AROUND
TO ITS INITIAL STATE)
SINGLE READ
ADSC
t
KHQZ
t
KHQV
t
KHQX2
t
GHQZ
t
GLQX
t
GLQV
t
KHQV
t
KHADVX
t
ADVVKH
t
KHS1X
t
S1VKH
t
KHWX
t
WVKH
t
KHADSX
t
ADSVKH
t
KHAX
t
AVKH
t
KLKH
t
KHKL
t
ADSVKH
t
KHKH
t
KHADSX
DATA OUT
G
ADV
S1
(S0 = V
IH
)
K
ADSP
ADDRESS
W
NOTE: Q(A2) represents the first output data from the base address A2; Q(A2+1) represents the next output data in the burst sequence with A2 as the base address.
A1 A2
READ CYCLES
Page 7
MCM62486B
7
MOTOROLA FAST SRAM
W IS IGNORED FOR FIRST CYCLE WHEN ADSP INITIATES BURST
NEW BURST WRITEBURST WRITE
ADV SUSPENDS BURST
t
KHDX
t
DVKH
t
KHADVX
t
ADVVKH
t
KHWX
t
WVKH
ADSC STARTS NEW BURST
A3
D(A3+2)D(A3+1)D(A3)D(A2+3)D(A2+2)D(A2+1)D(A2) D(A2+1)
t
KHADSX
t
ADSVKH
t
KHKH
t
KHKL
t
KLKH
D(A)
t
KHADSX
t
ADSVKH
t
KHAX
t
AVKH
t
KHSOX
t
SOVKH
SINGLE WRITEBURST READ
t
GHQZ
K
ADSP
ADSC
ADDRESS
W
(S1 = V
S0
IL
)
ADV
G
DATA IN
DATA OUT
A1 A2
WRITE CYCLES
Q(An–1) Q(An)
(WITH A SUSPENDED CYCLE)
Page 8
MCM62486B
8
MOTOROLA FAST SRAM
COMBINATION READ/WRITE CYCLE (E low, ADSC high)
BURST READREAD WRITE
K
ADSP
ADDRESS
W
ADV
G
DATA IN
DATA OUT
Q(A3)Q(A1) Q(A3+2)Q(A3+1)
t
KHQX2
t
GLQV
t
GHQZ
t
GLQX
t
KHQV
t
KHQX1
t
KHADVX
t
ADVVKH
t
KHWX
D(A2)
t
KHDX
t
DVKH
A3A2A1
t
WVKH
t
KHKH
t
ADSVKH
t
KLKH
t
KHKL
t
KHADSX
t
KHAX
t
AVKH
Page 9
MCM62486B
9
MOTOROLA FAST SRAM
APPLICATION EXAMPLE
i486DX4
DATA
ADDRESS
CLK
ADS
CONTROL
MCM62486B
CLOCK
ADDR
K
CACHE
CONTROL LOGIC
ADDR DATA
K
ADSC
W
G
ADV ADSP
DATA BUS
ADDRESS BUS
128K Byte Burstable, Secondary Cache Using
4 MCM62486BFN19s With a 100 MHz i486DX4
15 36
Page 10
MCM62486B
10
MOTOROLA FAST SRAM
ORDERING INFORMATION
(Order by Full Part Number)
Motorola Memory Prefix
Part Number
Full Part Numbers — MCM62486BFN11 MCM62486BFN12 MCM62486BFN14 MCM62486BFN19
Speed (11 = 11 ns, 12 = 12 ns, 14 = 14 ns,
19 = 19 ns)
Package (FN = PLCC)
MCM 62486B XX XX
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty , representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “T ypical” parameters can and do vary in different
applications. All operating parameters, including “T ypicals” must be validated for each customer application by customer’s technical experts. Motorola does
not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in
systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of
the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such
unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless
against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part.
Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
Page 11
MCM62486B
11
MOTOROLA FAST SRAM
PACKAGE DIMENSIONS
FN PACKAGE
44–LEAD PLCC
CASE 777–02
A
B
C
E
F
G
H
J
K
R
U
V
W
X
Y
Z
G1
K1
MIN MINMAX MAX
MILLIMETERS INCHES
DIM
17.40
17.40
4.20
2.29
0.33
0.66
0.51
0.64
16.51
16.51
1.07
1.07
1.07
—
2
°
15.50
1.02
17.65
17.65
4.57
2.79
0.48
0.81
—
—
16.66
16.66
1.21
1.21
1.42
0.50
10
°
16.00
—
0.685
0.685
0.165
0.090
0.013
0.026
0.020
0.025
0.650
0.650
0.042
0.042
0.042
—
2
°
0.610
0.040
0.695
0.695
0.180
0.110
0.019
0.032
—
—
0.656
0.656
0.048
0.048
0.056
0.020
10
°
0.630
—
1.27 BSC 0.050 BSC
NOTES:
1. DUE TO SPACE LIMITATION, CASE 777-02
SHALL BE REPRESENTED BY A GENERAL
(SMALLER) CASE OUTLINE DRAWING
RATHER THAN SHOWING ALL 44 LEADS.
2. DATUMS -L-, -M-, AND -N- DETERMINED
WHERE TOP OF LEAD SHOULDER EXITS
PLASTIC BODY AT MOLD PARTING LINE.
3. DIM G1, TRUE POSITION TO BE MEASURED
AT DATUM -T-, SEATING PLANE.
4. DIM R AND U DO NOT INCLUDE MOLD FLASH.
ALLOWABLE MOLD FLASH IS 0.25 (0.010) PER
SIDE.
5. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
6. CONTROLLING DIMENSION: INCH.
7. THE PACKAGE TOP MAY BE SMALLER THAN
THE PACKAGE BOTTOM BY UP TO .012 (.300).
DIMENSIONS R AND U ARE DETERMINED AT
THE OUTERMOST EXTREMES OF THE
PLASTIC BODY EXCLUSIVE OF MOLD FLASH,
TIE BAR BURRS, GATE BURRS AND
INTERLEAD FLASH, BUT INCLUDING ANY
MISMATCH BETWEEN THE TOP AND BOTTOM
OF THE PLASTIC BODY.
8. DIMENSION H DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTRUSION(S) SHALL NOT CAUSE THE H
DIMENSION TO BE GREATER THAN .037
(.940). THE DAMBAR INTRUSION(S) SHALL
NOT CAUSE THE H DIMENSION TO BE
SMALLER THAN .025 (.635).
9. 777-01 IS OBSOLETE, NEW STANDARD 777-02.
-N-
-M-
Y BRK
D
D
W
V
1
44
44
LEADS
ACTUAL
-L-
A
R
Z
C
G
G1
VIEW S
J
E
K
K1
H
F
VIEW D-D
X
G1
U
B
Z
VIEW S
0.10 (0.004)
SEATING
PLANE
-T-
0.25 (0.010) T L
–M
SNSS
0.18 (0.007) T L
–M
SNSM
0.18 (0.007) T L
–M
SNSM
0.18 (0.007) T L
–M
SNSM
0.18 (0.007) T L
–M
SNSM
0.25 (0.010) T L
–M
SNSS
0.18 (0.007) T L
–M
SNSM
0.18 (0.007) T L
–M
SNSM
Page 12
MCM62486B
12
MOTOROLA FAST SRAM
Literature Distribution Centers:
USA: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036.
JAPAN: Nippon Motorola Ltd.; 4–32–1, Nishi–Gotanda, Shinagawa–ku, Tokyo 141, Japan.
ASIA PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Center, No. 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong.
MCM62486B/D
*MCM62486B/D*
◊
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