Datasheet MCM62449WJ35R2, MCM62449WJ25R2, MCM62449WJ20, MCM62449WJ20R2, MCM62449WJ25 Datasheet (Motorola)

MCM6249

1

MOTOROLA FAST SRAM

1M x 4 Bit Static Random
Access Memory

The MCM6249 is a 4,194,304 bit static random access memory organized as
1,048,576 words of 4 bits, fabricated using high–performance silicon–gate
CMOS technology. Static design eliminates the need for external clocks or timing
strobes, while CMOS circuitry reduces power consumption and provides for
greater reliability .

The MCM6249 is equipped with chip enable (E

) and output enable (G) pins,
allowing for greater system flexibility and eliminating bus contention problems.
Either input, when high, will force the outputs into high impedance.

The MCM6249 is available in a 400 mil, 32–lead surface–mount SOJ package.

• Single 5 V ± 10% Power Supply

• Fast Access Time: 20/25/35 ns

• Equal Address and Chip Enable Access Time

• All Inputs and Outputs are TTL Compatible

• Three–State Outputs

• Power Operation: 190/175/160 mA Maximum, Active AC

BLOCK DIAGRAM

G

A18 A17 A16 A15 A14 A19 A3 A2 A1 A0

MEMORY MATRIX

1024 ROWS x

4096 COLUMNS

ROW

DECODER

INPUT

DATA

CONTROL

A11
A10

A9
A8
A7
A6
A5
A4

DQ0

DQ3

E

W

A13
A12

COLUMN I/O

COLUMN DECODER

DQ0

DQ3

Order this document

by MCM6249/D

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

PIN ASSIGNMENT

MCM6249

A0 – A19 Address Inputs. . . . . . . . . . . .

W

Write Enable. . . . . . . . . . . . . . . . . . . .

G

Output Enable. . . . . . . . . . . . . . . . . . .

E

Chip Enable. . . . . . . . . . . . . . . . . . . . . .

DQ0 – DQ3 Data Input/Output. . . . . . . .

NC No Connection. . . . . . . . . . . . . . . . .

V

CC

+ 5 V Power Supply. . . . . . . . . . . .

V

SS

Ground. . . . . . . . . . . . . . . . . . . . . . .

PIN NAMES

WJ PACKAGE

400 MIL SOJ

CASE 857A–02

32
31
30
29
28
27
26
25
24
23
22
21

2
3

1

5
6

4

7

9

10

8

12
13

11

14

20

15
16

19
18
17

A8
A9

A17

A6

E

A11

W
A13
A18
A10

V

CC

A16

A14
A3

A15

DQ2
A2

G
DQ3

A4
A19

A5

A0

V

SS

V

CC

V

SS

DQ0

DQ1

A7

A1

A12 NC

REV 4
5/95

 Motorola, Inc. 1995

MCM6249
2

MOTOROLA FAST SRAM

TRUTH TABLE (X = Don’t Care)

E

G W Mode I/O Pin Cycle Current

H X X Not Selected High–Z — I

SB1

, I

SB2

L H H Output Disabled High–Z — I

CCA

L L H Read D

out

Read I

CCA

L X L Write High–Z Write I

CCA

ABSOLUTE MAXIMUM RATINGS (See Note)

Rating

Symbol Value Unit

Power Supply Voltage Relative to V

SS

V

CC

– 0.5 to + 7.0 V

Voltage Relative to VSS for Any Pin

Except V

CC

Vin, V

out

– 0.5 to VCC + 0.5 V

Output Current (per I/O) I

out

± 20

mA

Power Dissipation P

D

1.0 W

Temperature Under Bias T

bias

– 10 to + 85 °C

Operating Temperature T

A

0 to + 70 °C

Storage Temperature — Plastic T

stg

– 55 to + 150 °C

NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are

exceeded. Functional operation should be restricted to RECOMMENDED OPER­ATING CONDITIONS. Exposure to higher than recommended voltages for
extended periods of time could affect device reliability.

DC OPERA TING CONDITIONS AND CHARACTERISTICS

(VCC = 5.0 V ± 10%, TA = 0 to + 70°C, Unless Otherwise Noted)

RECOMMENDED OPERATING CONDITIONS

Parameter Symbol Min Typ Max Unit

Supply Voltage (Operating Voltage Range) V

CC

4.5 5.0 5.5 V

Input High Voltage V

IH

2.2 — VCC + 0.3 V

Input Low Voltage V

IL

– 0.5*

— 0.8 V

*VIL (min) = – 0.5 V dc; VIL (min) = – 2.0 V ac (pulse width ≤ 2.0 ns).

DC CHARACTERISTICS

Parameter Symbol Min Max Unit

Input Leakage Current (All Inputs, Vin = 0 to VCC) I

lkg(I)

— ± 1.0 µA

Output Leakage Current (E = VIH, V

out

= 0 to VCC) I

lkg(O)

— ± 1.0 µA

Output Low Voltage (IOL = + 8.0 mA) V

OL

— 0.4 V

Output High Voltage (IOH = – 4.0 mA) V

OH

2.4 — V

POWER SUPPLY CURRENTS

Parameter Symbol Min Typ Max Unit

AC Active Supply Current (I

out

= 0 mA, MCM6249–20: t

AVAV

= 20 ns

VCC = max) MCM6249–25: t

AVAV

= 25 ns

MCM6249–35: t

AVAV

= 35 ns

I

CC

—
—
—

175
160
145

190
175
160

mA

AC Standby Current (VCC = max, MCM6249–20: t

AVAV

= 20 ns

E

= VIH, No other restrictions on MCM6249–25: t

AVAV

= 25 ns

other inputs) MCM6249–35: t

AVAV

= 35 ns

I

SB1

—
—
—

50
40
35

60
50
40

mA

CMOS Standby Current (E ≥ VCC – 0.2 V , Vin ≤ VSS + 0.2 V or

≥ VCC – 0.2 V) (VCC = max, f = 0 MHz)

I

SB2

— 10 15 mA

This device contains circuitry to protect the
inputs against damage due to high static
voltages or electric fields; however, it is ad­vised that normal precautions be taken to avoid
application of any voltage higher than maxi­mum rated voltages to these high impedance
circuits.

This CMOS memory circuit has been de­signed to meet the dc and ac specifications
shown in the tables, after thermal equilibrium
has been established. The circuit is in a test
socket or mounted on a printed circuit board
and transverse air flow of at least 500 linear
feet per minute is maintained.

MCM6249

3

MOTOROLA FAST SRAM

CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, T

A

= 25°C, Periodically Sampled Rather Than 100% Tested)

Parameter

Symbol Typ Max Unit

Input Capacitance All Inputs Except Clocks and DQs

E

, G, W

C

in

C

ck

4
5

6
8

pF

Input/Output Capacitance DQ C

I/O

5 8 pF

AC OPERA TING CONDITIONS AND CHARACTERISTICS

(VCC = 5.0 V ± 10%, TA = 0 to + 70°C, Unless Otherwise Noted)

Input Pulse Levels 0 to 3.0 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input Rise/Fall Time 2 ns. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input Timing Measurement Reference Level 1.5 V. . . . . . . . . . . . . . .

Output Timing Measurement Reference Level 1.5 V. . . . . . . . . . . . .

Output Load See Figure 1a. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

READ CYCLE TIMING (See Note 1)

MCM6249–20 MCM6249–25 MCM6249–35

Parameter Symbol Min Max Min Max Min Max Unit Notes

Read Cycle Time t

AVAV

20 — 25 — 35 — ns 2, 3

Address Access Time t

AVQV

— 20 — 25 — 35 ns

Enable Access Time t

ELQV

— 20 — 25 — 35 ns 4

Output Enable Access Time t

GLQV

— 6 — 8 — 10 ns

Output Hold from Address Change t

AXQX

5 — 5 — 5 — ns

Enable Low to Output Active t

ELQX

5 — 5 — 5 — ns 5, 6, 7

Output Enable Low to Output Active t

GLQX

0 — 0 — 0 — ns 5, 6, 7

Enable High to Output High–Z t

EHQZ

0 9 0 10 0 12 ns 5, 6, 7

Output Enable High to Output High–Z t

GHQZ

0 9 0 10 0 12 ns 5, 6, 7

Power Up Time t

ELICCH

0 — 0 — 0 — ns

Power Down Time t

EHICCL

— 20 — 25 — 35 ns

NOTES:

1. W

is high for read cycle.

2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus con–
tention conditions during read and write cycles.

3. All read cycle timings are referenced from the last valid address to the first transitioning address.

4. Addresses valid prior to or coincident with E

going low/E going high.

5. At any given voltage and temperature, t

EHQZ

max t t

ELQX

min, and t

GHQZ

max t t

GLQX

min, both for a given device and from device

to device.

6. Transition is measured ± 500 mV from steady–state voltage with load of Figure 1b.

7. This parameter is sampled and not 100% tested.

8. Device is continuously selected (E

≤ VIL, G ≤ VIL).

(a) (b)

The table of timing values shows either a minimum
or a maximum limit for each parameter. Input re­quirements are specified from the external system
point of view. Thus, address setup time is shown as
a minimum since the system must supply at least
that much time. On the other hand, responses from
the memory are specified from the device point of
view. Thus, the access time is shown as a maximum
since the device never provides data later than that
time.

TIMING LIMITS

OUTPUT

Z0 = 50

Ω

RL = 50

Ω

VL = 1.5 V

5 pF

+ 5 V

OUTPUT

255

Ω

480

Ω

Figure 1. AC Test Loads

MCM6249
4

MOTOROLA FAST SRAM

READ CYCLE 1 (See Note 8)

t

AXQX

t

AVAV

t

AVQV

DATA VALIDPREVIOUS DATA VALID

A (ADDRESS)

Q (DATA OUT)

READ CYCLE 2 (See Note)

Q (DATA OUT)

A (ADDRESS)

E (CHIP ENABLE)

G

(OUTPUT ENABLE)

NOTE: Addresses valid prior to or coincident with E going low/E going high.

t

AVAV

t

ELQV

t

ELQX

t

EHQZ

t

GHQZ

t

GLQV

t

GLQX

t

AVQV

t

ELICCH

t

EHICCL

I

SB

SUPPLY CURRENT

I

CC

HIGH–Z

DATA VALID

MCM6249

5

MOTOROLA FAST SRAM

WRITE CYCLE 1 (W Controlled, See Notes 1, 2, and 3)

MCM6249–20 MCM6249–25 MCM6249–35

Parameter Symbol Min Max Min Max Min Max Unit Notes

Write Cycle Time t

AVAV

20 — 25 — 35 — ns 4

Address Setup Time t

AVWL

0 — 0 — 0 — ns

Address Valid to End of W rite t

AVWH

15 — 17 — 20 — ns

Write Pulse Width t

WLWH,
t

WLEH

15 — 17 — 20 — ns

Data Valid to End of W rite t

DVWH

10 — 10 — 15 — ns

Data Hold Time t

WHDX

0 — 0 — 0 — ns

Write Low to Data High–Z t

WLQZ

0 9 0 10 0 15 ns 5,6,7

Write High to Output Active t

WHQX

5 — 5 — 5 — ns 5,6,7

Write Recovery Time t

WHAX

0 — 0 — 0 — ns

NOTES:

1. A write occurs during the overlap of E

low and W low.

2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus con–
tention conditions during read and write cycles.

3. If G

goes low coincident with or after W goes low, the output will remain in a high–impedance state.

4. All write cycle timings are referenced from the last valid address to the first transitioning address.

5. Transition is measured ± 500 mV from steady–state voltage with load of Figure 1b.

6. This parameter is sampled and not 100% tested.

7. At any given voltage and temperature, t

WLQZ

max < t

WHQX

min both for a given device and from device to device.

WRITE CYCLE 1 (W Controlled, See Notes 1, 2, and 3)

DATA VALID

HIGH–Z

HIGH–Z

t

AVAV

t

AVWH

t

WHAX

t

WHDX

t

WHQX

t

WLWH

t

AVWL

t

DVWH

t

WLQZ

A (ADDRESS)

E

(CHIP ENABLE)

W

(WRITE ENABLE)

D (DATA IN)

Q (DATA OUT)

t

WLEH

MCM6249
6

MOTOROLA FAST SRAM

WRITE CYCLE 2 (E Controlled, See Notes 1, 2, and 3)

MCM6249–20 MCM6249–25 MCM6249–35

Parameter Symbol Min Max Min Max Min Max Unit Notes

Write Cycle Time t

AVAV

20 — 25 — 35 — ns 4

Address Setup Time t

AVEL

0 — 0 — 0 — ns

Address Valid to End of W rite t

AVEH

15 — 17 — 20 — ns

Enable Pulse Width t

ELEH,

t

ELWH

15 — 17 — 20 — ns 5,6

Write Pulse Width t

WLEH

15 — 17 — 20 — ns

Data Valid to End of W rite t

DVEH

10 — 10 — 15 — ns

Data Hold Time t

EHDX

0 — 0 — 0 — ns

Write Recovery Time t

EHAX

0 — 0 — 0 — ns

NOTES:

1. A write occurs during the overlap of E

low and W low.

2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus con–
tention conditions during read and write cycles.

3. If G

goes low coincident with or after W goes low, the output will remain in a high–impedance state.

4. All write cycle timing is referenced from the last valid address to the first transitioning address.

5. If E

goes low coincident with or after W goes low, the output will remain in a high impedance condition.

6. If E

goes high coincident with or before W goes high, the output will remain in a high impedance condition.

WRITE CYCLE 2 (E Controlled, See Notes 1, 2, and 3)

DATA VALID

HIGH–Z

t

AVAV

t

AVEH

t

AVEL

t

ELWH

t

EHAX

t

DVEH

t

EHDX

A (ADDRESS)

E

(CHIP ENABLE)

W

(WRITE ENABLE)

D (DATA IN)

Q (DATA OUT)

t

ELEH

t

WLEH

ORDERING INFORMATION

(Order by Full Part Number)

Motorola Memory Prefix
Part Number

Package (WJ = 400 mil SOJ)

Full Part Numbers — MCM6249WJ20 MCM6249WJ20R2

MCM6249WJ25 MCM6249WJ25R2
MCM6249WJ35 MCM6249WJ35R2

Shipping Method (R2 = Tape and Reel, Blank = Rails)
Speed (20 = 20 ns, 25 = 25 ns, 35 = 35 ns)

MCM 6249 XX XX XX

MCM6249

7

MOTOROLA FAST SRAM

P ACKAGE DIMENSIONS

WJ PACKAGE

400 MIL SOJ

CASE 857A–02

MIN MINMAX MAX

MILLIMETERS INCHES

DIM

G

-T-

0.10 (0.004)

SEATING
PLANE

R

-B-

P

0.17 (0.007)ST

S

S

B

A

0.17 (0.007)ST

S

S

A

B

0.17 (0.007)ST

S

S

A

B

0.25 (0.010)

S

T

S

S

B

A

-A­L

32

17

16

1

K

D

32 PL

DETAIL Z

RADIUS

F

32 PL

N

NOTE 3

NOTE 3

DETAIL Z

S

C

E

A
B
C
D
E
F
G
K
L
N
P
R
S

20.83

10.03

3.26

0.41

2.24

0.67

0.89

0.76

11.05

9.27

0.77

21.08

10.29

3.75

0.50

2.48

0.81

1.14

1.14

11.30

9.52

1.01

0.820

0.395

0.128

0.016

0.088

0.026

0.035

0.030

0.435

0.365

0.030

0.830

0.405

0.148

0.020

0.098

0.032

0.045

0.045

0.445

0.375

0.040

1.27 BSC

0.64 BSC

0.050 BSC

0.025 BSC

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. TO BE DETERMINED AT PLANE -T-.

4. DIMENSION A & B DO NOT INCLUDE MOLD
PROTRUSION. MOLD PROTRUSION SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.

5. DIMENSION A & B INCLUDE MOLD MISMATCH AND
ARE DETERMINED AT THE PARTING LINE.

6. 857A-01 IS OBSOLETE, NEW STANDARD 857A-02.

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty , representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. “T ypical” parameters which may be provided in Motorola
data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”
must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of
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applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury
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arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
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Opportunity/Affirmative Action Employer.

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MCM6249/D

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