Datasheet MCM6227BJ25R2, MCM6227BJ35, MCM6227BJ35R2, MCM6227BWJ15, MCM6227BJ17 Datasheet (Motorola)

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

1M x 1 Bit Static Random

Order this document

by MCM6227B/D

MCM6227B

Access Memory

The MCM6227B is a 1,048,576 bit static random–access memory organized
as 1,048,576 words of 1 bit. Static design eliminates the need for external clocks
or timing strobes while CMOS circuitry reduces power consumption and provides
for greater reliability .

The MCM6227B is each equipped with a chip enable (E
vides reduced system power requirements without degrading access time per­formance.

The MCM6227B is available in 300 mil and 400 mil, 28–lead surface–mount
SOJ packages.

• Single 5 V ± 10% Power Supply

• Fast Access Times: 15/17/20/25/35 ns

• Equal Address and Chip Enable Access Times

• Input and Output are TTL Compatible

• Three–State Output

• Low Power Operation: 1 15/110/105/100/95 mA Maximum, Active AC

BLOCK DIAGRAM

A
A
A
A
A
A
A

ROW

DECODER

MEMORY MATRIX

512 ROWS x

2048 x 1 COLUMNS

) pin. This feature pro-

CASE 810B–03

WJ PACKAGE

PIN ASSIGNMENT

1

A
A

2
3

A
A

4
5

A

6

A

NC

7
8

A
A

9

A

10
11

A

12

Q

13

W

V

14

SS

J PACKAGE
300 MIL SOJ

400 MIL SOJ

CASE 810–03

V

28

CC

A

27

A

26

A

25

A

24

A

23

A

22

NC*

21

A

20
19

A

18

A

17

A

16

D

15

E

A
A

D

E

W

REV 3
10/31/96

 Motorola, Inc. 1994

MOTOROLA FAST SRAM

INPUT

DATA

CONTROL

COLUMN I/O

COLUMN DECODER

AAAAAA

A

AAA

A

PIN NAMES

A Address Inputs. . . . . . . . . . . . . . . . . . . .

W

Q

E

D Data Input. . . . . . . . . . . . . . . . . . . . . . . .

Q Data Output. . . . . . . . . . . . . . . . . . . . .

NC No Connection. . . . . . . . . . . . . . . . . .

V

CC

V

SS

*If not used for no connect, then do not ex-

ceed voltages of – 0.5 to VCC + 0.5 V.
This pin is used for manufacturing diag­nostics.

Write Enable. . . . . . . . . . . . . . . . . . . . .

Chip Enable. . . . . . . . . . . . . . . . . . . . . .

+ 5 V Power Supply. . . . . . . . . . . . .

Ground. . . . . . . . . . . . . . . . . . . . . . .

MCM6227B

1

TRUTH TABLE

E W Mode I/O Pin Cycle Current

H X Not Selected High–Z — I
L H Read D
L L Write High–Z Write I

H = High, L = Low, X = Don’t Care

out

Read I

SB1

, I

CCA
CCA

SB2

ABSOLUTE MAXIMUM RATINGS (See Note)

Rating

Power Supply Voltage Relative to V
Voltage Relative to VSS for Any Pin

Except V

Output Current I
Power Dissipation P

Temperature Under Bias T
Operating Temperature T
Storage Temperature T

NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are

CC

exceeded. Functional operation should be restricted to RECOMMENDED OPER­ATING CONDITIONS. Exposure to higher than recommended voltages for
extended periods of time could affect device reliability.

SS

Symbol V alue Unit

V

CC

Vin, V

out

bias

stg

out

D

A

– 0.5 to 7.0 V

– 0.5 to VCC + 0.5 V

± 20

1.1 W

– 10 to + 85 °C

0 to + 70 °C

– 55 to + 150 °C

mA

This device contains circuitry to protect the
inputs against damage due to high static volt­ages or electric fields; however, it is advised
that normal precautions be taken to avoid
application of any voltage higher than maxi­mum rated voltages to these high–impedance
circuits.

This CMOS memory circuit has been de­signed to meet the dc and ac specifications
shown in the tables, after thermal equilibrium
has been established. The circuit is in a test
socket or mounted on a printed circuit board
and transverse air flow of at least 500 linear feet
per minute is maintained.

DC OPERA TING CONDITIONS AND CHARACTERISTICS

(VCC = 5.0 V ± 10%, TA = 0 to 70°C, Unless Otherwise Noted)

RECOMMENDED OPERATING CONDITIONS

Parameter Symbol Min Max Unit

Supply Voltage (Operating Voltage Range) V
Input High Voltage V
Input Low Voltage V

*VIL (min) = – 0.5 V dc; VIL (min) = – 2.0 V ac (pulse width ≤ 20 ns).

**VIH (max) = VCC + 0.3 V dc; VIH (max) = VCC + 2 V ac (pulse width ≤ 20 ns).

DC CHARACTERISTICS AND SUPPLY CURRENTS

Parameter Symbol Min Max Unit

Input Leakage Current (All Inputs, Vin = 0 to VCC) I
Output Leakage Current (E = VIH, V
AC Active Supply Current (I

AC Standby Current (VCC = max, E = VIH, f ≤ f

CMOS Standby Current (E ≥ VCC – 0.2 V, Vin ≤ VSS + 0.2 V
or ≥ VCC – 0.2 V, VCC = max, f = 0 MHz)

Output Low Voltage (IOL = + 8.0 mA) V
Output High Voltage (IOH = – 4.0 mA) V

out

= 0 to VCC) I

out

= 0 mA, VCC = max)

max

)

MCM6227B–15: t
MCM6227B–17: t
MCM6227B–20: t
MCM6227B–25: t
MCM6227B–35: t

MCM6227B–15: t
MCM6227B–17: t
MCM6227B–20: t
MCM6227B–25: t
MCM6227B–35: t

AVAV
AVAV
AVAV
AVAV
AVAV

AVAV
AVAV
AVAV
AVAV
AVAV

= 15 ns
= 17 ns
= 20 ns
= 25 ns
= 35 ns

= 15 ns
= 17 ns
= 20 ns
= 25 ns
= 35 ns

CC

IH

IL

lkg(I)

lkg(O)
I

CCA

I

SB1

I

SB2

OL
OH

4.5 5.5 V

2.2 VCC +0.3** V

– 0.5* 0.8 V

— ± 1 µA
— ± 1 µA

—
—
—
—
—

—
—
—
—
—

— 5 mA

— 0.4 V

2.4 — V

115
110
105
100

95

40
35
30
25
20

mA

mA

MCM6227B
2

MOTOROLA FAST SRAM

CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, T

Input Capacitance All Inputs Except Clocks and D, Q

Input and Output Capacitance D, Q Cin, C

= 25°C, Periodically Sampled Rather Than 100% Tested)

A

Characteristic

E

and W

Symbol Typ Max Unit

C

in

out

4
5

5 8 pF

6
8

AC OPERA TING CONDITIONS AND CHARACTERISTICS

(VCC = 5.0 V ± 10%, TA = 0 to + 70°C, Unless Otherwise Noted)

Input Pulse Levels 0 to 3.0 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input Rise/Fall Time 2 ns. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input Timing Measurement Reference Level 1.5 V. . . . . . . . . . . . . . .

READ CYCLE TIMING (See Notes 1 and 2)

6227B–15 6227B–17 6227B–20 6227B–25 6227B–35

Parameter Symbol Min Max Min Max Min Max Min Max Min Max Unit Notes

Read Cycle Time t
Address Access Time t
Enable Access Time t
Output Hold from

Address Change
Enable Low to Output

Active
Enable High to Output

High–Z

NOTES:

1. W

is high for read cycle.

2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus con­tention conditions during read and write cycles.

3. All timings are referenced from the last valid address to the first transitioning address.

4. Addresses valid prior to or coincident with E

5. At any given voltage and temperature, t

6. Transition is measured ± 500 mV from steady–state voltage with load of Figure 1b.

7. This parameter is sampled and not 100% tested.

8. Device is continuously selected (E

AVAV
AVQV
ELQV

t

AXQX

t

ELQX

t

EHQZ

15 — 17 — 20 — 25 — 35 — ns 2, 3

— 15 — 17 — 20 — 25 — 35 ns
— 15 — 17 — 20 — 25 — 35 ns 4

5 — 5 — 5 — 5 — 5 — ns

5 — 5 — 5 — 5 — 5 — ns 5, 6, 7

— 6 — 7 — 7 — 8 — 8 ns 5, 6, 7

going low.

max is less than t

EHQZ

≤ VIL).

Output Timing Measurement Reference Level 1.5 V. . . . . . . . . . . . .

Output Load See Figure 1a. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

min, both for a given device and from device to device.

ELQX

pF

OUTPUT

Z0 = 50

Ω

(a) (b)

MOTOROLA FAST SRAM

RL = 50

VL = 1.5 V

Ω

OUTPUT

255

Ω

Figure 1. AC Test Loads

+ 5 V

480

5 pF

TIMING LIMITS

The table of timing values shows either a

minimum or a maximum limit for each param-

Ω

eter. Input requirements are specified from
the external system point of view. Thus, ad­dress setup time is shown as a minimum
since the system must supply at least that
much time. On the other hand, responses
from the memory are specified from the de­vice point of view. Thus, the access time is
shown as a maximum since the device never
provides data later than that time.

MCM6227B

3

A (ADDRESS)

READ CYCLE 1 (See Notes 1, 2, and 8)

t

AVAV

t

AXQX

Q (DATA OUT)

A (ADDRESS)

E

(CHIP ENABLE)

Q (DATA OUT)

I

SUPPLY CURRENT

CC

I

SB

HIGH–Z

t

AVQV

READ CYCLE 2 (See Note 4)

t

AVAV

t

ELQV

t

ELQX

t

AVQV

t

ELICCH

DATA VALID

DATA VALIDPREVIOUS DATA VALID

t

EHQZ

t

EHICCL

MCM6227B
4

MOTOROLA FAST SRAM

WRITE CYCLE 1 (W Controlled, See Notes 1 and 2)

6227B–15 6227B–17 6227B–20 6227B–25 6227B–35

Parameter Symbol Min Max Min Max Min Max Min Max Min Max Unit Notes

Write Cycle Time t
Address Setup Time t
Address Valid to End of

Write
Write Pulse Width t

Data Valid to End of
Write

Data Hold TIme t
Write Low to Data

High–Z
Write High to Output

Active
Write Recovery Time t

NOTES:

1. A write occurs during the overlap of E

2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus con­tention conditions during read and write cycles.

3. All timings are referenced from the last valid address to the first transitioning address.

4. Transition is measured ± 500 mV from steady–state voltage with load of Figure 1b.

5. This parameter is sampled and not 100% tested.

6. At any given voltage and temperature, t

AVAV

AVWL

t

AVWH

WLWH,
t

WLEH

t

DVWH

WHDX

t

WLQZ

t

WHQX

WHAX

15 — 17 — 20 — 25 — 35 — ns 3

0 — 0 — 0 — 0 — 0 — ns

12 — 14 — 15 — 17 — 20 — ns

12 — 14 — 15 — 17 — 20 — ns

7 — 8 — 8 — 10 — 11 — ns

0 — 0 — 0 — 0 — 0 — ns

— 6 — 7 — 7 — 8 — 8 ns 4, 5, 6

5 — 5 — 5 — 5 — 5 — ns 4, 5, 6

0 — 0 — 0 — 0 — 0 — ns

low and W low.

max is less than t

WLQZ

min both for a given device and from device to device.

WHQX

A (ADDRESS)

E

(CHIP ENABLE)

W

(WRITE ENABLE)

D (DATA IN)

Q (DATA OUT)

WRITE CYCLE 1 (W Controlled See Notes 1 and 2)

t

AVAV

t

AVWH

t

WLWH

t

WLEH

t

AVWL

t

WLQZ

HIGH–Z HIGH–Z

t

DVWH

DATA VALID

t

WHAX

t

WHDX

t

WHQX

MOTOROLA FAST SRAM

MCM6227B

5

WRITE CYCLE 2 (E Controlled, See Notes 1 and 2)

6227B–15 6227B–17 6227B–20 6227B–25 6227B–35

Parameter Symbol Min Max Min Max Min Max Min Max Min Max Unit Notes

Write Cycle Time t
Address Setup Time t
Address Valid to End of

Write
Enable to End of Write t

Write Pulse Width t
Data Valid to End of

Write
Data Hold Time t
Write Recovery Time t

NOTES:

1. A write occurs during the overlap of E

2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus con­tention conditions during read and write cycles.

3. All timings are referenced from the last valid address to the first transitioning address.

4. If E

goes low coincident with or after W goes low, the output will remain in a high–impedance state.

5. If E

goes high coincident with or before W goes high, the output will remain in a high–impedance state.

AVAV
AVEL

t

AVEH

ELEH,

t

ELWH
WLEH

t

DVEH

EHDX
EHAX

15 — 17 — 20 — 25 — 35 — ns 3

0 — 0 — 0 — 0 — 0 — ns

12 — 14 — 15 — 17 — 20 — ns

10 — 11 — 12 — 15 — 20 — ns 4, 5

12 — 14 — 15 — 17 — 20 — ns

7 — 8 — 8 — 10 — 11 — ns

0 — 0 — 0 — 0 — 0 — ns
0 — 0 — 0 — 0 — 0 — ns

low and W low.

WRITE CYCLE 2 (E Controlled See Notes 1 and 2)

t

AVAV

A (ADDRESS)

E

(CHIP ENABLE)

(WRITE ENABLE)

W

D (DATA IN)

Q (DATA OUT)

Motorola Memory Prefix
Part Number

t

AVEL

HIGH–Z

ORDERING INFORMATION

(Order by Full Part Number)

MCM 6227B XX XX XX

t

AVEH

t

ELEH

t

EHDX

t

t

ELWH

t

WLEH

t

DVEH

DATA VALID

Shipping Method (R2 = Tape and Reel, Blank = Rails)

Speed (15 = 15 ns, 17 = 17 ns, 20 = 20 ns,
25 = 25 ns, 35 = 35 ns)

Package (J = 300 mil SOJ, WJ = 400 mil SOJ)

EHAX

Full Part Numbers — MCM6227BJ15 MCM6227BJ15R2 MCM6227BWJ15 MCM6227BWJ15R2

MCM6227BJ17 MCM6227BJ17R2 MCM6227BWJ17 MCM6227BWJ17R2
MCM6227BJ20 MCM6227BJ20R2 MCM6227BWJ20 MCM6227BWJ20R2
MCM6227BJ25 MCM6227BJ25R2 MCM6227BWJ25 MCM6227BWJ25R2
MCM6227BJ35 MCM6227BJ35R2 MCM6227BWJ35 MCM6227BWJ35R2

MCM6227B
6

MOTOROLA FAST SRAM

P ACKAGE DIMENSIONS

28 LEAD

400 MIL SOJ

CASE 810–03

28 LEAD

300 MIL SOJ

CASE 810B–03

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. DIMENSION A & B DO NOT INCLUDE MOLD
PROTRUSION. MOLD PROTRUSION SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.

3. CONTROLLING DIMENSION: INCH.

4. DIM R TO BE DETERMINED AT DATUM -T-.

MILLIMETERS INCHES

MIN MINMAX MAX

DIM

A
B
C
D

G
H
K

M
N

R

E
F

L

P

S

18.29

10.04

3.26

0.39

2.24

0.67

1.27 BSC

—

0.89

0.64 BSC

0

°

0.76

11.05

9.15

0.77

18.54

10.28

3.75

0.50

2.48

0.81

0.50

1.14

5

°

1.14

11.30

9.65

1.01

0.720

0.395

0.128

0.015

0.088

0.026

0.050 BSC
—

0.035

0.025 BSC

0

°

0.030

0.435

0.360

0.030

0.730

0.405

0.148

0.020

0.098

0.032

0.020

0.045

5

°

0.045

0.445

0.380

0.040

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

F

DETAIL Z

28

1

15

14

N

D

24 PL

0.18 (0.007)MTSA

P

-B-

S

C

E

-A-

H BRK

0.18 (0.007) TSB

L

M

G

M

0.10 (0.004)

K

DETAIL Z

SEATING PLANE

-T­R

0.25 (0.010) TSB

S

S RAD

Y14.5M, 1982.

2. DIMENSION A & B DO NOT INCLUDE MOLD
PROTRUSION. MOLD PROTRUSION SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.

3. CONTROLLING DIMENSION: INCH.

4. DIM R TO BE DETERMINED AT DATUM -T-.

5. 810B-01 AND -02 OBSOLETE, NEW STANDARD
810B-03.

MILLIMETERS INCHES

MIN MINMAX MAX

DIM

M
N
P
R
S

18.29

7.50

3.26

0.39

2.24

0.67

1.27 BSC
—

0.89

0.64 BSC

0

°

0.76

8.38

6.60

0.77

18.54

7.74

3.75

0.50

2.48

0.81

0.50

1.14

10

1.14

8.64

6.86

1.01

°

A
B
C
D
E
F
G
H
K
L

0.720

0.295

0.128

0.015

0.088

0.026

0.050 BSC
—

0.035

0.025 BSC

0

°

0.030

0.330

0.260

0.030

0.730

0.305

0.148

0.020

0.098

0.032

0.020

0.045

10

0.045

0.340

0.270

0.040

°

MOTOROLA FAST SRAM

MCM6227B

7

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty , representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. “T ypical” parameters which may be provided in Motorola
data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”
must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of
others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other
applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury
or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal
Opportunity/Affirmative Action Employer.

How to reach us:
USA/EUROPE/ Locations Not Listed: Motorola Literature Distribution; JAPAN: Nippon Motorola Ltd.: SPD, Strategic Planning Office, 4–32–1,

P.O. Box 5405, Denver, Colorado 80217. 303–675–2140 or 1–800–441–2447 Nishi–Gotanda, Shinagawa–ku, Tokyo 141, Japan. 81–3–5487–8488

Mfax: [e-mail] – TOUCHTONE 602–244–6609 ASIA/P ACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park,

– US & Canada ONLY 1–800–774–1848 51 Ting Kok Road, T ai Po, N.T., Hong Kong. 852–26629298

INTERNET: http://motorola.com/sps

Mfax is a trademark of Motorola, Inc.

MCM6227B
8

◊

MOTOROLA FAST SRAM

MCM6227B/D