Datasheet MCM6206BBEJ25, MCM6206BBEJ25R, MCM6206BBEJ12R, MCM6206BBEJ15R, MCM6206BBEJ20 Datasheet (Motorola)

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Product Preview

32K x 8 Bit Fast Static RAM

The MCM6206BB is a 262,144 bit static random access memory organized as
32,768 words of 8 bits. Static design eliminates the need for external clocks or
timing strobes, while CMOS circuitry reduces power consumption and provides
for greater reliability .

This device meets JEDEC standards for functionality and pinout, and is avail­able in plastic small–outline J–leaded packages.

• Single 5 V ± 10% Power Supply

• Fully Static — No Clock or Timing Strobes Necessary

• Fast Access Times: 12/15/20/25 ns

• Equal Address and Chip Enable Access Times

• Output Enable (G

Eliminate Bus Contention Problems

• Low Power Operation: 125 – 140 mA Maximum AC

• Fully TTL Compatible — Three State Output

A
A
A
A
A
A
A
A
A

DQ

DQ

) Feature for Increased System Flexibility and to

BLOCK DIAGRAM

ROW

DECODER

INPUT

DATA

CONTROL

.

.

.

MEMORY MATRIX

COLUMN I/O

COLUMN DECODER

V

CC

V

SS

Order this document

by MCM6206BB/D

MCM6206BB

J PACKAGE

300 MIL SOJ

CASE

810B–03

PIN ASSIGNMENT

A

1
2

A

3

A

4

A

5

A

6

A

7

A

8

A

9

A

10

A

11

DQ

12

DQ

13

DQ

14

V

SS

PIN NAMES

A Address Input. . . . . . . . . . . . . . . . . . . .

DQ Data Input/Data Output. . . . . . . . . .

W
G
E
V

CC

V

SS

28

V
27
26
25
24
23
22
21
20

E
19

18
17
16
15

Write Enable. . . . . . . . . . . . . . . . . . . .

Output Enable. . . . . . . . . . . . . . . . . . .

Power Supply (+ 5 V). . . . . . . . . . .

Chip Enable. . . . . . . . . . . . . . . . . . . . . .

CC

W
A
A
A
A

G
A

DQ
DQ
DQ
DQ
DQ

Ground. . . . . . . . . . . . . . . . . . . . . . .

E

CIRCUIT

W

CONTROL

G

This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.

6/4/97

 Motorola, Inc. 1997

MOTOROLA FAST SRAM

AAAAAA

MCM6206BB

1

TRUTH TABLE (X = Don’t Care)

G W Mode VCC Current Output Cycle

E

H X X Not Selected I

L H H Output Disabled I
L L H Read I
L X L Write I

SB1

, I

CCA
CCA
CCA

SB2

High–Z –
High–Z –

D

out

High–Z Write Cycle

Read Cycle

ABSOLUTE MAXIMUM RATINGS

Rating Symbol Value Unit

Power Supply Voltage V
Voltage Relative to VSS For Any Pin

Except V
Output Current I
Power Dissipation P
Temperature Under Bias T
Ambient Temperature T
Storage Temperature—Plastic T

NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are

CC

exceeded. Functional operation should be restricted to RECOMMENDED OPER­ATING CONDITIONS. Exposure to higher than recommended voltages for ex­tended periods of time could affect device reliability.

CC

Vin, V

out

bias

stg

out

D

A

– 0.5 to + 7.0 V

– 0.5 to VCC + 0.5 V

± 20 mA

1.0 W

– 10 to + 85 °C

0 to + 70 °C

– 55 to + 125 °C

This device contains circuitry to protect the
inputs against damage due to high static volt­ages or electric fields; however, it is advised
that normal precautions be taken to avoid
application of any voltage higher than maxi­mum rated voltages to this high–impedance
circuit.

This CMOS memory circuit has been de­signed to meet the dc and ac specifications
shown in the tables, after thermal equilibrium
has been established. The circuit is in a test
socket or mounted on a printed circuit board
and transverse air flow of at least 500 linear
feet per minute is maintained.

DC OPERA TING CONDITIONS AND CHARACTERISTICS

(VCC = 5.0 V ±10%, TA = 0 to 70°C, Unless Otherwise Noted)

RECOMMENDED OPERATING CONDITIONS

Parameter Symbol Min Typ Max Unit

Supply Voltage (Operating Voltage Range) V
Input High Voltage V
Input Low Voltage V

*VIL (min) = – 0.5 V dc; VIL (min) = – 2.0 V ac (pulse width ≤ 20 ns)

**VIH (max) = VCC + 0.3 V dc; VIH (max) = VCC + 2.0 V ac (pulse width ≤ 20 ns)

DC CHARACTERISTICS

Parameter Symbol Min Max Unit

Input Leakage Current (All Inputs, Vin = 0 to VCC) I
Output Leakage Current (E = VIH or G = VIH, V
Output High Voltage (IOH = – 4.0 mA) V
Output Low Voltage (IOL = 8.0 mA) V

= 0 to VCC) I

out

POWER SUPPLY CURRENTS

Parameter Symbol –12 –15 –20 –25 Unit

AC Active Supply Current (I
AC Standby Current (E = VIH, VCC = Max, f = f
CMOS Standby Current (VCC = Max, f = 0 MHz, E ≥ VCC – 0.2 V

Vin ≤ VSS + 0.2 V, or ≥ VCC – 0.2 V)

out = 0 mA, VCC

= Max, f = f

max)

) I

max

CC

IH

IL

4.5 5.0 5.5 V

2.2 —

– 0.5*

lkg(I)

lkg(O)

OH

OL

CCA

I

SB1

I

SB2

— 0.8 V

— ± 1 µA
— ± 1 µA

2.4 — V
— 0.4 V

140 135 130 125 mA

40 35 35 30 mA
10 10 10 10 mA

VCC + 0.3**

V

CAPACITANCE (f = 1 MHz, dV = 3 V, T

Address Input Capacitance C
Control Pin Input Capacitance (E, G, W) C
I/O Capacitance C

= 25°C, Periodically sampled rather than 100% tested)

A

Characteristic

MCM6206BB
2

Symbol Max Unit

in
in

I/O

6 pF
8 pF
8 pF

MOTOROLA FAST SRAM

AC OPERA TING CONDITIONS AND CHARACTERISTICS

(VCC = 5.0 V ± 10%, TA = 0 to + 70°C, Unless Otherwise Noted)

Input Timing Measurement Reference Level 1.5 V. . . . . . . . . . . . . . .

Input Pulse Levels 0 to 3.0 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input Rise/Fall Time 5 ns. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

READ CYCLE (See Note 1)

–12 –15 –20 –25

Parameter Symbol Min Max Min Max Min Max Min Max Unit Notes

Read Cycle Time t
Address Access Time t
Enable Access Time t
Output Enable Access Time t
Output Hold from Address Change t
Enable Low to Output Active t
Enable High to Output High–Z t
Output Enable Low to Output Active t
Output Enable High to Output High–Z t
Power Up Time t
Power Down Time t

NOTES:

1. W

is high for read cycle.

2. All timings are referenced from the last valid address to the first transitioning address.

3. Addresses valid prior to or coincident with E

4. At any given voltage and temperature, t
device and from device to device.

5. Transition is measured ±500 mV from steady–state voltage.

6. This parameter is sampled and not 100% tested.

7. Device is continuously selected (E

AVAV
AVQV
ELQV
GLQV
AXQX
ELQX
EHQZ
GLQX

GHQZ
ELICCH
EHICCL

EHQZ

= VIL, G = VIL).

12 — 15 — 20 — 25 — ns 2
— 12 — 15 — 20 — 25 ns
— 12 — 15 — 20 — 25 ns 3
— 6 — 8 — 10 — 12 ns

3 — 3 — 3 — 3 — ns 4,5,6
4 — 4 — 4 — 4 — ns 4,5,6

— 7 — 8 — 9 — 10 ns 4,5,6

0 — 0 — 0 — 0 — ns 4,5,6

— 6 — 7 — 8 — 10 ns 4,5,6

0 — 0 — 0 — 0 — ns

— 12 — 15 — 20 — 25 ns

going low.

(max) is less than t

Output Timing Measurement Reference Level 1.5 V. . . . . . . . . . . . .

Output Load Figure 1 Unless Otherwise Noted. . . . . . . . . . . . . . . . . .

(min), and t

ELQX

(max) is less than t

GHQZ

(min), both for a given

GLQX

OUTPUT

MOTOROLA FAST SRAM

Z0 = 50

Ω

50

Ω

VL = 1.5 V

Figure 1. AC Test Loads

TIMING LIMITS

The table of timing values shows either a
minimum or a maximum limit for each param­eter. Input requirements are specified from
the external system point of view. Thus, ad­dress setup time is shown as a minimum
since the system must supply at least that
much time. On the other hand, responses
from the memory are specified from the de­vice point of view. Thus, the access time is
shown as a maximum since the device never
provides data later than that time.

MCM6206BB

3

A (ADDRESS)

READ CYCLE 1 (See Note 7)

t

AXQX

t

AVAV

Q (DATA OUT)

A (ADDRESS)

E (CHIP ENABLE)

G (OUTPUT ENABLE)

Q (DATA OUT)

I

V

CC

SUPPLY CURRENT

CC

I

SB

DATA VALIDPREVIOUS DATA V ALID

t

AVQV

READ CYCLE 2 (See Note 3)

t

AVAV

t

AVQV

t

ELQV

t

EHQZ

t

ELQX

t

GLQV

t

HIGH Z HIGH Z

t

ELICCH

GLQX

DATA VALID

t

GHQZ

t

EHICCL

MCM6206BB
4

MOTOROLA FAST SRAM

WRITE CYCLE 1 (W Controlled, See Notes 1 and 2)

–12 –15 –20 –25

Parameter Symbol Min Max Min Max Min Max Min Max Unit Notes

Write Cycle Time t
Address Setup Time t
Address Valid to End of W rite t
Write Pulse Width t

Write Pulse Width,
G

High
Data Valid to End of W rite t
Data Hold Time t
Write Low to Output High–Z t
Write High to Output Active t
Write Recovery Time t

NOTES:

1. A write occurs during the overlap of E

2. If G

goes low coincident with or after W goes low, the output will remain in a high impedance state.

3. All timings are referenced from the last valid address to the first transitioning address.

4. If G

≥ VIH, the output will remain in a high impedance state.

5. At any given voltage and temperature, t

6. Transition is measured ±500 mV from steady–state voltage.

7. This parameter is sampled and not 100% tested.

AVAV

AVWL

AVWH

WLWH
t

WLEH

t

WLWH
t

WLEH
DVWH
WHDX

WLQZ
WHQX
WHAX

low and W low.

WLQZ

12 — 15 — 20 — 25 — ns 3

0 — 0 — 0 — 0 — ns

10 — 12 — 15 — 20 — ns

,

10 — 12 — 15 — 20 — ns

,

10 — 10 — 12 — 15 — ns 4

6 — 7 — 8 — 10 — ns
0 — 0 — 0 — 0 — ns

— 6 — 7 — 8 — 10 ns 5,6,7

2 — 2 — 2 — 2 — ns 5,6,7
0 — 0 — 0 — 0 — ns

(max) is less than t

(min), both for a given device and from device to device.

WHQX

A (ADDRESS)

E

(CHIP ENABLE)

W

(WRITE ENABLE)

D (DATA IN)

Q (DATA OUT)

WRITE CYCLE 1 (W Controlled, See Notes 1 and 2)

t

AVAV

t

AVWH

t

WLWH

t

WLEH

t

DVWH

DATA VALID

HIGH Z

HIGH Z

t

AVWL

t

WLQZ

t

WHAX

t

WHDX

t

WHQX

MOTOROLA FAST SRAM

MCM6206BB

5

WRITE CYCLE 2 (E Controlled, See Note 1)

–12 –15 –20 –25

Parameter Symbol Min Max Min Max Min Max Min Max Unit Notes

Write Cycle Time t
Address Setup Time t
Address Valid to End of W rite t
Enable to End of Write t

Data Valid to End of W rite t
Data Hold Time t
Write Recovery Time t

NOTES:

1. A write occurs during the overlap of E

2. All timings are referenced from the last valid address to the first transitioning address.

3. If E

goes low coincident with or after W goes low, the output will remain in a high impedance state.

4. If E

goes high coincident with or before W goes high, the output will remain in a high impedance state.

AVAV
AVEL

AVEH

ELEH

t

ELWH
DVEH
EHDX
EHAX

low and W low.

12 — 15 — 20 — 25 — ns

0 — 0 — 0 — 0 — ns

10 — 12 — 15 — 20 — ns

,

9 — 10 — 12 — 15 — ns 3,4

6 — 7 — 8 — 10 — ns
0 — 0 — 0 — 0 — ns
0 — 0 — 0 — 0 — ns

WRITE CYCLE 2 (E Controlled, See Note 1)

t

AVAV

A (ADDRESS)

E

(CHIP ENABLE)

W (WRITE ENABLE)

D (DATA IN)

Q (DATA OUT)

t

AVEL

t

AVEH

HIGH Z

t

WLEH

t

ELEH

t

ELWH

t

DVEH

DATA VALID

t

EHDX

t

EHAX

MCM6206BB
6

MOTOROLA FAST SRAM

Motorola Memory Prefix
Part Number

ORDERING INFORMATION

(Order by Full Part Number)

MCM 6206BB EJ XX X

Shipping Method (R = Tape and Reel, Blank = Rails)
Speed (12 = 12 ns, 15 = 15 ns, 20 = 20 ns,

25 = 25 ns)
Package (J = 300 mil SOJ, E = Evolutionary Pinout)

Full Part Numbers — MCM6206BBEJ12 MCM6206BBEJ12R

MCM6206BBEJ15 MCM6206BBEJ15R
MCM6206BBEJ20 MCM6206BBEJ20R
MCM6206BBEJ25 MCM6206BBEJ25R

MOTOROLA FAST SRAM

MCM6206BB

7

P ACKAGE DIMENSIONS

CASE 810B–03

300 MIL SOJ

28 LEAD

F

DETAIL Z

28

1

-A-

M

15

14

L

G

H BRK

N

24 PL

D

0.18 (0.007) T A

M

0.18 (0.007) T B

S

S S

P

-B-

M

E

0.10 (0.004)

K

DETAIL Z

SEATING PLANE

-T­R

0.25 (0.010) T B

S S

S RAD

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. DIMENSION A & B DO NOT INCLUDE MOLD
PROTRUSION. MOLD PROTRUSION SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.

3. CONTROLLING DIMENSION: INCH.

4. DIM R TO BE DETERMINED AT DATUM -T-.

INCHES MILLIMETERS

MIN MINMAX MAX

DIM

A
B
C
D
E
F
G

C

H
K
L
M
N
P
R
S

0.720

0.295

0.128

0.015

0.088

0.026

0.050 BSC
—

0.035

0.025 BSC

0°10

0.030

0.330

0.260

0.030

0.730

0.305

0.148

0.020

0.098

0.032

0.020

0.045

0.045

0.340

0.270

0.040

18.29

°

7.50

3.26

0.39

2.24

0.67

1.27 BSC
—

0.89

0.64 BSC

0°10

0.76

8.38

6.60

0.77

18.54

7.74

3.75

0.50

2.48

0.81

0.50

1.14

1.14

8.64

6.86

1.01

°

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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
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MCM6206BB

◊

MOTOROLA FAST SRAM

MCM6206BB/D

8