Datasheet MC88LV926DW Datasheet (Motorola)

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SEMICONDUCTOR TECHNICAL DATA

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 

The MC88LV926 Clock Driver utilizes phase–locked loop technology
to lock its low skew outputs’ frequency and phase onto an input reference
clock. It is designed to provide clock distribution for CISC microprocessor
or single processor RISC systems. The RST
provide a processor reset function designed specifically for the
MC68/EC/LC030/040/060 microprocessor family. To support the 68060
processor, the 88LV926 operates from a 3.3V as well as a 5.0V supply.

The PLL allows the high current, low skew outputs to lock onto a single
clock input and distribute it with essentially zero delay to multiple
locations on a board. The PLL also allows the MC88LV926 to multiply a
low frequency input clock and distribute it locally at a higher (2X) system
frequency.

• 2X_Q Output Meets All Requirements of the 50 and 66MHz 68060

Microprocessor PCLK Input Specifications

• Low Voltage 3.3V V

CC

• Three Outputs (Q0–Q2) With Output–Output Skew <500ps

• CLKEN Output for Half Speed Bus Applications

• The Phase Variation From Part–to–Part Between SYNC and the ‘Q’

Outputs Is Less Than 600ps (Derived From the TPD Specification,
Which Defines the Part–to–Part Skew)

• SYNC Input Frequency Range From 5MHZ to 2X_Q F

• All Outputs Have ±36mA Drive (Equal High and Low) CMOS Levels

• Can Drive Either CMOS or TTL Inputs. All Inputs Are TTL–Level Compatible

• Test Mode Pin (PLL_EN) Provided for Low Frequency Testing

_IN/RST_OUT(LOCK) pins

/4

Max



LOW SKEW CMOS PLL

68060 CLOCK DRIVER

20

1

DW SUFFIX

PLASTIC SOIC PACKAGE

CASE 751D–04

Three ‘Q’ outputs (Q0–Q2) are provided with less than 500ps skew between their rising edges. A 2X_Q output runs at twice
the ‘Q’ output frequency . The 2X_Q output is ideal for 68060 systems which require a 2X processor clock input, and it meets the
tight duty cycle spec of the 50 and 66MHz 68060. The QCLKEN output is designed to drive the CLKEN
the bus logic runs at half of the microprocessor clock rate. The QCLKEN output is skewed relative to the 2X_Q output to ensure
that CLKEN
multiplication from the ‘Q’ outputs to the SYNC input. Since the feedback is done internally (no external feedback pin is provided)
the input/output frequency relationships are fixed. The Q3
tree design.

In normal phase–locked operation the PLL_EN pin is held high. Pulling the PLL_EN pin low disables the VCO and puts the
88LV926 in a static ‘test mode’. In this mode there is no frequency limitation on the input clock, which is necessary for a low
frequency board test environment.

The RST
pin will be pulled actively low until phase–lock is achieved. When phase–lock occurs, the RST_OUT(LOCK) is released and a
pull–up resistor will pull the signal high. To give a processor reset signal, the RST
RST

_OUT(LOCK) pin will stay low for 1024 cycles of the ‘Q’ output frequency after the RST_IN pin is brought back high.

Description of the RST

The RST
acting as a lock indicator. If the RST
steady state phase/frequency lock to the input reference is achieved. 1024 ‘Q’ output cycles after phase–lock is achieved the
RST

_OUT(LOCK) pin will go into a high impedance state, allowing it to be pulled high by an external pull–up resistor (see the
AC/DC specs for the characteristics of the RST
RST

_OUT(LOCK) pin will remain low.

1/96

 Motorola, Inc. 1996

setup and hold times of the 68060 are satisfied. A Q/2 frequency is fed back internally, providing a fixed 2X

output provides an inverted clock output to allow flexibility in the clock

_OUT(LOCK) pin doubles as a phase–lock indicator. When the RST_IN pin is held high, the open drain RST_OUT

_IN pin is toggled low, and the

_IN/RST_OUT(LOCK) Functionality

_IN and RST_OUT(LOCK) pins provide a 68030/040/060 processor reset function, with the RST_OUT pin also

_IN pin is held high during system power–up, the RST_OUT pin will be in the low state until

_OUT(LOCK) pin). If the RST_IN pin is held low during power–up, the

1

REV 3

input of the 68060 when

MC88LV926

Pinout: 20–Lead Wide SOIC Package (Top View)

1

2

CC

3

Q0

4

5

6

7

8

9

10

RST_IN

Description of the RST_IN/RST_OUT(LOCK) Functionality (continued)

After the system start–up is complete and the 88LV926 is

phase–locked to the SYNC input signal (RST

_OUT high), the
processor reset functionality can be utilized. When the
RST

_IN pin is toggled low (min. pulse width=10nS),

RST

_OUT(LOCK) will go to the low state and remain there
for 1024 cycles of the ‘Q’ output frequency (512 SYNC
cycles). During the time in which the RST

_OUT(LOCK) is
actively pulled low, all the 88LV926 clock outputs will
continue operating correctly and in a locked condition to the
SYNC input (clock signals to the 68030/040/060 family of
processors must continue while the processor is in reset). A
propagation delay after the 1024th cycle RST

_OUT(LOCK)
goes back to the high impedance state to be pulled high by
the resistor.

phase–lock to the reference source, some constraints must
be placed on the power supply ramp rate to make sure the
RST

_OUT(LOCK) signal holds the processor in reset during
system start–up (power–up). With the recommended loop
filter values (see Figure 6.) the lock time is approximately
10ms. The phase–lock loop will begin attempting to lock to a
reference source (if it is present) when VCC reaches 2V. If
the VCC ramp rate is significantly slower than 10ms, then the
PLL could lock to the reference source, causing
RST

_OUT(LOCK) to go high before the 88LV926 and
’030/040 processor is fully powered up, violating the
processor reset specification. Therefore, if it is necessary for
the RST
ramp rate must be less than 10mS for proper 68030/040/060
reset operation.

Power Supply Ramp Rate Restriction for Correct 030/040
Processor Reset Operation During System Start–up

Because the RST_OUT(LOCK) pin is an indicator of

This ramp rate restriction can be ignored if the RST
can be held low during system start–up (which holds
RST

_OUT low). The RST_OUT(LOCK) pin will then be
pulled back high 1024 cycles after the RST

CAPACITANCE AND POWER SPECIFICATIONS

20

GNDQ3

19

2X_QV

18

QCLKENMR

17

V

CC

16

Q2VCC(AN)

15

GNDRC1

14

RST

_OUT(LOCK)GND(AN)

13

PLL_ENSYNC

12

Q1GND

11

V

CC

_IN pin to be held high during power–up, the V

_IN pin goes high.

CC

_IN pin

Symbol Parameter Value Typ Unit Test Conditions

C

IN

C

PD

PD

1

PD

2

* Value at VCC = 3.3V TBD.

MOTOROLA TIMING SOLUTIONS

Input Capacitance 4.5* pF VCC = 5.0V
Power Dissipation Capacitance 40* pF VCC = 5.0V
Power Dissipation at 33MHz With 50Ω

Thevenin Termination
Power Dissipation at 33MHz With 50Ω

Parallel Termination to GND

15mW/Output*

90mW/Device

37.5mW/Output*
225mW/Device

2

mW VCC = 5.0V

T = 25°C

mW VCC = 5.0V

T = 25°C

BR1333 — REV 5

MC88LV926

MAXIMUM RATINGS*

Symbol Parameter Limits Unit

VCC, AV
V
V
I
I
I
T

* Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the

Recommended Operating Conditions.

CC
in
out

in
out
CC

stg

RECOMMENDED OPERATING CONDITIONS

Symbol Parameter Limits Unit

V

CC

V

in

V

out

T

A

ESD Static Discharge Voltage > 1500 V

DC Supply Voltage Referenced to GND –0.5 to 7.0 V
DC Input Voltage (Referenced to GND) –0.5 to VCC +0.5 V
DC Output Voltage (Referenced to GND) –0.5 to VCC +0.5 V
DC Input Current, Per Pin ±20 mA
DC Output Sink/Source Current, Per Pin ±50 mA
DC VCC or GND Current Per Output Pin ±50 mA
Storage Temperature –65 to +150 °C

Supply Voltage 3.3 ±0.3 V
DC Input Voltage 0 to V
DC Output Voltage 0 to V
Ambient Operating Temperature 0 to 70 °C

CC
CC

V
V

DC CHARACTERISTICS (TA = 0°C to 70°C; VCC = 3.3V ± 0.3V)

Symbol Parameter V

V

IH

V

IL

V

OH

V

OL

I

IN

I

CCT

I

OLD

I

OHD

I

CC

1. IOL is +12mA for the RST_OUT output.

2. The PLL_EN input pin is not guaranteed to meet this specification.

3. Maximum test duration 2.0ms, one output loaded at a time.

4. The MC88LV926 can also be operated from a 5.0V supply. VOH output levels will vary 1:1 with VCC, input levels and current specs will be
unchanged.

Minimum High Level Input Voltage 3.0

Minimum Low Level Input Voltage 3.0

Minimum High Level Output Voltage 3.0

Minimum Low Level Output Voltage 3.0

Maximum Input Leakage Current 3.3 ±1.0 µA VI = VCC, GND
Maximum ICC/Input 3.3 2.0
Minimum Dynamic3 Output Current 3.3 88 mA V

Maximum Quiescent Supply Current 3.3 750 µA VI = VCC, GND

CC

3.3

3.3

3.3

3.3

3.3 –88 mA V

4

Guaranteed Limits Unit Condition

2.0

2.0

0.8

0.8

2.2

2.5

0.55

0.55

2

V V

V V

V VIN = VIH or V

V VIN = VIH or V

mA VI = VCC – 2.1V

= 0.1V or

OUT

VCC – 0.1V

= 0.1V or

OUT

VCC – 0.1V

I

OH –36mA

I

OH +36mA

OLD
OHD

–36mA

+36mA

= 1.0V Max

= 3.85 Min

IL

IL

1

TIMING SOLUTIONS
BR1333 — REV 5

3 MOTOROLA

MC88LV926

RST_OUT

RST_IN

SYNC1

PLL_EN

LOCK INDICAT OR

RESET_OUT

PFD

÷

8

POWER–ON

RESET

CH

PUMP

01

VCO

DELAY

Q

÷

2

R

Q

÷

4

R

Q

÷

4

R

Q

÷

4

R

Q

÷

4

R

÷

4

R

2X_Q

Q0

Q1

Q2

Q3

CLKEN

MR

Figure 1. MC88L V926 Logic Block Diagram

SYNC INPUT TIMING REQUIREMENTS

Symbol Parameter Minimum Maximum Unit

t

RISE/FALL

SYNC Input
t

,

CYCLE

SYNC Input
Duty Cycle Duty Cycle, SYNC Input 50% ± 25%

Rise/Fall Time, SYNC Input
From 0.8V to 2.0V

Input Clock Period
SYNC Input

— 5.0 ns

f

2X_Q

1

ń

4

200 ns

FREQUENCY SPECIFICATIONS (TA = 0°C to 70°C; VCC = 3.3V ± 0.3V or 5.0V ±5%)

Symbol Parameter Guaranteed Minimum Unit

Fmax (2X_Q) Maximum Operating Frequency, 2X_Q Output 66 MHz
Fmax (‘Q’) Maximum Operating Frequency,

Maximum Operating Frequency is guaranteed with the 88LV926 in a phase–locked condition.

MOTOROLA TIMING SOLUTIONS

Q0–Q3 Outputs

4

33 MHz

BR1333 — REV 5

MC88LV926

AC CHARACTERISTICS (TA = 0°C to 70°C; VCC = 3.3V ± 0.3V or 5.0V ±5%)

Symbol Parameter Mimimum Maximum Unit Condition

t

RISE/FALL

All Outputs
t

RISE/FALL

2X_Q Output
t

pulse width(a)

(Q0, Q1, Q2, Q3)

t

pulse width(b)

(2X_Q Output)

t

SKEWr

(Rising)

t

SKEWf

(Falling)

t

SKEWall

t

SKEW

t

LOCK

t

PHL

t

REC

SYNC
tW, MR LOW
tW, RST_IN LOW Minimum Pulse Width, RST_IN Low 10 — ns When in Phase–Lock
t

PZL

t

PLZ

1. These specifications are not tested, they are guaranteed by statistical characterization. See Application Note 1 for a discussion of this
methodology.

2. Under equally loaded conditions and at a fixed temperature and voltage.

3. With VCC fully powered–on: t

4. See Application Note 4 for the distribution in time of each output referenced to SYNC.

5. Specification is valid only when the PLL_EN pin is low.

6. Guaranteed that QCLKEN

1

1

1,2

1,2

1,2

QCLKEN Output–to–Output Skew

3

MR – Q Propagation Delay,

, MR to

5

5

Rise/Fall Time, into 50Ω Load 0.3 1.6 ns t

Rise/Fall Time into a 50Ω Load 0.5 1.6 ns t

1

Output Pulse Width
Q0, Q1, Q2, Q3 at 1.65V

1

Output Pulse Width
2X_Q at 1.65V

Output–to–Output Skew
Between Outputs Q0–Q2
(Rising Edge Only)

Output–to–Output Skew
Between Outputs Q0–Q2
(Falling Edge Only)

Output–to–Output Skew
2X_Q, Q0–Q2, Q3

QCLKEN to 2X_Q 2X_Q = 50MHz

Phase–Lock Acquisition Time,
All Outputs to SYNC Input

MR to Any Output (High–Low)
Reset Recovery Time rising MR edge

to falling SYNC edge
Minimum Pulse Width, MR input Low 5 — ns

Output Enable Time
RST

_IN Low to RST_OUT Low

Output Enable Time
RST_IN High to RST_OUT High Z

Max is with C1 = 0.1µF; t

CLOCK

will meet the setup and hold time requirement of the 68060.

2X_Q = 66MHz

0.5t

0.5t

1016 ‘Q’ Cycles

(508 Q/2 Cycles)

LOCK

– 0.5 0.5t

cycle

– 0.5 0.5t

cycle

— 500 ps Into a 50Ω Load

— 1.0 ns Into a 50Ω Load

— 750 ps Into a 50Ω Load

6

9.7

6

7.0

1 10 ms

1.5 13.5 ns Into a 50Ω Load

9 — ns

1.5 16.5 ns See Application

1024 ‘Q’ Cycles

(512 Q/2 Cycles)

Min is with C1 = 0.01µF.

+ 0.5 ns 50Ω Load Terminated to

cycle

+ 0.5 ns 50Ω Load Terminated to

cycle

—

ns Into a 50Ω Load

ns See Application

– 0.8V to 2.0V

RISE

t

– 2.0V to 0.8V

FALL

– 0.8V to 2.0V

RISE

t

– 2.0V to 0.8V

FALL

VCC/2 (See Application
Note 3)

VCC/2 (See Application
Note 3)

Terminated to VCC/2
(See Timing Diagram in
Figure 5.)

Terminated to VCC/2
(See Timing Diagram in
Figure 5.)

Terminated to VCC/2
(See Timing Diagram in
Figure 5.)

Terminated to VCC/2
(See Timing Diagram in
Figure 5.)

Terminated to VCC/2

Note 5

Note 5

TIMING SOLUTIONS
BR1333 — REV 5

5 MOTOROLA

MC88LV926

Application Notes

1. Several specifications can only be measured when the
MC88LV926 is in phase–locked operation. It is not
possible to have the part in phase–lock on ATE
(automated test equipment). Statistical characterization
techniques were used to guarantee those specifications
which cannot be measured on the A TE. MC88L V926 units
were fabricated with key transistor properties intentionally
varied to create a 14 cell designed experimental matrix. IC
performance was characterized over a range of transistor
properties (represented by the 14 cells) in excess of the
expected process variation of the wafer fabrication area.
Response Surface Modeling (RSM) techniques were
used to relate IC performance to the CMOS transistor
properties over operation voltage and temperature. IC
performance to each specification and fab variation were
used in conjunction with Yield Surface Modeling
(YSM) methodology to set performance limits of ATE
testable specifications within those which are to be
guaranteed by statistical characterization. In this way, all
units passing the ATE test will meet or exceed the
non–tested specifications limits.

2. A 470KΩ resistor tied to either Analog VCC or Analog
GND, as shown in Figure 2., is required to ensure no jitter
is present on the MC88LV926 outputs. This technique
causes a phase offset between the SYNC input and the
Q0 output, measured at the pins. The tPD spec describes
how this offset varies with process, temperature, and
voltage. The specs were arrived at by measuring the
phase relationship for the 14 lots described in note 1 while
the part was in phase–locked operation. The actual
measurements were made with a 10MHz SYNC input
(1.0ns edge rate from 0.8V to 2.0V). The phase
measurements were made at 1.5V. See Figure 2. for a
graphical description.

3. Two specs (t

RISE/FALL

and t

Width 2X_Q output,

PULSE

see AC Specifications) guarantee that the MC88LV926
meets the 33MHz and 66MHz 68060 P–Clock input
specification.

RC1

EXTERNAL

LOOP FILTER

WITH THE 470K
SPECIFICA TION, MEASURED AT THE INPUT PINS IS:

tPD = 2.25ns

SYNC INPUT

Q0 OUTPUT

330

Ω

R2

0.1µF

Ω

RESISTOR TIED IN THIS FASHION THE T

±

1.0ns (TYPICAL VALUES)

2.25ns

OFFSET

C1

ANALOG GND

470K
REFERENCE
RESISTOR

3V

Figure 2. Depiction of the Fixed SYNC to Q0 Offset (tPD) Which Is Present

When a 470KΩ Resistor Is Tied to VCC or Ground

5V

PD

ANALOG V

470K

REFERENCE

RESISTOR

WITH THE 470K
SPECIFICA TION, MEASURED AT THE INPUT PINS IS:

SYNC INPUT

Q0 OUTPUT

Ω

RESISTOR TIED IN THIS FASHION THE T

tPD = –0.80ns

CC

RC1

330

Ω

R2

0.1µF

ANALOG GND

±

0.30ns

–0.8ns

OFFSET

C1

5V

PD

3V

MOTOROLA TIMING SOLUTIONS

6

BR1333 — REV 5

MC88LV926

RST_OUT PIN

INTERNAL

LOGIC

ANALOG GND

V

CC

1K

C

L

Figure 3. RST_OUT Test Circuit

12.5MHz

CRYSTAL

OSCILLA T OR

SYNC

MR
PLL_EN
RST

_IN

2X_Q

QCLKEN

RST

_OUT

Q0
Q1
Q2

Q3

66MHz P–CLOCK OUT-

PUT

33MHz

B–CLOCK

AND SYSTEM

OUTPUTS

DELAY 33MHz CLKEN OUTPUT

Figure 4. Logical Representation of the MC88L V926 With Input/Output Frequency Relationships

SYNC Input

Q0–Q3 Outputs

2X_Q Output

QCLKEN

t

SKEWall

t

SKEWQCLKEN

Figure 5. Output/Input Switching Waveforms and Timing Relationships

t

SKEWf

t

SYNC Input

CYCLE

t

SKEWr

Timing Notes

t

SKEWf

t

‘Q’ Outputs

CYCLE

t

SKEWQCLKEN

t

SKEWr

1. The MC88LV926 aligns rising edges of the outputs and the SYNC input, therefore the SYNC input does not require a 50%
duty cycle.

2. All skew specs are measured between the VCC/2 crossing point of the appropriate output edges. All skews are specified as
‘windows’, not as a ± deviation around a center point.

TIMING SOLUTIONS
BR1333 — REV 5

7 MOTOROLA

MC88LV926

The tPD spec includes the full temperature range from 0°C
to 70°C and the full VCC range from 3.0V to 3.3V . If the ∆T
and ∆VCC is a given system are less than the specification
limits, the tPD spec window will be reduced. The t

PD

window for a given ∆T and ∆VCC is given by the following
regression formula:

TBD

Notes Concerning Loop Filter and Board Layout Issues

1. Figure 6. shows a loop filter and analog isolation scheme
which will be effective in most applications. The following
guidelines should be followed to ensure stable and
jitter–free operation:

1a. All loop filter and analog isolation components should be

tied as close to the package as possible. Stray current
passing through the parasitics of long traces can cause
undesirable voltage transients at the RC1 pin.

1b. The 47Ω resistors, the 10µF low frequency bypass

capacitor, and the 0.1µF high frequency bypass capacitor
form a wide bandwidth filter that will make the 88LV926
PLL insensitive to voltage transients from the system
digital VCC supply and ground planes. This filter will
typically ensure that a 100mV step deviation on the digital
VCC supply will cause no more than a 100ps phase
deviation on the 88LV926 outputs. A 250mV step
deviation on VCC using the recommended filter values
will cause no more than a 250ps phase deviation; if a
25µF bypass capacitor is used (instead of 10µF) a
250mV VCC step will cause no more than a 100ps phase
deviation.

If good bypass techniques are used on a board design
near components which may cause digital VCC and
ground noise, the above described VCC step deviations
should not occur at the 88L V926’s digital VCC supply . The

5. The RST

_OUT pin is an open drain N–Channel output.
Therefore an external pull–up resistor must be provide to
pull up the RST

_OUT pin when it goes into the high
impedance state (after the MC88LV926 is phase–locked
to the reference input with RST
cycles after the RST
locked). In the t

_IN pin goes high when the part is

and t

PLZ

_IN held high or 1024 ‘Q’

specifications, a 1KΩ resistor

PZL

is used as a pull–up as shown in Figure 3.

purpose of the bypass filtering scheme shown in Figure

6. is to give the 88LV926 additional protection from the
power supply and ground plane transients that can occur
in a high frequency, high speed digital system.

1c. There are no special requirements set forth for the loop

filter resistors (470K and 330Ω). The loop filter capacitor
(0.1uF) can be a ceramic chip capacitor, the same as a
standard bypass capacitor.

1d. The 470K reference resistor injects current into the

internal charge pump of the PLL, causing a fixed offset
between the outputs and the SYNC input. This also
prevents excessive jitter caused by inherent PLL
dead–band. If the VCO (2X_Q output) is running above
40MHz, the 470K resistor provides the correct amount of
current injection into the charge pump (2–3µA). If the
VCO is running below 40MHz, a 1MΩ reference resistor
should be used (instead of 470K).

2. In addition to the bypass capacitors used in the analog
filter of Figure 6., there should be a 0.1µF bypass
capacitor between each of the other (digital) four V

CC

pins and the board ground plane. This will reduce output
switching noise caused by the 88LV926 outputs, in
addition to reducing potential for noise in the ‘analog’
section of the chip. These bypass capacitors should also
be tied as close to the 88LV926 package as possible.

NOTE: FURTHER LOOP OPTIMIZA TION MA Y OCCUR

10µF LOW

FREQ BIAS

0.1µF HIGH
FREQ BIAS

BOARD V

47

470K

47

BOARD GND

Ω

Ω

CC

5

ANALOG V

Ω

330

6

RC1

0.1µF (LOOP
FILTER CAP)

A SEPARATE ANALOG POWER SUPPLY IS NOT NECESSARY AND
SHOULD NOT BE USED. FOLLOWING THESE PRESCRIBED GUIDE­LINES IS ALL THAT IS NECESSARY T O USE THE MC88L V926 IN A NOR­MAL DIGITAL ENVIRONMENT.

7

ANALOG GND

CC

ANALOG LOOP FILTER/VCO
SECTION OF THE MC88LV926
20–PIN SOIC PACKAGE (NOT
DRAWN TO SCALE)

Figure 6. Recommended Loop Filter and Analog Isolation Scheme for the MC88L V926

MOTOROLA TIMING SOLUTIONS

8

BR1333 — REV 5

MC88LV926

16.67MHz
X–TAL

OSCILLA TOR

SYSTEM RESET

MC68060
PCLK

CLKEN

RESET

MEMORY MODULE

SYNC

_IN

RST

2X_Q

QCLKEN

RST

_OUT

Q0
Q1
Q2

Q3

66MHz

33MHz

Figure 7. T ypical MC88LV926/MC68060 System Configuration

ASIC

ASIC

TIMING SOLUTIONS
BR1333 — REV 5

9 MOTOROLA

MC88LV926

1

-T-

-A-

G

D

20 PL

0.25 (0.010)MT

OUTLINE DIMENSIONS

DW SUFFIX

SOIC PACKAGE

CASE 751D-03

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A AND B DO NOT INCLUDE MOLD

1120

-B-

P

0.25 (0.010) B

10

10 PL

MM

R X 45°

C

SEATING
PLANE

K

S

S

A

B

M

F

J

PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER
SIDE.

5. 751D-01, AND -02 OBSOLETE, NEW STANDARD
751D-03.

MILLIMETERS INCHES

MIN MINMAX MAX

DIM

12.95

12.65

A
B
C
D
F
G

K

M

P
R

7.60

7.40

2.65

2.35

0.49

0.35

0.90

0.50

1.27 BSC 0.050 BSC

J

0.32

0.25

0.25

0.10
7

0

°

0.25

10.55

0.75

°

10.05

0.499

0.292

0.093

0.014

0.020

0.010

0.004
0

0.395

0.010

0.510

0.299

0.104

0.019

0.035

0.012

0.009
7

°

°

0.415

0.029

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty , representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “T ypical” parameters can and do vary in different
applications. All operating parameters, including “T ypicals” must be validated for each customer application by customer’s technical experts. Motorola does
not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in
systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of
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against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part.
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How to reach us:
USA/EUROPE: Motorola Literature Distribution; JAP AN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, Toshikatsu Otsuki,

P.O. Box 20912; Phoenix, Arizona 85036. 1–800–441–2447 6F Seibu–Butsuryu–Center, 3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 03–3521–8315

MFAX: [e-mail] –TOUCHTONE (602) 244–6609 HONG KONG: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park,
INTERNET: http://Design–NET .com 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298

MOTOROLA TIMING SOLUTIONS

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10

*MC88LV926/D*

MC88LV926/D

BR1333 — REV 5