Datasheet MC88916DW Datasheet (Motorola)

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SEMICONDUCTOR TECHNICAL DATA

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The MC88916 Clock Driver utilizes phase–locked loop technology to
lock its low skew outputs’ frequency and phase onto an input reference
clock. It is designed to provide clock distribution for CISC microprocessor
or single processor RISC systems. The RST
provide a processor reset function designed specifically for the
MC68/EC/LC030/040 microprocessor family. The 88916 comes in two
speed grades: 70 and 80MHz. These frequencies correspond to the
2X_Q maximum output frequency . The two grades should be ordered as
the MC88916DW70 and MC88916DW80, respectively.

• Provides Performance Required to Drive 68030 Microprocessor Family

as well as the 33 and 40MHz 68040 Microprocessors

• Three Outputs (Q0–Q2) With Output–Output Skew <500ps and Six

Outputs T otal (Q0–Q2, Q3
and Frequency Locked to the SYNC Input

, 2X_Q,) With <1ns Skew Each Being Phase

• The Phase Variation From Part–to–Part Between SYNC and the ‘Q’

Outputs Is Less Than 600ps (Derived From the TPD Specification,
Which Defines the Part–to–Part Skew)

• SYNC Input Frequency Range From 5MHZ to 2X_Q F

• Additional Outputs Available at 2X and ÷2 the System ‘Q’ Frequency.

Also a Q

(180° Phase Shift) Output Available.

• All Outputs Have ±36mA Drive (Equal High and Low) CMOS Levels.

Can Drive Either CMOS or TTL Inputs. All Inputs Are TTL–Level
Compatible

• Test Mode Pin (PLL_EN) Provided for Low Frequency Testing

_IN/RST_OUT(LOCK) pins

/4

Max

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LOW SKEW CMOS PLL

CLOCK DRIVER WITH

PROCESSOR RESET

20

1

DW SUFFIX

SOIC PACKAGE

CASE 751D–04

The PLL allows the high current, low skew outputs to lock onto a single clock input and distribute it with essentially zero delay
to multiple locations on a board. The PLL also allows the MC88916 to multiply a low frequency input clock and distribute it locally
at a higher (2X) system frequency.

Three ‘Q’ outputs (Q0–Q2) are provided with less than 500ps skew between their rising edges. The Q3
phase shift) from the ‘Q’ outputs. A 2X_Q output runs at twice the ‘Q’ output frequency. The 2X_Q output does not meet the
stringent duty cycle requirement of the 20 and 25Mhz 68040 microprocessor PCLK input. The 88920 has been designed
specifically to provide the 68040 PCLK and BCLK inputs for the low frequency 68040 microprocessor. 68040 designers should
refer to the 88920 data sheet for more details. For the 33 and 40MHz 68040, the 2X_Q output will meet the duty cycle
requirements of the PCLK input. The Q/2 output runs at 1/2 the ‘Q’ frequency . This output is fed back internally, providing a fixed
2X multiplication from the ‘Q’ outputs to the SYNC input. Since the feedback is done internally (no external feedback pin is
provided) the input/output frequency relationships are fixed.

In normal phase–locked operation the PLL_EN pin is held high. Pulling the PLL_EN pin low disables the VCO and puts the
88916 in a static ‘test mode’. In this mode there is no frequency limitation on the input clock, which is necessary for a low
frequency board test environment.

The RST
pin will be pulled actively low until phase–lock is achieved. When phase–lock occurs, the RST_OUT(LOCK) is released and a
pull–up resistor will pull the signal high. To give a processor reset signal, the RST
RST

Description of the RST_IN/RST_OUT(LOCK) Functionality

The RST
a lock indicator. If the RST
state phase/frequency lock to the input reference is achieved. 1024 ‘Q’ output cycles after phase–lock is achieved the
RST
AC/DC specs for the characteristics of the RST
RST

_OUT(LOCK) pin doubles as a phase–lock indicator. When the RST_IN pin is held high, the open drain RST_OUT

_IN pin is toggled low, and the

_OUT(LOCK) pin will stay low for 1024 cycles of the ‘Q’ output frequency after the RST_IN pin is brought back high.

_IN and RST_OUT(LOCK) pins provide a 68030/040 processor reset function, with the RST_OUT pin also acting as

_IN pin is held high during system power–up, the RST_OUT pin will be in the low state until steady

_OUT(LOCK) pin will go into a high impedance state, allowing it to be pulled high by an external pull–up resistor (see the

_OUT(LOCK) pin). If the RST_IN pin is held low during power–up, the

_OUT(LOCK) pin will remain low.

output is inverted (180°

11/93

 Motorola, Inc. 1995

1

REV 2

MC88916

1

2

CC

3

Q0

4

5

6

7

8

9

10

RST_IN

Pinout: 20–Lead Wide SOIC Package (Top View)

Description of the RST_IN/RST_OUT(LOCK) Functionality (continued)

20

19

18

17

16

15

14

13

12

11

GNDQ3

2X_QV

Q/2MR

V

CC

Q2VCC(AN)

GNDRC1

RST

PLL_ENSYNC

Q1GND

V

CC

_OUT(LOCK)GND(AN)

After the system start–up is complete and the 88916 is
phase–locked to the SYNC input signal (RST

_OUT high), the
processor reset functionality can be utilized. When the
RST

_IN pin is toggled low (min. pulse width=10nS),

RST

_OUT(LOCK) will go to the low state and remain there
for 1024 cycles of the ‘Q’ output frequency (512 SYNC
cycles). During the time in which the RST

_OUT(LOCK) is
actively pulled low, all the 88916 clock outputs will continue
operating correctly and in a locked condition to the SYNC
input (clock signals to the 68030/040 family of processors
must continue while the processor is in reset). A propagation
delay after the 1024th cycle RST

_OUT(LOCK) goes back to

the high impedance state to be pulled high by the resistor.

phase–lock to the reference source, some constraints must
be placed on the power supply ramp rate to make sure the
RST

_OUT(LOCK) signal holds the processor in reset during
system start–up (power–up). With the recommended loop
filter values (see Figure 7) the lock time is approximately
10ms. The phase–lock loop will begin attempting to lock to a
reference source (if it is present) when VCC reaches 2V. If
the VCC ramp rate is significantly slower than 10ms, then the
PLL could lock to the reference source, causing
RST

_OUT(LOCK) to go high before the 88916 and 68030
processor is fully powered up, violating the processor reset
specification. Therefore, if it is necessary for the RST
to be held high during power–up, the VCC ramp rate must be
less than 10mS for proper 68030/040 reset operation.

Power Supply Ramp Rate Restriction for Correct 68030
Processor Reset Operation During System Start–up

Because the RST_OUT(LOCK) pin is an indicator of

This ramp rate restriction can be ignored if the RST
can be held low during system start–up (which holds
RST

_OUT low). The RST_OUT(LOCK) pin will then be
pulled back high 1024 cycles after the RST

CAPACITANCE AND POWER SPECIFICATIONS

Symbol Parameter Value Typ Unit Test Conditions

C
C
PD

PD

IN
PD

1

2

Input Capacitance 4.5 pF VCC = 5.0V
Power Dissipation Capacitance 40 pF VCC = 5.0V
Power Dissipation at 33MHz With 50Ω

Thevenin Termination
Power Dissipation at 33MHz With 50Ω

Parallel Termination to GND

15mW/Output
90mW/Device

37.5mW/Output
225mW/Device

mW VCC = 5.0V

T = 25°C

mW VCC = 5.0V

T = 25°C

_IN pin

_IN pin

_IN pin goes high.

MOTOROLA TIMING SOLUTIONS

2

BR1333 — REV 5

MC88916

MAXIMUM RATINGS*

Symbol Parameter Limits Unit

VCC, AV
V
V
I
I
I
T

* Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the

Recommended Operating Conditions.

CC
in
out

in
out
CC

stg

RECOMMENDED OPERATING CONDITIONS

Symbol Parameter Limits Unit

V

CC

V

in

V

out

T

A

ESD Static Discharge Voltage > 1500 V

DC Supply Voltage Referenced to GND –0.5 to 7.0 V
DC Input Voltage (Referenced to GND) –0.5 to VCC +0.5 V
DC Output Voltage (Referenced to GND) –0.5 to VCC +0.5 V
DC Input Current, Per Pin ±20 mA
DC Output Sink/Source Current, Per Pin ±50 mA
DC VCC or GND Current Per Output Pin ±50 mA
Storage Temperature –65 to +150 °C

Supply Voltage 5.0 ±10% V
DC Input Voltage 0 to V
DC Output Voltage 0 to V
Ambient Operating Temperature –40 to 85 °C

CC
CC

V
V

DC CHARACTERISTICS (TA = –40°C to +85°C; VCC = 5.0V ± 5%)

Symbol Parameter V

V

IH

V

IL

V

OH

V

OL

I

IN

I

CCT

I

OLD

I

OHD

I

CC

1. IOL is +12mA for the RST_OUT output.

2. The PLL_EN input pin is not guaranteed to meet this specification.

3. Maximum test duration 2.0ms, one output loaded at a time.

Minimum High Level Input Voltage 4.75

Minimum Low Level Input Voltage 4.75

Minimum High Level Output Voltage 4.75

Minimum Low Level Output Voltage 4.75

Maximum Input Leakage Current 5.25 ±1.0 µA VI = VCC, GND
Maximum ICC/Input 5.25 2.0
Minimum Dynamic3 Output Current 5.25 88 mA V

Maximum Quiescent Supply Current 5.25 750 µA VI = VCC, GND

CC

5.25

5.25

5.25

5.25

5.25 –88 mA V

Guaranteed Limits Unit Condition

2.0

2.0

0.8

0.8

4.01

4.51

0.44

0.44

2

V V

V V

V VIN = VIH or V

V VIN = VIH or V

mA VI = VCC – 2.1V

= 0.1V or

OUT

VCC – 0.1V

= 0.1V or

OUT

VCC – 0.1V

I

OH –36mA

I

OH +36mA

OLD
OHD

–36mA

+36mA

= 1.0V Max

= 3.85 Min

IL

IL

1

TIMING SOLUTIONS
BR1333 — REV 5

3 MOTOROLA

MC88916

RST

_OUT

RST_IN

SYNC

PLL_EN

LOCK INDICAT OR AND

RESET_OUT 1024 CYCLE

COUNT CIRCUITRY

PFD

POWER–ON

RESET

CH

PUMP

01

VCO

2X_Q

D Q0

D Q1

D Q2

D Q3

D Q/2

Q

Q

R

Q

Q

R

Q

Q

R

Q

Q

R

Q

Q

R

MR

Figure 1. MC88916 Logic Block Diagram

SYNC INPUT TIMING REQUIREMENTS

Symbol Parameter Minimum Maximum Unit

t

RISE/FALL

SYNC Input
t

, Input Clock Period

CYCLE

SYNC Input SYNC Input
Duty Cycle Duty Cycle, SYNC Input 50% ± 25%

Rise/Fall Time, SYNC Input
From 0.8V to 2.0V

— 5.0 ns

‘DW70 ‘DW80

57 50 200 ns

FREQUENCY SPECIFICATIONS (TA = –40°C to +85°C; VCC = 5.0V ± 5%)

Guaranteed Minimum

Symbol Parameter MC88916DW70 MC88916DW80 Unit

Fmax (2X_Q) Maximum Operating Frequency, 2X_Q Output 70 80 MHz
Fmax (‘Q’) Maximum Operating Frequency, Q0–Q2, Q3 Outputs 35 40 MHz

1. Maximum Operating Frequency is guaranteed with the 88916 in a phase–locked condition, and all outputs loaded at 50Ω terminated to VCC/2.

MOTOROLA TIMING SOLUTIONS

4

BR1333 — REV 5

MC88916

AC CHARACTERISTICS (TA = –40°C to +85°C; VCC = 5.0V ± 5%)

Symbol Parameter Mimimum Maximum Unit Condition

t

RISE/FALL

All Outputs
t

RISE/FALL

2X_Q Output
t

pulse width(a)

(Q0, Q1, Q2, Q3)
t

pulse width(b)

(2X_Q Output)

t

PD

SYNC – Q/2

t

SKEWr

(Rising)

t

SKEWf

(Falling)

t

SKEWall

t

LOCK

t

PHL

t

REC

SYNC
tW, MR LOW
tW, RST_IN LOW Minimum Pulse Width, RST_IN Low 10 — ns When in Phase–Lock
t

PZL

t

PLZ

1. These specifications are not tested, they are guaranteed by statistical characterization. See Application Note 1 for a discussion of this
methodology.

2. Under equally loaded conditions and at a fixed temperature and voltage.

3. With VCC fully powered–on: t

4. See Application Note 4 for the distribution in time of each output referenced to SYNC.

5. Limits do not meet requirements of the 68040 microprocessor. Refer to the 88920 for a low frequency 68040 clock driver.

6. Specification is valid only when the PLL_EN pin is low.

7. This is a typical specification only, worst case guarantees are not provided.

1

1

1,4

1,2

1,2

1,2

3

MR – Q Propagation Delay,

, MR to

6

6

Rise/Fall Time, All Outputs into a 50Ω
Load

Rise/Fall Time into a 20pF Load, With
Termination Specified in AppNote 3

1

Output Pulse Width
Q0, Q1, Q2, Q3 at VCC/2

1

Output Pulse Width 40–49MHz
2X_Q at VCC/2 50–65MHz

SYNC Input to Q/2 Output Delay
(Measured at SYNC and Q/2 Pins)

Output–to–Output Skew
Between Outputs Q0–Q2, Q/2
(Rising Edge Only)

Output–to–Output Skew
Between Outputs Q0–Q2
(Falling Edge Only)

Output–to–Output Skew
2X_Q, Q/2, Q0–Q2 Rising
Q3

Falling

Phase–Lock Acquisition Time,
All Outputs to SYNC Input

MR

to Any Output (High–Low)

Reset Recovery Time rising MR edge
to falling SYNC edge

Minimum Pulse Width, MR input Low 5 — ns

Output Enable Time
RST

_IN Low to RST_OUT Low

Output Enable Time
RST_IN High to RST_OUT High Z

CLOCK

66–80MHz

Max is with C1 = 0.1µF; t

0.3 1.6 ns t

0.5 1.6 ns t

0.5t

0.5t

0.5t

0.5t

1016 ‘Q’ Cycles

(508 Q/2 Cycles)

LOCK

– 0.5 0.5t

cycle

5

– 1.5

cycle

– 1.0

cycle

– 0.5

cycle

–0.75 –0.15 ns With 1MΩ From RC1

7

+1.25

— 500 ps Into a 50Ω Load

— 1.0 ns Into a 50Ω Load

— 1.0 ns Into a 50Ω Load

1 10 ms

1.5 13.5 ns Into a 50Ω Load

9 — ns

1.5 16.5 ns See Application

Min is with C1 = 0.01µF.

0.5t

5

0.5t

0.5t

1024 ‘Q’ Cycles

(512 Q/2 Cycles)

+ 0.5 ns 50Ω Load Terminated to

cycle

5

+ 1.5

cycle
cycle

cycle

+3.25

+ 1.0

+ 0.5

7

5

RISE

t

FALL
RISE

t

FALL

VCC/2 (See App Note 3)

ns 50Ω Load Terminated to

VCC/2 (See App Note 3)

to An V
(See Application Note 2)

ns With 1MΩ From RC1

to An GND
(See Application Note 2)

Terminated to VCC/2
(See Timing Diagram in
Figure 6)

Terminated to VCC/2
(See Timing Diagram in
Figure 6)

Terminated to VCC/2
(See Timing Diagram in
Figure 6)

Terminated to VCC/2
(See Timing Diagram in
Figure 6)

Note 5

ns See Application

Note 5

– 0.8V to 2.0V
– 2.0V to 0.8V

– 0.8V to 2.0V
– 2.0V to 0.8V

CC

TIMING SOLUTIONS
BR1333 — REV 5

5 MOTOROLA

MC88916

Application Notes

1. Several specifications can only be measured when the
MC88916 is in phase–locked operation. It is not possible
to have the part in phase–lock on ATE (automated test
equipment). Statistical characterization techniques were
used to guarantee those specifications which cannot be
measured on the ATE. MC88916 units were fabricated
with key transistor properties intentionally varied to create
a 14 cell designed experimental matrix. IC performance
was characterized over a range of transistor properties
(represented by the 14 cells) in excess of the expected
process variation of the wafer fabrication area. IC
performance to each specification and fab variation were
used to set performance limits of ATE testable
specifications within those which are to be guaranteed by
statistical characterization. In this way, all units passing
the ATE test will meet or exceed the non–tested
specifications limits.

2. A 1MΩ resistor tied to either Analog VCC or Analog GND,
as shown in Figure 2, is required to ensure no jitter is
present on the MC88916 outputs. This technique causes
a phase offset between the SYNC input and the Q0
output, measured at the pins. The tPD spec describes how
this offset varies with process, temperature, and voltage.
The specs were arrived at by measuring the phase
relationship for the 14 lots described in note 1 while the
part was in phase–locked operation. The actual
measurements were made with a 10MHz SYNC input
(1.0ns edge rate from 0.8V to 2.0V). The phase
measurements were made at 1.5V. See Figure 2 for a
graphical description.

3. The pulse width spec for the Q and 2Q_X outputs is
referenced to a VCC/2 threshold. T o translate this down to
a 1.5V reference with the same pulse width tolerance, the
termination scheme pictured in Figure 3 must be used.
This termination scheme is required to drive the PCLK
input of the 68040 microprocessor with the 88916 outputs.

4. The tPD spec (SYNC to Q/2) guarantees how close the
Q/2 output will be locked to the reference input connected
to the SYNC input (including temperature and voltage
variation). This also tells what the skew from the Q/2
output on one part connected to a given reference input, to
the Q/2 output on one or more parts connected to that
reference input (assuming equal delay from the reference
input to the SYNC input of each part). Therefore the t

PD

spec is equivalent to a part–to–part specification.
However, to correctly predict the skew from a given output
on one part to any other output on one or more other parts,
the distribution of each output in relation to the SYNC
input must be known. This distribution for the MC88916 is
provided in Table 1.

TABLE 1. Distribution of Each Output versus SYNC

Output –(ps) +(ps)

2X_Q

Q0
Q1
Q2
Q3

Q/2

TBD
TBD
TBD
TBD
TBD
TBD

TBD
TBD
TBD
TBD
TBD
TBD

RC1

EXTERNAL

LOOP FILTER

WITH THE 1M
SPECIFICA TION, MEASURED AT THE INPUT PINS IS:

Ω

tPD = 2.25ns

SYNC INPUT

Q0 OUTPUT

330

Ω

R2

0.1µF

RESISTOR TIED IN THIS FASHION THE T

±

1.0ns (TYPICAL VALUES)

2.25ns

OFFSET

C1

ANALOG GND

1M
REFERENCE
RESISTOR

3V

Figure 2. Depiction of the Fixed SYNC to Q0 Offset (tPD) Which Is Present

When a 1MΩ Resistor Is Tied to VCC or Ground

5V

PD

ANALOG V

REFERENCE

WITH THE 1M
SPECIFICA TION, MEASURED AT THE INPUT PINS IS:

Ω

SYNC INPUT

Q0 OUTPUT

1M

RESISTOR

RESISTOR TIED IN THIS FASHION THE T

tPD = –0.80ns

CC

RC1

330

Ω

R2

0.1µF

ANALOG GND

±

0.30ns

–0.8ns

OFFSET

C1

5V

PD

3V

MOTOROLA TIMING SOLUTIONS

6

BR1333 — REV 5

MC88916

RST_OUT PIN

INTERNAL

LOGIC

C

ANALOG GND

Figure 4. RST_OUT Test Circuit

SYNC Input

Zo (CLOCK

Ω

TRACE)

R

88916

2X_Q

OUTPUT

Rs

Rs = Zo – 7

Figure 3. MC68040 PCLK Input T ermination Scheme

V

CC

1K

L

16.5MHz

CRYSTAL

OSCILLA TOR

SYNC

MR
PLL_EN
RST

Figure 5. Logical Representation of the MC88916 With

Input/Output Frequency Relationships

P

RP = 1.5Zo

_IN

68040
PCLK

CLOCK

INPUT

RST

2X_Q

Q0
Q1
Q2

Q3

Q/2

_OUT

66MHz PCLK OUTPUT

33MHz

B–CLOCK

AND SYSTEM

OUTPUTS

Q0–Q2 Outputs

Q3

Output

2X_Q Output

Q/2 Output

t

SYNC Input

CYCLE

t

SKEWall

t

SKEWf

t

SKEWr

t

t

CYCLE

SKEWf

‘Q’ Outputs

Figure 6. Output/Input Switching Waveforms and Timing Relationships

t

SKEWr

Timing Notes

1. The MC88916 aligns rising edges of the outputs and the SYNC input, therefore the SYNC input does not require a 50%
duty cycle.

2. All skew specs are measured between the VCC/2 crossing point of the appropriate output edges. All skews are specified as
‘windows’, not as a ± deviation around a center point.

TIMING SOLUTIONS
BR1333 — REV 5

7 MOTOROLA

MC88916

The tPD spec includes the full temperature range from 0°C
to 70°C and the full VCC range from 4.75V to 5.25V . If the
∆T and ∆VCC in a given system are less than the
specification limits, the tPD spec window will be reduced.
The tPD window for a given ∆T and ∆VCC is given by the
following regression formula:

TBD

Notes Concerning Loop Filter and Board Layout Issues

1. Figure 7 shows a loop filter and analog isolation scheme
which will be effective in most applications. The following
guidelines should be followed to ensure stable and
jitter–free operation:

1a. All loop filter and analog isolation components should be

tied as close to the package as possible. Stray current
passing through the parasitics of long traces can cause
undesirable voltage transients at the RC1 pin.

1b. The 47Ω resistors, the 10µF low frequency bypass

capacitor, and the 0.1µF high frequency bypass capacitor
form a wide bandwidth filter that will make the 88916 PLL
insensitive to voltage transients from the system digital
VCC supply and ground planes. This filter will typically
ensure that a 100mV step deviation on the digital V
supply will cause no more than a 100ps phase deviation
on the 88916 outputs. A 250mV step deviation on V
using the recommended filter values will cause no more
than a 250ps phase deviation; if a 25µF bypass capacitor
is used (instead of 10µF) a 250mV VCC step will cause no
more than a 100ps phase deviation.

If good bypass techniques are used on a board design
near components which may cause digital VCC and
ground noise, the above described VCC step deviations
should not occur at the 88916’s digital VCC supply. The
purpose of the bypass filtering scheme shown in Figure 7

CC
CC

5. The RST

_OUT pin is an open drain N–Channel output.
Therefore an external pull–up resistor must be provide to
pull up the RST

_OUT pin when it goes into the high
impedance state (after the MC88916 is phase–locked to
the reference input with RST
cycles after the RST
locked). In the t

_IN pin goes high when the part is

and t

PLZ

_IN held high or 1024 ‘Q’

specifications, a 1KΩ resistor

PZL

is used as a pull–up as shown in Figure 4.

is to give the 88916 additional protection from the power
supply and ground plane transients that can occur in a
high frequency, high speed digital system.

1c. There are no special requirements set forth for the loop

filter resistors (1M and 330Ω). The loop filter capacitor
(0.1uF) can be a ceramic chip capacitor, the same as a
standard bypass capacitor.

1d. The 1M reference resistor injects current into the internal

charge pump of the PLL, causing a fixed offset between
the outputs and the SYNC input. This also prevents
excessive jitter caused by inherent PLL dead–band. If the
VCO (2X_Q output) is running above 40MHz, the 1M
resistor provides the correct amount of current injection
into the charge pump (2–3µA). If the VCO is running
below 40MHz, a 1.5MΩ reference resistor should be
used.

2. In addition to the bypass capacitors used in the analog
filter of Figure 7, there should be a 0.1µF bypass
capacitor between each of the other (digital) four V

CC

pins and the board ground plane. This will reduce output
switching noise caused by the 88916 outputs, in addition
to reducing potential for noise in the ‘analog’ section of
the chip. These bypass capacitors should also be tied as
close to the 88916 package as possible.

BOARD V

CC

47

Ω

5

10µF LOW

FREQ BIAS

0.1µF HIGH
FREQ BIAS

1M

Ω

Ω

47

BOARD GND

ANALOG V

Ω

330

6

RC1

0.1µF (LOOP
FILTER CAP)

A SEPARATE ANALOG POWER SUPPLY IS NOT NECESSARY AND
SHOULD NOT BE USED. FOLLOWING THESE PRESCRIBED GUIDE­LINES IS ALL THAT IS NECESSAR Y TO USE THE MC88916 IN A NORMAL
DIGITAL ENVIRONMENT.

7

ANALOG GND

CC

ANALOG LOOP FILTER/VCO
SECTION OF THE MC88916
20–PIN SOIC PACKAGE (NOT
DRAWN TO SCALE)

Figure 7. Recommended Loop Filter and Analog Isolation Scheme for the MC88916

MOTOROLA TIMING SOLUTIONS

8

BR1333 — REV 5

OUTLINE DIMENSIONS

PLASTIC SOIC PACKAGE

CASE 751D–04

–A

–

1120

–B

P 10 PL

–

110

D

20 PL

0.010 (0.25) T A B

M

S S

C

G 18 PL

K

–T

SEATING

–

PLANE

0.010 (0.25)

J

F

DW SUFFIX

ISSUE E

M M

B

M

R X 45°

MC88916

NOTES:

1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.150
(0.006) PER SIDE.

5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.13
(0.005) TOTAL IN EXCESS OF D DIMENSION
AT MAXIMUM MATERIAL CONDITION.

MILLIMETERS INCHES

MIN MINMAX MAX

DIM

12.65

A

7.40

B

2.35

C

0.35

D

0.50

F

1.27 BSC 0.050 BSC

G

0.25

J

0.10

K

0

M

°

P

10.05

R

0.25

12.95

7.60

2.65

0.49

0.90

0.32

0.25
7

10.55

0.75

0.499

0.510

0.292

0.299

0.093

0.104

0.014

0.019

0.020

0.035

0.010

0.012

0.004

0.009

0

7

°

°

°

0.395

0.010

0.415

0.029

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty , representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “T ypical” parameters can and do vary in different
applications. All operating parameters, including “T ypicals” must be validated for each customer application by customer’s technical experts. Motorola does
not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in
systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of
the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such
unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless
against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part.
Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.

How to reach us:
USA/EUROPE: Motorola Literature Distribution; JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, Toshikatsu Otsuki,

P.O. Box 20912; Phoenix, Arizona 85036. 1–800–441–2447 6F Seibu–Butsuryu–Center, 3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 03–3521–8315

MFAX: [e-mail] –TOUCHTONE (602) 244–6609 HONG KONG: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park,
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TIMING SOLUTIONS
BR1333 — REV 5

◊

CODELINE

9 MOTOROLA

*MC88916/D*

MC88916/D