The MC74VHCU04 is an advanced high speed CMOS unbuffered inverter
fabricated with silicon gate CMOS technology. It achieves high speed
operation similar to equivalent Bipolar Schottky TTL while maintaining
CMOS low power dissipation.
The inputs tolerate voltages up to 7V , allowing the interface of 5V systems
to 3V systems.
• High Speed: tPD = 3.5ns (Typ) at VCC = 5V
• Low Power Dissipation: ICC = 2µA (Max) at TA = 25°C
• High Noise Immunity: V
• Power Down Protection Provided on Inputs
• Balanced Propagation Delays
• Designed for 2V to 5.5V Operating Range
• Low Noise: V
= 0.8V (Max)
OLP
• Pin and Function Compatible with Other Standard Logic Families
• Latchup Performance Exceeds 300mA
• ESD Performance: HBM > 2000V; Machine Model > 200V
• Chip Complexity: 12 FETs or 3 Equivalent Gates
1
3
A2
NIH
= V
= 10% VCC (Min.)
NIL
LOGIC DIAGRAM
2
4
Y1A1
Y2
D SUFFIX
14–LEAD SOIC PACKAGE
CASE 751A–03
14–LEAD TSSOP PACKAGE
14–LEAD SOIC EIAJ PACKAGE
MC74VHCUXXD
MC74VHCUXXDT
MC74VHCUXXM
DT SUFFIX
CASE 948G–01
M SUFFIX
CASE 965–01
ORDERING INFORMATION
SOIC
TSSOP
SOIC EIAJ
10
12
6
Y3
Y = A
8
Y4
Y5
Y6
A3
A4
A5
A6
5
9
11
13
Pinout: 14–Lead Packages (Top View)
VCCA6Y6
131412111098
2134567
A1Y1A2Y2A3Y3GND
A5Y5A4Y4
FUNCTION TABLE
InputsOutputs
A
L
H
Y
H
L
6/97
Motorola, Inc. 1997
1
REV 0
Page 2
MC74VHCU04
Î
Î
Î
Î
ÎÎÎ
ÎÎÎ
V
CC
Î
Î
Î
Î
Î
Î
ÎÎÎ
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
ÎÎÎ
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
ÎÎÎ
Î
Î
Î
Î
Î
Î
Î
Î
ÎÎÎ
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
ÎÎÎ
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
ÎÎÎ
Î
Î
Î
MAXIMUM RATINGS*
Symbol
V
V
I
I
I
Î
T
DC Supply Voltage
CC
V
DC Input Voltage
in
DC Output Voltage
out
I
Input Diode Current
IK
Output Diode Current
OK
DC Output Current, per Pin
out
DC Supply Current, VCC and GND Pins
CC
P
Power Dissipation in Still Air,SOIC Packages†
D
ОООООООООООО
Storage Temperature
stg
* Absolute maximum continuous ratings are those values beyond which damage to the device
may occur. Exposure to these conditions or conditions beyond those indicated may adversely
affect device reliability . Functional operation under absolute–maximum–rated conditions is not
implied.
†Derating — SOIC Packages: – 7 mW/_C from 65_ to 125_C
TSSOP Package: – 6.1 mW/_C from 65_ to 125_C
RECOMMENDED OPERATING CONDITIONS
Symbol
V
V
V
T
DC Supply Voltage
CC
DC Input Voltage
in
DC Output Voltage
out
Operating Temperature
A
Parameter
Parameter
TSSOP Package†
Value
–0.5 to + 7.0
–0.5 to + 7.0
–0.5 to VCC + 0.5
–20
± 20
± 25
± 50
500
450
ÎÎÎÎ
– 65 to + 150
Min
Max
2.0
5.5
0
5.5
0
V
CC
–40
+ 85
Unit
V
V
V
mA
mA
mA
mA
mW
Î
_
C
Unit
V
V
V
_
C
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance circuit. For proper operation, Vin and
V
should be constrained to the
out
range GND v (Vin or V
Unused inputs must always be
) v VCC.
out
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
DC ELECTRICAL CHARACTERISTICS
Symbol
V
IH
ÎÎ
ÎÎ
V
IL
ÎÎ
ÎÎ
V
OH
ÎÎ
ÎÎ
ÎÎ
V
OL
ÎÎ
ÎÎ
ÎÎÎÎÎÎÎÎОООООО
Parameter
Minimum High–Level
ÎÎÎÎ
Input Voltage
ÎÎÎÎ
Maximum Low–Level
ÎÎÎÎ
Input Voltage
ÎÎÎÎ
Minimum High–Level
Output Voltage
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
Maximum Low–Level
ÎÎÎÎ
Output Voltage
ÎÎÎÎ
Test Conditions
ОООООО
ОООООО
ОООООО
ОООООО
Vin =V
IL
IOH = –50µA
ОООООО
Vin = GND
ОООООО
ОООООО
Vin = V
ОООООО
IOL = 50µA
ОООООО
Vin = V
IOH = –4mA
IOH = –8mA
IH
CC
IOL = 4mA
IOL = 8mA
V
V
2.0
ÎÎ
3.0 to
5.5
ÎÎ
2.0
ÎÎ
3.0 to
5.5
ÎÎ
2.0
3.0
ÎÎ
4.5
3.0
ÎÎ
4.5
ÎÎ
2.0
ÎÎ
3.0
4.5
ÎÎ
3.0
ÎÎ
4.5
TA = 25°C
Min
Typ
Max
1.70
ÎÎ
VCC x 0.8
ÎÎ
ÎÎ
ÎÎ
1.8
2.7
ÎÎ
4.0
2.58
ÎÎ
3.94
ÎÎ
ÎÎ
ÎÎ
ÎÎÎÎÎÎÎ
Î
Î
Î
Î
2.0
3.0
Î
4.5
Î
Î
0.0
Î
0.0
0.0
Î
ÎÎ
ÎÎ
0.30
ÎÎ
VCC x 0.2
ÎÎ
ÎÎÎÎÎ
ÎÎ
ÎÎ
0.2
ÎÎ
0.3
0.5
ÎÎ
0.36
0.36
TA = –40 to 85°C
Min
Max
1.70
ÎÎ
VCC x 0.8
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
0.30
ÎÎ
VCC x 0.2
ÎÎ
1.8
2.7
4.0
2.48
ÎÎ
3.80
ÎÎ
ÎÎ
ÎÎ
ÎÎÎÎÎ
ÎÎ
ÎÎ
ÎÎ
0.2
ÎÎ
0.3
0.5
ÎÎ
0.44
0.44
Unit
V
V
V
V
MOTOROLAVHC Data – Advanced CMOS Logic
2
DL203 — Rev 0
Page 3
DC ELECTRICAL CHARACTERISTICS
ÎÎÎ
ÎÎÎ
Î
Î
Î
ÎÎÎ
Î
Î
Î
Î
Î
Î
ÎÎÎ
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Symbol
Symbol
I
in
ÎÎ
I
CC
ÎÎ
Parameter
Parameter
Maximum Input
ÎÎÎÎ
Leakage Current
Maximum Quiescent
Supply Current
ÎÎÎÎ
Test Conditions
Test Conditions
Vin = 5.5 or GND
ОООООО
Vin = VCC or GND
ОООООО
V
V
CC
CC
V
V
0 to 5.5
ÎÎ
5.5
ÎÎ
TA = 25°C
Min
Typ
Max
± 0.1
ÎÎÎÎÎÎÎ
2.0
ÎÎÎÎÎÎÎ
MC74VHCU04
TA = –40 to 85°C
Min
ÎÎÎÎÎ
ÎÎÎÎÎ
Max
± 1.0
20.0
Unit
Unit
µA
µA
AC ELECTRICAL CHARACTERISTICS (Input t
Symbol
t
,
PLH
t
ÎÎ
PHL
ÎÎÎООООООÎООООООО
C
ÎÎ
Maximum Propagation Delay,
A or B to Y
Maximum Input Capacitance
in
Parameter
ОООООО
ОООООО
= tf = 3.0ns)
r
TA = 25°C
Test Conditions
VCC = 3.3 ± 0.3VCL = 15pF
ООООООО
CL = 50pF
VCC = 5.0 ± 0.5VCL = 15pF
CL = 50pF
ОООООООÎÎÎÎÎ
Min
Typ
5.0
ÎÎÎÎ
7.5
3.5
ÎÎÎÎ
5.0
5
Max
8.9
11.4
ÎÎ
5.5
7.0
ÎÎ
10
ÎÎ
TA = –40 to 85°C
Min
1.0
1.0
Î
1.0
1.0
Î
ÎÎÎÎ
Max
10.5
13.0
ÎÎ
6.5
8.0
ÎÎ
10
Unit
ns
pF
Typical @ 25°C, VCC = 5.0V
C
PD
Power Dissipation Capacitance (Per Inverter) (Note NO T AG)
9
pF
1. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: I
dynamic power consumption; PD = CPD V
NOISE CHARACTERISTICS (Input t
= tf = 3.0ns, CL = 50pF, VCC = 5.0V)
r
CC
2
CC(OPR
fin + ICC VCC.
= CPD VCC fin + ICC/6 (per buffer). CPD is used to determine the no–load
)
TA = 25°C
SymbolCharacteristic
V
V
V
V
OLP
OLV
IHD
ILD
Quiet Output Maximum Dynamic V
Quiet Output Minimum Dynamic V
OL
OL
Minimum High Level Dynamic Input Voltage4.0V
Maximum Low Level Dynamic Input Voltage1.0V
TypMax
0.50.8V
–0.5–0.8V
Unit
A
50%
50% V
Y
CC
Figure 1. Switching Waveforms
VHC Data – Advanced CMOS LogicDL203 — Rev 0
V
CC
GND
t
PLH
t
PHL
Parasitic Diode
INPUTOUTPUT
Parasitic Diode
Figure 3. Input Equivalent Circuit
3MOTOROLA
TEST POINT
OUTPUT
DEVICE
UNDER
TEST
CL*
*Includes all probe and jig capacitance
Figure 2. T est Circuit
Page 4
MC74VHCU04
1
SEATING
PLANE
–A–
G
D14 PL
0.25 (0.010)T BA
OUTLINE DIMENSIONS
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751A–03
ISSUE F
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
814
P 7 PL
–B–
MM
7
X 45°
C
R
K
M
SS
B0.25 (0.010)
M
J
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
F
MILLIMETERSINCHES
MINMINMAXMAX
DIM
A
B
C
D
F
G
J
K
M
P
R
8.75
8.55
4.00
3.80
1.75
1.35
0.49
0.35
1.25
0.40
1.27 BSC0.050 BSC
0.25
0.19
0.25
0.10
7
0
°
°
5.80
6.20
0.25
0.50
0.337
0.150
0.054
0.014
0.016
0.008
0.004
0.228
0.010
0.344
0.157
0.068
0.019
0.049
0.009
0.009
7
0
°
°
0.244
0.019
0.10 (0.004)
SEATING
–T–
PLANE
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948G–01
ISSUE O
14X REFK
S
U
T
S
N
0.25 (0.010)
U0.15 (0.006) T
S
2X L/2
0.10 (0.004)V
14
M
8
M
L
PIN 1
IDENT.
1
S
U0.15 (0.006) T
A
–V–
B
–U–
N
F
7
DETAIL E
K
K1
J
J1
SECTION N–N
C
D
G
H
DETAIL E
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED
0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE –W–.
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH OR PROTRUSIONS AND ARE MEASURED
Q
1
c
AT THE PARTING LINE. MOLD FLASH OR
PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006)
PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
MILLIMETERS
DIMMINMAXMINMAX
–––2.05–––0.081
A
A
0.050.200.0020.008
1
0.350.500.0140.020
b
0.180.270.0070.011
c
9.9010.500.3900.413
D
5.105.450.2010.215
E
1.27 BSC0.050 BSC
e
H
7.408.200.2910.323
E
0.500.850.0200.033
0.50
L
1.101.500.0430.059
E
0
M
_
Q
0.700.900.0280.035
1
–––1.42–––0.056
Z
10
INCHES
10
0
_
_
_
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty , representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. “T ypical” parameters which may be provided in Motorola
data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”
must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of
others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other
applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury
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arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
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Opportunity/Affirmative Action Employer.
Mfax is a trademark of Motorola, Inc.
How to reach us:
USA/EUROPE/Locations Not Listed: Motorola Literature Distribution;JAPAN: Nippon Motorola Ltd.: SPD, Strategic Planning Office, 4–32–1,
P.O. Box 5405, Denver, Colorado 80217. 303–675–2140 or 1–800–441–2447Nishi–Gotanda, Shinagawa–ku, Tokyo 141, Japan. 81–3–5487–8488
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INTERNET: http://motorola.com/sps
VHC Data – Advanced CMOS Logic
◊
5MOTOROLA
MC74VHCU04/D
DL203 — Rev 0
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